Support 256-bit DataBusWidth in PCIe

[hanw]

• Support gen3 core completer interface
• Support gen3 core requester interface up to 128 bits
• Extend MemToPcie to 256 bits
• Extend gen3 core requester interface to 256 bits
• Merge back to master

[hanw]

Simulation is easy, I submited a patch.

[jameyhicks]

With your Bluesim patch, you can verify that everything in mkConnectalTop for your design works with DataBusWidth=256.

Working out from there, I would make a test bench that you can send/receive TLPs from software, and in the hardware side of the testbench connect MemMasterEngine and MemSlaveEngine to your mkConnectalTop.

Once that is working, incorporate the simulation model for the PCIe core and send/receive TLPS via its PIPE interface.

Once that is working, it should just work on the hardware.