From 39f73f28d06ff65e811e39aa0858a141c699b8bb Mon Sep 17 00:00:00 2001
From: "Lee, Sang Ik" <sang.ik.lee@intel.com>
Date: Wed, 10 Jan 2024 17:48:42 -0800
Subject: [PATCH] Fix macro names of headers to follow MLIR standard.

---
 mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h         | 6 +++---
 mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.td        | 6 +++---
 mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td   | 6 +++---
 mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td | 6 +++---
 mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td     | 6 +++---
 mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td   | 6 +++---
 6 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
index 974d52d2419603..a05e046a0e0c0b 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef _XeGPU_OPS_H_INCLUDED_
-#define _XeGPU_OPS_H_INCLUDED_
+#ifndef MLIR_DIALECT_XEGPU_IR_XEGPU_H
+#define MLIR_DIALECT_XEGPU_IR_XEGPU_H
 
 #include <mlir/IR/BuiltinTypes.h>
 #include <mlir/IR/Dialect.h>
@@ -49,4 +49,4 @@ class TensorDescType;
 #define GET_OP_CLASSES
 #include <mlir/Dialect/XeGPU/IR/XeGPU.h.inc>
 
-#endif // _XeGPU_OPS_H_INCLUDED_
+#endif // MLIR_DIALECT_XEGPU_IR_XEGPU_H
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.td
index 3c36ffd80c1e6c..232e962870716c 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.td
@@ -6,9 +6,9 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef _XeGPU_TD_INCLUDED_
-#define _XeGPU_TD_INCLUDED_
+#ifndef MLIR_DIALECT_XEGPU_IR_XEGPU_TD
+#define MLIR_DIALECT_XEGPU_IR_XEGPU_TD
 
 include "mlir/Dialect/XeGPU/IR/XeGPUOps.td"
 
-#endif // _XeGPU_TD_INCLUDED_
+#endif // MLIR_DIALECT_XEGPU_IR_XEGPU_TD
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
index 12d5307142d5e3..84112b8b18a810 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef _XEGPU_ATTRS_TD_INCLUDED_
-#define _XEGPU_ATTRS_TD_INCLUDED_
+#ifndef MLIR_DIALECT_XEGPU_IR_XEGPUATTRS_TD
+#define MLIR_DIALECT_XEGPU_IR_XEGPUATTRS_TD
 
 include "mlir/Dialect/XeGPU/IR/XeGPUDialect.td"
 
@@ -133,4 +133,4 @@ def XeGPU_AtomicRMWKindAttr : I64EnumAttr<
   let cppNamespace = "::mlir::xegpu";
 }
 
-#endif // _XEGPU_ATTRS_TD_INCLUDED_
+#endif // MLIR_DIALECT_XEGPU_IR_XEGPUATTRS_TD
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
index 4f16589e035ab7..ae29f87a8812a7 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef _XEGPU_DIALECT_TD_INCLUDED_
-#define _XEGPU_DIALECT_TD_INCLUDED_
+#ifndef MLIR_DIALECT_XEGPU_IR_XEGPUDIALECT_TD
+#define MLIR_DIALECT_XEGPU_IR_XEGPUDIALECT_TD
 
 include "mlir/IR/OpBase.td"
 include "mlir/IR/OpAsmInterface.td"
@@ -51,4 +51,4 @@ def XeGPUDialect : Dialect {
     let useDefaultAttributePrinterParser = true;
 }
 
-#endif //XEGPU_DIALECT
+#endif // MLIR_DIALECT_XEGPU_IR_XEGPUDIALECT_TD
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
index 8a0afa548b6364..6866f903d715e8 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef _XeGPU_OPS_TD_INCLUDED_
-#define _XeGPU_OPS_TD_INCLUDED_
+#ifndef MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD
+#define MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD
 
 include "mlir/Dialect/XeGPU/IR/XeGPUAttrs.td"
 include "mlir/Dialect/XeGPU/IR/XeGPUDialect.td"
@@ -584,4 +584,4 @@ def XeGPU_MfenceOp
       }];
   }
 
-#endif // _XeGPU_OPS_TD_INCLUDED_
+#endif // MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
index 9380e12defbd6b..8d2f1e769c3049 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef _XEGPU_TYPES_TD_INCLUDED_
-#define _XEGPU_TYPES_TD_INCLUDED_
+#ifndef MLIR_DIALECT_XEGPU_IR_XEGPUTYPES_TD
+#define MLIR_DIALECT_XEGPU_IR_XEGPUTYPES_TD
 
 include "mlir/IR/BuiltinTypes.td"
 
@@ -168,4 +168,4 @@ def XeGPU_Nbarrier: XeGPUTypeDef<"Nbarrier", "nbarrier", [], "mlir::Type"> {
   }];
 }
 
-#endif // _XEGPU_TYPES_TD_INCLUDED_
+#endif // MLIR_DIALECT_XEGPU_IR_XEGPUTYPES_TD