Fix beh_lib.sv syntax error when using RV_FPGA_OPTIMIZE

[olofk]

As was reported in chipsalliance/VeeRwolf#1 , verilator reports a syntax error in beh_lib.sv when using RV_FPGA_OPTIMIZE. Older versions of Verilator parses this fine, but it seems there has been a stricter check introduced somewhere between versions 4.006 and 4.010. I also noticed that Icarus verilog doesn't handle this syntax either. This patch simplifies the expression to work in all cases

[robertgolla]

Actually with that change we will no longer be able to run our testbench to validate that RV_FPGA_OPTIMIZE works or not (hierarchy must match with w/out the RV_FPGA_OPTIMIZE).

Can you try the following:

`ifndef PHYSICAL

if (WIDTH >= 8) begin: genblock

`endif

 rvdffs #(WIDTH) dff ( .* );

`ifndef PHYSICAL

end

`endif

That should work fine.

[olofk]

That seems to work fine. Should I send an updated patch or do you take care of it on your side?

[robertgolla]

I will take care of this from my side tomorrow. Will let you know when it is pushed. Thanks for helping with this.

[robertgolla]

This is now fixed as part of the 1.3 release.