diff --git a/docs/src/appendix/experimental-features.md b/docs/src/appendix/experimental-features.md index dc1dbaa596b..b8a97dd588e 100644 --- a/docs/src/appendix/experimental-features.md +++ b/docs/src/appendix/experimental-features.md @@ -7,19 +7,12 @@ section: "chisel3" Chisel has a number of new features that are worth checking out. This page is an informal list of these features and projects. -- [FixedPoint](#fixed-point) - [Module Variants](#module-variants) - [Bundle Literals](#bundle-literals) - [Vec Literals](#vec-literals) -- [Loading Memories for simulation or FPGA initialization](#loading-memories) +- [Loading-Memories-for-simulation-or-FPGA-initialization](#loading-memories-for-simulation-or-fpga-initialization) - -### FixedPoint -FixedPoint numbers are basic *Data* type along side of UInt, SInt, etc. Most common math and logic operations -are supported. Chisel allows both the width and binary point to be inferred by the Firrtl compiler which can simplify -circuit descriptions. See [FixedPointSpec](https://github.com/freechipsproject/chisel3/tree/master/src/test/scala/chiselTests/FixedPointSpec.scala) - -### Module Variants +## Module Variants The standard Chisel *Module* requires a `val io = IO(...)`, the experimental package introduces several new ways of defining Modules - BaseModule: no contents, instantiable @@ -29,7 +22,7 @@ new ways of defining Modules - RawModule: will be the user-facing version of UserDefinedModule - Module: type-aliases to ImplicitModule, the user-facing version of ImplicitModule. -### Bundle Literals +## Bundle Literals Bundle literals can be constructed via an experimental import: @@ -90,7 +83,7 @@ class Example3 extends RawModule { circt.stage.ChiselStage.emitSystemVerilog(new Example3) ``` -### Vec Literals +## Vec Literals Vec literals are very similar to Bundle literals and can be constructed via an experimental import. They can be constructed in two forms, with type and length inferred as in: @@ -173,6 +166,8 @@ class VecExample5 extends RawModule { circt.stage.ChiselStage.emitSystemVerilog(new VecExample5) ``` +## Loading Memories for simulation or FPGA initialization + ### Inline initialization with external file Memories can be initialized by generating inline `readmemh` or `readmemb` statements in the output Verilog. @@ -210,7 +205,7 @@ class InitMemInline(memoryFile: String = "") extends Module { The default is to use `$readmemh` (which assumes all numbers in the file are in ascii hex), but to use ascii binary there is an optional `hexOrBinary` argument which can be set to `MemoryLoadFileType.Hex` or `MemoryLoadFileType.Binary`. You will need to add an additional import. -#### SystemVerilog Bind Initialization +### SystemVerilog Bind Initialization Chisel can also initialize memories by generating a SV bind module with `readmemh` or `readmemb` statements by using the function `loadMemoryFromFile` from `chisel3.util.experimental`. diff --git a/docs/src/cookbooks/cookbook.md b/docs/src/cookbooks/cookbook.md index 312636f2976..9cda0102814 100644 --- a/docs/src/cookbooks/cookbook.md +++ b/docs/src/cookbooks/cookbook.md @@ -265,8 +265,8 @@ getVerilogString(new Foo) ### How do I partially reset an Aggregate Reg? -The easiest way is to use a partially-specified [Bundle Literal](#../appendix/experimental-features#bundle-literals) -or [Vec Literal](#../appendix/experimental-features#vec-literals) to match the type of the Reg. +The easiest way is to use a partially-specified [Bundle Literal](../appendix/experimental-features#bundle-literals) +or [Vec Literal](../appendix/experimental-features#vec-literals) to match the type of the Reg. ```scala mdoc:silent:reset import chisel3._ @@ -309,7 +309,7 @@ getVerilogString(new MyModule2) ## Bundles -### How do I deal with aliased Bundle fields? +### How do I deal with aliased Bundle fields? ```scala mdoc:invisible:reset import chisel3._ @@ -377,7 +377,9 @@ Note that this also means you must pass `gen` as a function, for example: getVerilogString(new Top(new UsingAFunctionBundle(() => UInt(8.W)))) ``` - **Warning**: you must ensure that `gen` creates fresh objects rather than capturing an already constructed value: +##### Aliased Warning + +**Warning**: you must ensure that `gen` creates fresh objects rather than capturing an already constructed value: ```scala mdoc:crash class MisusedFunctionArguments extends Module { @@ -823,7 +825,11 @@ circt.stage.ChiselStage.emitSystemVerilog(new CountBits(4)) .head + ");\n" ``` +<<<<<<< HEAD ### How do I resolve "Dynamic index ... is too wide/narrow for extractee ..."? +======= +## How do I resolve "Dynamic index ... is too wide/narrow for extractee ..."? +>>>>>>> 946392f5d ([website] Bump Docusaurus to 3.1.1 and fix broken anchors (#3948)) Chisel will warn if a dynamic index is not the correctly-sized width for indexing a Vec or UInt. diff --git a/docs/src/explanations/connectable.md b/docs/src/explanations/connectable.md index 4f66410e3c0..f30a16f083e 100644 --- a/docs/src/explanations/connectable.md +++ b/docs/src/explanations/connectable.md @@ -21,7 +21,7 @@ section: "chisel3" * [Connecting Records](#connecting-records) * [Defaults with waived connections](#defaults-with-waived-connections) * [Connecting types with optional members](#connecting-types-with-optional-members) - * [Always ignore extra members (partial connection operator)](#always-ignore-extra-members-partial-connection-operator) + * [Always ignore extra members (partial connection operator)](#always-ignore-errors-caused-by-extra-members-partial-connection-operator) * [Connecting components with different widths](#connecting-components-with-different-widths) * [Techniques for connecting structurally inequivalent Chisel types](#techniques-for-connecting-structurally-inequivalent-chisel-types) * [Connecting different sub-types of the same super-type, with colliding names](#connecting-different-sub-types-of-the-same-super-type-with-colliding-names) diff --git a/docs/src/explanations/memories.md b/docs/src/explanations/memories.md index ae996c303af..dd95d446ae2 100644 --- a/docs/src/explanations/memories.md +++ b/docs/src/explanations/memories.md @@ -198,7 +198,7 @@ class MaskedRWSmem extends Module { Chisel memories can be initialized from an external `binary` or `hex` file emitting proper Verilog for synthesis or simulation. There are multiple modes of initialization. -For more information, check the experimental docs on [Loading Memories](../appendix/experimental-features#loading-memories) feature. +For more information, check the experimental docs on [Loading Memories](../appendix/experimental-features#loading-memories-for-simulation-or-fpga-initialization) feature. ## SRAM @@ -251,4 +251,4 @@ class TopModule extends Module { mem.readwritePorts(2).isWrite := false.B val bar = WireInit(UInt(8.W), mem.readwritePorts(2).readData) } -``` \ No newline at end of file +``` diff --git a/docs/src/explanations/warnings.md b/docs/src/explanations/warnings.md index 24af2fa83b0..559016ad9e8 100644 --- a/docs/src/explanations/warnings.md +++ b/docs/src/explanations/warnings.md @@ -118,25 +118,25 @@ See the [ChiselEnum explanation](chisel-enum#casting) for more information and h This warning occurs when dynamically indexing a `UInt` or an `SInt` with an index that is wider than necessary to address all bits in the indexee. It indicates that some of the high-bits of the index are ignored by the indexing operation. -It can be fixed as described in the [Cookbook](../cookbooks/cookbook#dynamic-index-too-wide-narrow). +It can be fixed as described in the [Cookbook](../cookbooks/cookbook#how-do-i-resolve-dynamic-index--is-too-widenarrow-for-extractee-). ### [W003] Dynamic bit select too narrow This warning occurs when dynamically indexing a `UInt` or an `SInt` with an index that is to small to address all bits in the indexee. It indicates that some bits of the indexee cannot be reached by the indexing operation. -It can be fixed as described in the [Cookbook](../cookbooks/cookbook#dynamic-index-too-wide-narrow). +It can be fixed as described in the [Cookbook](../cookbooks/cookbook#how-do-i-resolve-dynamic-index--is-too-widenarrow-for-extractee-). ### [W004] Dynamic index too wide This warning occurs when dynamically indexing a `Vec` with an index that is wider than necessary to address all elements of the `Vec`. It indicates that some of the high-bits of the index are ignored by the indexing operation. -It can be fixed as described in the [Cookbook](../cookbooks/cookbook#dynamic-index-too-wide-narrow). +It can be fixed as described in the [Cookbook](../cookbooks/cookbook#how-do-i-resolve-dynamic-index--is-too-widenarrow-for-extractee-). ### [W005] Dynamic index too narrow This warning occurs when dynamically indexing a `Vec` with an index that is to small to address all elements in the `Vec`. It indicates that some elements of the `Vec` cannot be reached by the indexing operation. -It can be fixed as described in the [Cookbook](../cookbooks/cookbook#dynamic-index-too-wide-narrow). +It can be fixed as described in the [Cookbook](../cookbooks/cookbook#how-do-i-resolve-dynamic-index--is-too-widenarrow-for-extractee-). ### [W006] Extract from Vec of size 0 diff --git a/docs/src/resources/faqs.md b/docs/src/resources/faqs.md index d589d7b1157..a1877d976f3 100644 --- a/docs/src/resources/faqs.md +++ b/docs/src/resources/faqs.md @@ -8,7 +8,7 @@ section: "chisel3" * [Where should I start if I want to learn Chisel?](#where-should-i-start-if-i-want-to-learn-chisel) * [How do I ... in Chisel?](#how-do-i-do--eg-like-that-in-verilog-in-chisel) -* [What versions of the various projects work together?](#what-versions) +* [What versions of the various projects work together?](#what-versions-of-the-various-projects-work-together) * [How can I contribute to Chisel?](#how-can-i-contribute-to-chisel) * [Why DecoupledIO instead of ReadyValidIO?](#why-decoupledio-instead-of-readyvalidio) * [Why do I have to wrap module instantiations in `Module(...)`?](#why-do-i-have-to-wrap-module-instantiations-in-module) @@ -28,7 +28,7 @@ We recommend the [Chisel Bootcamp](https://github.com/freechipsproject/chisel-bo See the [cookbooks](../cookbooks/cookbook). -### What versions of the various projects work together? +### What versions of the various projects work together? See [Chisel Project Versioning](../appendix/versioning). diff --git a/website/docusaurus.config.js b/website/docusaurus.config.js index 48d08f9f348..08ac299c457 100644 --- a/website/docusaurus.config.js +++ b/website/docusaurus.config.js @@ -46,6 +46,7 @@ const config = { onBrokenLinks: 'throw', onBrokenMarkdownLinks: 'throw', + onBrokenAnchors: 'throw', // Even if you don't use internalization, you can use this field to set useful // metadata like html lang. For example, if your site is Chinese, you may want diff --git a/website/package.json b/website/package.json index c50ce5088b5..7797fbd7fa4 100644 --- a/website/package.json +++ b/website/package.json @@ -13,18 +13,18 @@ "write-heading-ids": "docusaurus write-heading-ids" }, "dependencies": { - "@docusaurus/core": "3.0.0", - "@docusaurus/plugin-client-redirects": "3.0.0", - "@docusaurus/preset-classic": "3.0.0", + "@docusaurus/core": "3.1.1", + "@docusaurus/plugin-client-redirects": "3.1.1", + "@docusaurus/preset-classic": "3.1.1", "@mdx-js/react": "^3.0.0", - "clsx": "^1.2.1", - "prism-react-renderer": "^2.1.0", + "clsx": "^2.0.0", + "prism-react-renderer": "^2.3.0", "react": "^18.0.0", "react-dom": "^18.0.0" }, "devDependencies": { - "@docusaurus/module-type-aliases": "3.0.0", - "@docusaurus/types": "3.0.0" + "@docusaurus/module-type-aliases": "3.1.1", + "@docusaurus/types": "3.1.1" }, "browserslist": { "production": [