From ff01f706fbe161a906163da4e4357d16eb75a727 Mon Sep 17 00:00:00 2001 From: "mergify[bot]" <37929162+mergify[bot]@users.noreply.github.com> Date: Tue, 20 Feb 2024 08:52:06 -0800 Subject: [PATCH] Remove extra bit from `SRAMInterface` address width (#3830) (#3840) (cherry picked from commit 4f1f4a7744f2b9ea217e8c2972c312642755be1b) Co-authored-by: Deborah Soung --- src/main/scala/chisel3/util/SRAM.scala | 2 +- src/test/scala/chiselTests/Mem.scala | 10 +++++----- src/test/scala/chiselTests/util/SRAMSpec.scala | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/main/scala/chisel3/util/SRAM.scala b/src/main/scala/chisel3/util/SRAM.scala index 9ffab068320..b69db7f4c64 100644 --- a/src/main/scala/chisel3/util/SRAM.scala +++ b/src/main/scala/chisel3/util/SRAM.scala @@ -104,7 +104,7 @@ class SRAMInterface[T <: Data]( s"SRAMInterface_${SRAM.portedness(numReadPorts, numWritePorts, numReadwritePorts)}${if (masked) "_masked" else ""}}_${tpe.typeName}" - val addrWidth = log2Up(memSize + 1) + val addrWidth = log2Up(memSize) val readPorts: Vec[MemoryReadPort[T]] = Vec(numReadPorts, new MemoryReadPort(tpe, addrWidth)) val writePorts: Vec[MemoryWritePort[T]] = Vec(numWritePorts, new MemoryWritePort(tpe, addrWidth, masked)) diff --git a/src/test/scala/chiselTests/Mem.scala b/src/test/scala/chiselTests/Mem.scala index a854a0195c7..16330f2584c 100644 --- a/src/test/scala/chiselTests/Mem.scala +++ b/src/test/scala/chiselTests/Mem.scala @@ -529,10 +529,10 @@ class SRAMSpec extends ChiselFunSpec { val chirrtl = ChiselStage.emitCHIRRTL(new TestModule(1, 1), args = Array("--full-stacktrace")) chirrtl should include( - "writePorts : { flip address : UInt<6>, flip enable : UInt<1>, flip data : UInt<8>[3], flip mask : UInt<1>[3]}[1]" + "writePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip data : UInt<8>[3], flip mask : UInt<1>[3]}[1]" ) chirrtl should include( - "readwritePorts : { flip address : UInt<6>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>[3], flip writeData : UInt<8>[3], flip mask : UInt<1>[3]}[1]" + "readwritePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>[3], flip writeData : UInt<8>[3], flip mask : UInt<1>[3]}[1]" ) for (i <- 0 until 3) { @@ -576,13 +576,13 @@ class SRAMSpec extends ChiselFunSpec { val wrIndexSuffix = if (i == 0) "" else s"_$i" chirrtl should include( - s"read mport mem_out_readPorts_${i}_data_MPORT = mem_mem[_mem_out_readPorts_${i}_data_T], readClocks[${i}]" + s"read mport mem_out_readPorts_${i}_data_MPORT = mem_mem[_mem_out_readPorts_${i}_data_WIRE], readClocks[${i}]" ) chirrtl should include( - s"write mport mem_MPORT${wrIndexSuffix} = mem_mem[_mem_T${wrIndexSuffix}], writeClocks[${i}]" + s"write mport mem_MPORT${wrIndexSuffix} = mem_mem[mem.writePorts[${i}].address], writeClocks[${i}]" ) chirrtl should include( - s"rdwr mport mem_out_readwritePorts_${i}_readData_MPORT = mem_mem[_mem_out_readwritePorts_${i}_readData_T], readwriteClocks[${i}]" + s"rdwr mport mem_out_readwritePorts_${i}_readData_MPORT = mem_mem[_mem_out_readwritePorts_${i}_readData_WIRE], readwriteClocks[${i}]" ) } } diff --git a/src/test/scala/chiselTests/util/SRAMSpec.scala b/src/test/scala/chiselTests/util/SRAMSpec.scala index 7a45fa7158a..79974e1d1ea 100644 --- a/src/test/scala/chiselTests/util/SRAMSpec.scala +++ b/src/test/scala/chiselTests/util/SRAMSpec.scala @@ -35,7 +35,7 @@ class SRAMSpec extends ChiselFlatSpec { chirrtl should include("module Top :") chirrtl should include("smem sram_mem : UInt<8> [32]") chirrtl should include( - "wire sram : { readPorts : { flip address : UInt<6>, flip enable : UInt<1>, data : UInt<8>}[0], writePorts : { flip address : UInt<6>, flip enable : UInt<1>, flip data : UInt<8>}[0], readwritePorts : { flip address : UInt<6>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>, flip writeData : UInt<8>}[1]}" + "wire sram : { readPorts : { flip address : UInt<5>, flip enable : UInt<1>, data : UInt<8>}[0], writePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip data : UInt<8>}[0], readwritePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>, flip writeData : UInt<8>}[1]}" ) val dummyAnno = annos.collectFirst { case DummyAnno(t) => (t.toString) }