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Surfing around at the new website I am missing a plain and hopefully simple Getting Started. The Jupiter thing is nice, but a bit slow and also detached from real HW design work. I think we need a super simple example that can be tested (with chiseltest or something new) and generated to Verilog to explore it in an FPGA.
I’d be happy to contribute on this. We just need to agree where to put it (code and document).
Cheers,
Martin
The text was updated successfully, but these errors were encountered:
Surfing around at the new website I am missing a plain and hopefully simple Getting Started. The Jupiter thing is nice, but a bit slow and also detached from real HW design work. I think we need a super simple example that can be tested (with chiseltest or something new) and generated to Verilog to explore it in an FPGA.
I’d be happy to contribute on this. We just need to agree where to put it (code and document).
Cheers,
Martin
The text was updated successfully, but these errors were encountered: