FIRRTL bulk connections emitted incorrectly for views of same type but non-identity mapping

[jackkoenig]

Type of issue: Bug Report

Please provide the steps to reproduce the problem:

Consider the following Chisel:

//> using scala "2.13.12"
//> using dep "org.chipsalliance::chisel:6.4.0"
//> using plugin "org.chipsalliance:::chisel-plugin:6.4.0"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
import _root_.circt.stage.ChiselStage

import chisel3.experimental.dataview._

object Util {
  type ReversedVec[T <: Data] = Vec[T]
  implicit def reversedVecView[T <: Data]: DataView[Vec[T], ReversedVec[T]] =
    DataView.mapping[Vec[T], ReversedVec[T]](v => v.cloneType, { case (a, b) => a.reverse.zip(b) })
}
import Util._
class MyModule extends Module {
  val in = IO(Input(Vec(2, UInt(8.W))))
  val turducken, legacy = IO(Output(Vec(2, UInt(8.W))))

  val view = in.viewAs[ReversedVec[UInt]]
  turducken :<>= view
  legacy <> view
}

object Main extends App {
  println( ChiselStage.emitCHIRRTL(new MyModule))
  println(
    ChiselStage.emitSystemVerilog(
      gen = new MyModule,
      firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
    )
  )
}

What is the current behavior?

This emits the following Verilog:

// Generated by CIRCT firtool-1.62.0
module MyModule(
  input        clock,
               reset,
  input  [7:0] in_0,
               in_1,
  output [7:0] turducken_0,
               turducken_1,
               legacy_0,
               legacy_1
);

  assign turducken_0 = in_1;
  assign turducken_1 = in_0;
  assign legacy_0 = in_0;
  assign legacy_1 = in_1;
endmodule

What is the expected behavior?

Obviously those connections to legacy are wrong. This is due to the fact that Chisel is emitting a bulk connect to FIRRTL:

FIRRTL version 3.3.0
circuit MyModule :
  module MyModule : @[Users/koenig/work/t/badbulkconnect/chisel-example.scala 18:7]
    input clock : Clock @[Users/koenig/work/t/badbulkconnect/chisel-example.scala 18:7]
    input reset : UInt<1> @[Users/koenig/work/t/badbulkconnect/chisel-example.scala 18:7]
    input in : UInt<8>[2] @[Users/koenig/work/t/badbulkconnect/chisel-example.scala 19:14]
    output turducken : UInt<8>[2] @[Users/koenig/work/t/badbulkconnect/chisel-example.scala 20:29]
    output legacy : UInt<8>[2] @[Users/koenig/work/t/badbulkconnect/chisel-example.scala 20:29]

    connect turducken[0], in[1] @[Users/koenig/work/t/badbulkconnect/chisel-example.scala 23:13]
    connect turducken[1], in[0] @[Users/koenig/work/t/badbulkconnect/chisel-example.scala 23:13]
    connect legacy, in @[Users/koenig/work/t/badbulkconnect/chisel-example.scala 24:10]

Please tell us about your environment:

Other Information

What is the use case for changing the behavior?