Mem of Vec cannot be accessed as expected

[colinschmidt]

With the following chisel

val blocks = Mem(nSectors, Vec(dataBeats, UInt(dataBitsPerBeat.W)))
...
blocks(dataReq.offset)(dataBeat) := io.data.bits.data

After the rocket-chip chisel bump(from chisel3/bb12fe to chisel3/e2c5c1) the above code no longer behaves as expected (accessing the inner Vec of the Mem) and instead throws the following error.

[error] /home/centos/hwacha-template/testchipip/src/main/scala/BlockDevice.scala:375: type mismatch;
[error]  found   : chisel3.core.UInt
[error]  required: chisel3.core.CompileOptions
[error]     blocks(dataReq.offset)(dataBeat) := io.data.bits.data

A simple workaround is below but seems highly unintuitive

blocks(dataReq.offset).apply(dataBeat) := io.data.bits.data

If I had more time I'd write a test but alas I do not have more time.