diff --git a/README.md b/README.md
index a4d2fe4285b..8d5e46543c6 100644
--- a/README.md
+++ b/README.md
@@ -132,7 +132,7 @@ Then you can open the generated HTML and copy-paste
 
 Consider an FIR filter that implements a convolution operation, as depicted in this block diagram:
 
-<img src="https://raw.githubusercontent.com/chipsalliance/chisel/master/docs/src/images/fir_filter.svg?sanitize=true" width="512" />
+<img src="https://raw.githubusercontent.com/chipsalliance/chisel/main/docs/src/images/fir_filter.svg?sanitize=true" width="512" />
 
 While Chisel provides similar base primitives as synthesizable Verilog, and *could* be used as such:
 
@@ -218,7 +218,7 @@ If you like a textbook to learn Chisel and also a bit of digital design in gener
 
 ### Build Your Own Chisel Projects
 
-See [the setup instructions](SETUP.md) for how to set up your environment to build Chisel locally.
+Please see [the Installation page](https://www.chisel-lang.org/docs/installation) of the Chisel website for information about how to use Chisel locally.
 
 When you're ready to build your own circuits in Chisel, **we recommend starting from the [Chisel Template](https://github.com/freechipsproject/chisel-template) repository**, which provides a pre-configured project, example design, and testbench.
 Follow the [chisel-template README](https://github.com/freechipsproject/chisel-template) to get started.
@@ -245,7 +245,7 @@ libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.6.0" % "test"
 
 ### Guide For New Contributors
 
-If you are trying to make a contribution to this project, please read [CONTRIBUTING.md](https://github.com/chipsalliance/chisel/blob/master/CONTRIBUTING.md)
+If you are trying to make a contribution to this project, please read [CONTRIBUTING.md](CONTRIBUTING.md).
 
 ### Design Verification
 
@@ -278,7 +278,7 @@ Call-in info and meeting notes are available [here](https://docs.google.com/docu
 
 These are the base data types for defining circuit components:
 
-![Image](https://raw.githubusercontent.com/chipsalliance/chisel/master/docs/src/images/type_hierarchy.svg?sanitize=true)
+![Image](https://raw.githubusercontent.com/chipsalliance/chisel/main/docs/src/images/type_hierarchy.svg?sanitize=true)
 
 ## Contributor Documentation
 
@@ -316,7 +316,7 @@ sbt test
 
 ### Running Projects Against Local Chisel
 
-To use the development version of Chisel (`master` branch), you will need to build from source and publish locally.
+To use the development version of Chisel (`main` branch), you will need to build from source and publish locally.
 The repository version can be found by running `sbt version`.
 As of the time of writing it was: `6.0.0+1-8d92842c-SNAPSHOT`.
 
@@ -381,4 +381,4 @@ You are encouraged to do your development against the latest SNAPSHOT, but note
 
 ### Roadmap
 
-See [Roadmap](https://github.com/chipsalliance/chisel3/blob/master/ROADMAP.md).
+See [Roadmap](ROADMAP.md).
diff --git a/SETUP.md b/SETUP.md
deleted file mode 100644
index 8aa6a7b9e0a..00000000000
--- a/SETUP.md
+++ /dev/null
@@ -1,64 +0,0 @@
-# Chisel Local Setup
-Instructions for setting up your environment to run Chisel locally.
-
-For a minimal setup, you only need to install [SBT (the Scala Build Tool)](http://www.scala-sbt.org), which will automatically fetch the appropriate version of Scala and Chisel based on your project configuration.
-
-[Verilator](https://www.veripool.org/wiki/verilator) Installation is required to simulate your Verilog designs.
-
-## Ubuntu Linux
-
-1.  Install the JVM
-    ```bash
-    sudo apt-get install default-jdk
-    ```
-
-1.  Install sbt according to the instructions from [sbt download](https://www.scala-sbt.org/download.html).
-
-2.  Install Verilator.
-    We currently recommend Verilator version v4.226.
-    Follow these instructions to compile it from the source.
-
-    1.  Install prerequisites (if not installed already):
-        ```bash
-        sudo apt-get install git make autoconf g++ flex bison
-        ```
-
-    2.  Clone the Verilator repository:
-        ```bash
-        git clone https://github.com/verilator/verilator
-        ```
-
-    3.  In the Verilator repository directory, check out a known good version:
-        ```bash
-        git pull
-        git checkout v4.226
-        ```
-
-    4.  In the Verilator repository directory, build and install:
-        ```bash
-        unset VERILATOR_ROOT # For bash, unsetenv for csh
-        autoconf # Create ./configure script
-        ./configure
-        make
-        sudo make install
-        ```
-
-## Arch Linux
-1.  Install Verilator and SBT
-    ```bash
-    pacman -Sy verilator sbt
-    ```
-
-## Windows
-1.  [Download and install sbt for Windows](https://www.scala-sbt.org/download.html).
-
-Verilator does not appear to have native Windows support.
-However, Verilator works in [WSL](https://docs.microsoft.com/en-us/windows/wsl/install-win10) or in other Linux-compatible environments like Cygwin.
-
-There are no issues with generating Verilog from Chisel, which can be pushed to FPGA or ASIC tools.
-
-## Mac OS X
-1.  Install Verilator and SBT
-    ```bash
-    brew install sbt verilator
-    ```