diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index 3c759062e51..06e45126ee0 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -95,7 +95,7 @@ private[chisel3] object ir {
 
     def earlyLocalName(id: HasId, includeRoot: Boolean): String = id.getOptionRef match {
       case Some(Index(Node(imm), Node(value))) =>
-        s"${earlyLocalName(imm, includeRoot)}[${earlyLocalName(imm, includeRoot)}]"
+        s"${earlyLocalName(imm, includeRoot)}[${earlyLocalName(value, includeRoot)}]"
       case Some(Index(Node(imm), arg)) => s"${earlyLocalName(imm, includeRoot)}[${arg.localName}]"
       case Some(Slot(Node(imm), name)) => s"${earlyLocalName(imm, includeRoot)}.$name"
       case Some(OpaqueSlot(Node(imm))) => s"${earlyLocalName(imm, includeRoot)}"
diff --git a/src/test/scala/chiselTests/DataPrint.scala b/src/test/scala/chiselTests/DataPrint.scala
index 784a2089d78..67954d9ebd4 100644
--- a/src/test/scala/chiselTests/DataPrint.scala
+++ b/src/test/scala/chiselTests/DataPrint.scala
@@ -53,6 +53,16 @@ class DataPrintSpec extends ChiselFlatSpec with Matchers {
     (2.U + 2.U).toString should be("BoundDataModule.?: OpResult[UInt<2>]")
     Wire(Vec(3, UInt(2.W))).toString should be("BoundDataModule.?: Wire[UInt<2>[3]]")
 
+    val idx = IO(Input(UInt(3.W)))
+    val jdx = IO(Input(new Bundle {
+      val value = UInt(3.W)
+    }))
+    val port = IO(Input(new Bundle {
+      val vec = Vec(8, UInt(8.W))
+    }))
+    port.vec(idx).toString should be("BoundDataModule.port.vec[idx]: IO[UInt<8>]")
+    port.vec(jdx.value).toString should be("BoundDataModule.port.vec[jdx.value]: IO[UInt<8>]")
+
     class InnerModule extends Module {
       val io = IO(Output(new Bundle {
         val a = UInt(4.W)