From 21e3b8a1f6af280a476e726cfef462fd3e06d8d9 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 10 Mar 2020 18:48:57 -0700 Subject: [PATCH] tilelink/amba: avoid dangerous chisel3 <> and := in key locations --- src/main/scala/amba/axi4/Filter.scala | 2 +- src/main/scala/amba/axi4/Fragmenter.scala | 4 ++-- src/main/scala/amba/axi4/IdIndexer.scala | 6 +++--- src/main/scala/amba/axi4/ToTL.scala | 4 ++-- src/main/scala/amba/axi4/UserYanker.scala | 2 +- src/main/scala/amba/axi4/Xbar.scala | 6 +++--- src/main/scala/amba/axis/Xbar.scala | 8 +++----- src/main/scala/tilelink/Arbiter.scala | 4 ++-- src/main/scala/tilelink/ToAHB.scala | 2 +- src/main/scala/tilelink/ToAPB.scala | 2 +- src/main/scala/tilelink/ToAXI4.scala | 2 +- 11 files changed, 20 insertions(+), 22 deletions(-) diff --git a/src/main/scala/amba/axi4/Filter.scala b/src/main/scala/amba/axi4/Filter.scala index 7eee69aa8d2..fe0ebc4c553 100644 --- a/src/main/scala/amba/axi4/Filter.scala +++ b/src/main/scala/amba/axi4/Filter.scala @@ -32,7 +32,7 @@ class AXI4Filter( lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => - out <> in + out :<> in } } } diff --git a/src/main/scala/amba/axi4/Fragmenter.scala b/src/main/scala/amba/axi4/Fragmenter.scala index 8ca8a824e04..c4c2485f5c0 100644 --- a/src/main/scala/amba/axi4/Fragmenter.scala +++ b/src/main/scala/amba/axi4/Fragmenter.scala @@ -112,7 +112,7 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule a.ready := out.ready && last out.valid := a.valid - out.bits := a.bits + out.bits :<= a.bits out.bits.len := beats1 // We forcibly align every access. If the first beat was misaligned, the strb bits @@ -173,7 +173,7 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule wbeats_ready := w_idle out.w.valid := in_w.valid && (!wbeats_ready || wbeats_valid) in_w.ready := out.w.ready && (!wbeats_ready || wbeats_valid) - out.w.bits := in_w.bits + out.w.bits :<= in_w.bits out.w.bits.last := w_last // We should also recreate the last last assert (!out.w.valid || !in_w.bits.last || w_last) diff --git a/src/main/scala/amba/axi4/IdIndexer.scala b/src/main/scala/amba/axi4/IdIndexer.scala index 5ea31c61872..d08a794d76d 100644 --- a/src/main/scala/amba/axi4/IdIndexer.scala +++ b/src/main/scala/amba/axi4/IdIndexer.scala @@ -52,9 +52,9 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule // Leave everything mostly untouched out.ar :<> in.ar out.aw :<> in.aw - out.w <> in.w - in.b <> out.b - in.r <> out.r + out.w :<> in.w + in.b :<> out.b + in.r :<> out.r val bits = log2Ceil(edgeIn.master.endId) - idBits if (bits > 0) { diff --git a/src/main/scala/amba/axi4/ToTL.scala b/src/main/scala/amba/axi4/ToTL.scala index 80697329779..5062362d544 100644 --- a/src/main/scala/amba/axi4/ToTL.scala +++ b/src/main/scala/amba/axi4/ToTL.scala @@ -159,7 +159,7 @@ class AXI4ToTL(wcorrupt: Boolean = false)(implicit p: Parameters) extends LazyMo ok_r.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour - in.r <> Queue.irrevocable(ok_r, 1, flow=true) + in.r :<> Queue.irrevocable(ok_r, 1, flow=true) ok_b.bits.id := out.d.bits.source >> addedBits ok_b.bits.resp := d_resp @@ -178,7 +178,7 @@ class AXI4ToTL(wcorrupt: Boolean = false)(implicit p: Parameters) extends LazyMo when (in.b.fire() && s) { r := r + UInt(1) } } - in.b.bits := q_b.bits + in.b.bits :<= q_b.bits in.b.valid := q_b.valid && b_allow q_b.ready := in.b.ready && b_allow diff --git a/src/main/scala/amba/axi4/UserYanker.scala b/src/main/scala/amba/axi4/UserYanker.scala index 8c76ce8e905..31b33a2a3fa 100644 --- a/src/main/scala/amba/axi4/UserYanker.scala +++ b/src/main/scala/amba/axi4/UserYanker.scala @@ -84,7 +84,7 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e q.enq.bits :<= in.aw.bits.echo } - out.w <> in.w + out.w :<> in.w } } } diff --git a/src/main/scala/amba/axi4/Xbar.scala b/src/main/scala/amba/axi4/Xbar.scala index 43743f77cd7..6b2c74bf96f 100644 --- a/src/main/scala/amba/axi4/Xbar.scala +++ b/src/main/scala/amba/axi4/Xbar.scala @@ -189,7 +189,7 @@ class AXI4Xbar( AXI4Arbiter(arbitrationPolicy)(out(o).ar, portsAROI(o):_*) // W arbitration is informed by the Q, not policy out(o).w.valid := Mux1H(awOut(o).io.deq.bits, portsWOI(o).map(_.valid)) - out(o).w.bits := Mux1H(awOut(o).io.deq.bits, portsWOI(o).map(_.bits)) + out(o).w.bits :<= Mux1H(awOut(o).io.deq.bits, portsWOI(o).map(_.bits)) portsWOI(o).zipWithIndex.map { case (p, i) => if (in.size > 1) { p.ready := out(o).w.ready && awOut(o).io.deq.bits(i) @@ -223,7 +223,7 @@ object AXI4Xbar def fanout[T <: AXI4BundleBase](input: IrrevocableIO[T], select: Seq[Bool]) = { val filtered = Wire(Vec(select.size, input)) for (i <- 0 until select.size) { - filtered(i).bits := input.bits + filtered(i).bits :<= input.bits filtered(i).valid := input.valid && select(i) } input.ready := Mux1H(select, filtered.map(_.ready)) @@ -281,7 +281,7 @@ object AXI4Arbiter } sink.valid := Mux(idle, anyValid, Mux1H(state, valids)) - sink.bits := Mux1H(muxState, sources.map(_.bits)) + sink.bits :<= Mux1H(muxState, sources.map(_.bits)) muxState } } diff --git a/src/main/scala/amba/axis/Xbar.scala b/src/main/scala/amba/axis/Xbar.scala index 79eacf24522..0aee7e9a8f8 100644 --- a/src/main/scala/amba/axis/Xbar.scala +++ b/src/main/scala/amba/axis/Xbar.scala @@ -76,9 +76,7 @@ object AXISXbar if (sources.isEmpty) { sink.valid := false.B } else if (sources.size == 1) { - sink.valid := sources.head.valid - sink.bits := sources.head.bits - sources.head.ready := sink.ready + sink :<> sources.head } else { // The number of beats which remain to be sent val idle = RegInit(true.B) @@ -107,14 +105,14 @@ object AXISXbar val allowed = Mux(idle, readys, state) (sources zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids)) - sink.bits := Mux1H(muxState, sources.map(_.bits)) + sink.bits :<= Mux1H(muxState, sources.map(_.bits)) } } def fanout(input: AXISBundle, select: Seq[Bool]): Seq[AXISBundle] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { - filtered(i).bits := input.bits + filtered(i).bits :<= input.bits filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) diff --git a/src/main/scala/tilelink/Arbiter.scala b/src/main/scala/tilelink/Arbiter.scala index 433f38a9147..08c97dac77e 100644 --- a/src/main/scala/tilelink/Arbiter.scala +++ b/src/main/scala/tilelink/Arbiter.scala @@ -43,7 +43,7 @@ object TLArbiter if (sources.isEmpty) { sink.valid := Bool(false) } else if (sources.size == 1) { - sink <> sources.head._2 + sink :<> sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) @@ -84,7 +84,7 @@ object TLArbiter s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids)) - sink.bits := Mux1H(muxState, sourcesIn.map(_.bits)) + sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } diff --git a/src/main/scala/tilelink/ToAHB.scala b/src/main/scala/tilelink/ToAHB.scala index df32503da0f..ad52f2d84ad 100644 --- a/src/main/scala/tilelink/ToAHB.scala +++ b/src/main/scala/tilelink/ToAHB.scala @@ -202,7 +202,7 @@ class TLToAHB(val aFlow: Boolean = false, val supportHints: Boolean = true, val // a_ready and htrans, we add another entry for aFlow=false. val depth = if (aFlow) 2 else 3 val d = Wire(in.d) - in.d <> Queue(d, depth, flow=true) + in.d :<> Queue(d, depth, flow=true) assert (!d.valid || d.ready) val d_flight = RegInit(UInt(0, width = 2)) diff --git a/src/main/scala/tilelink/ToAPB.scala b/src/main/scala/tilelink/ToAPB.scala index af9a6acb506..c423dc9e220 100644 --- a/src/main/scala/tilelink/ToAPB.scala +++ b/src/main/scala/tilelink/ToAPB.scala @@ -63,7 +63,7 @@ class TLToAPB(val aFlow: Boolean = true)(implicit p: Parameters) extends LazyMod // phase result. Whenever we have a queued response, we can not allow // APB to present new responses, so we must quash the address phase. val d = Wire(in.d) - in.d <> Queue(d, 1, flow = true) + in.d :<> Queue(d, 1, flow = true) // We need an irrevocable input for APB to stall val a = Queue(in.a, 1, flow = aFlow, pipe = !aFlow) diff --git a/src/main/scala/tilelink/ToAXI4.scala b/src/main/scala/tilelink/ToAXI4.scala index b571519ec72..445efa27407 100644 --- a/src/main/scala/tilelink/ToAXI4.scala +++ b/src/main/scala/tilelink/ToAXI4.scala @@ -148,7 +148,7 @@ class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String val depth = if (combinational) 1 else 2 val out_arw = Wire(Decoupled(new AXI4BundleARW(out.params))) val out_w = Wire(out.w) - out.w <> Queue.irrevocable(out_w, entries=depth, flow=combinational) + out.w :<> Queue.irrevocable(out_w, entries=depth, flow=combinational) val queue_arw = Queue.irrevocable(out_arw, entries=depth, flow=combinational) // Fan out the ARW channel to AR and AW