diff --git a/src/main/scala/amba/ahb/ToTL.scala b/src/main/scala/amba/ahb/ToTL.scala index e062015676c..7cdf05e23b2 100644 --- a/src/main/scala/amba/ahb/ToTL.scala +++ b/src/main/scala/amba/ahb/ToTL.scala @@ -110,9 +110,10 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule x.fetch := !in.hprot(0) x.privileged := in.hprot(1) x.bufferable := in.hprot(2) - x.cacheable := in.hprot(3) - x.secure := false.B x.modifiable := in.hprot(3) + x.secure := false.B + x.readalloc := in.hprot(3) + x.writealloc := in.hprot(3) } } } diff --git a/src/main/scala/amba/apb/ToTL.scala b/src/main/scala/amba/apb/ToTL.scala index 1510fc25486..89ea23bc65a 100644 --- a/src/main/scala/amba/apb/ToTL.scala +++ b/src/main/scala/amba/apb/ToTL.scala @@ -92,8 +92,9 @@ class APBToTL()(implicit p: Parameters) extends LazyModule prot.secure := !in.pprot(1) prot.fetch := in.pprot(2) prot.bufferable := true.B - prot.cacheable := true.B prot.modifiable := true.B + prot.readalloc := true.B + prot.writealloc := true.B } when (out.a.fire()) { assert(in.paddr === out.a.bits.address, "Do not expect to have to perform alignment in APB2TL Conversion") diff --git a/src/main/scala/amba/axi4/ToTL.scala b/src/main/scala/amba/axi4/ToTL.scala index 88049f776ca..219cbeea9c6 100644 --- a/src/main/scala/amba/axi4/ToTL.scala +++ b/src/main/scala/amba/axi4/ToTL.scala @@ -97,7 +97,8 @@ class AXI4ToTL(wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule rprot.fetch := in.ar.bits.prot(2) rprot.bufferable := in.ar.bits.cache(0) rprot.modifiable := in.ar.bits.cache(1) - rprot.cacheable := in.ar.bits.cache(2) || in.ar.bits.cache(3) + rprot.readalloc := in.ar.bits.cache(2) + rprot.writealloc := in.ar.bits.cache(3) } val r_sel = UIntToOH(in.ar.bits.id, numIds) @@ -132,7 +133,8 @@ class AXI4ToTL(wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule wprot.fetch := in.aw.bits.prot(2) wprot.bufferable := in.aw.bits.cache(0) wprot.modifiable := in.aw.bits.cache(1) - wprot.cacheable := in.aw.bits.cache(2) || in.aw.bits.cache(3) + wprot.readalloc := in.aw.bits.cache(2) + wprot.writealloc := in.aw.bits.cache(3) } val w_sel = UIntToOH(in.aw.bits.id, numIds) diff --git a/src/main/scala/amba/package.scala b/src/main/scala/amba/package.scala index 5b7bb1f4d36..80024ccb1cf 100644 --- a/src/main/scala/amba/package.scala +++ b/src/main/scala/amba/package.scala @@ -7,9 +7,10 @@ import freechips.rocketchip.util._ package object amba { class AMBAProtBundle extends Bundle { - val cacheable = Bool() // false => no need to probe other cores val bufferable = Bool() // writeback caching ok? val modifiable = Bool() // legal to read/write-combine/expand this request? + val readalloc = Bool() + val writealloc = Bool() val privileged = Bool() // machine_mode=true, user_mode=false val secure = Bool() // secure_master=true, normal=false val fetch = Bool() // instruct_fetch=true, load/store=false @@ -19,9 +20,10 @@ package object amba { case class AMBAProtField() extends BundleField(AMBAProt) { def data = Output(new AMBAProtBundle) def default(x: AMBAProtBundle) { - x.cacheable := false.B x.bufferable := false.B x.modifiable := false.B + x.readalloc := false.B + x.writealloc := false.B x.privileged := true.B x.secure := true.B x.fetch := false.B diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index 99245232d68..f60e3777824 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -554,16 +554,18 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { // Drive APROT Bits tl_out_a.bits.user.lift(AMBAProt).foreach { x => - val user_bit_cacheable = edge.manager.supportsAcquireTFast(access_address, a_size) + val user_bit_cacheable = s2_pma.cacheable x.privileged := s2_req.dprv === PRV.M || user_bit_cacheable - x.cacheable := user_bit_cacheable + // if the address is cacheable, enable outer caches + x.bufferable := user_bit_cacheable + x.modifiable := user_bit_cacheable + x.readalloc := user_bit_cacheable + x.writealloc := user_bit_cacheable // Following are always tied off x.fetch := false.B x.secure := true.B - x.bufferable := false.B - x.modifiable := false.B } // Set pending bits for outstanding TileLink transaction diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index 7536a0f68af..9d9adb739bc 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -163,7 +163,6 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) val s2_can_speculatively_refill = s2_tlb_resp.cacheable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill icache.io.s2_kill := s2_speculative && !s2_can_speculatively_refill || s2_xcpt icache.io.s2_prefetch := s2_tlb_resp.prefetchable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableICachePrefetch - icache.io.privileged := io.ptw.status.prv === PRV.M fq.io.enq.valid := RegNext(s1_valid) && s2_valid && (icache.io.resp.valid || !s2_tlb_resp.miss && icache.io.s2_kill) fq.io.enq.bits.pc := s2_pc diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index 29942b72402..6b2fc87e866 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -124,8 +124,6 @@ class ICacheBundle(val outer: ICache) extends CoreBundle()(outer.p) { val clock_enabled = Bool(INPUT) val keep_clock_enabled = Bool(OUTPUT) - - val privileged = Bool(INPUT) } class ICacheModule(outer: ICache) extends LazyModuleImp(outer) @@ -445,16 +443,20 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) } // Drive APROT information tl_out.a.bits.user.lift(AMBAProt).foreach { x => - val user_bit_cacheable = edge_out.manager.supportsAcquireTFast(refill_paddr, lgCacheBlockBytes.U) + // Rocket caches all fetch requests, and it's difficult to differentiate privileged/unprivileged on + // cached data, so mark as privileged + val user_bit_cacheable = true.B - x.privileged := io.privileged || user_bit_cacheable // privileged if machine mode or memory port - x.cacheable := user_bit_cacheable + // enable outer caches for all fetches + x.privileged := user_bit_cacheable + x.bufferable := user_bit_cacheable + x.modifiable := user_bit_cacheable + x.readalloc := user_bit_cacheable + x.writealloc := user_bit_cacheable // Following are always tied off x.fetch := true.B x.secure := true.B - x.bufferable := false.B - x.modifiable := false.B } tl_out.b.ready := Bool(true) tl_out.c.valid := Bool(false) diff --git a/src/main/scala/tilelink/ToAHB.scala b/src/main/scala/tilelink/ToAHB.scala index e8c1f63b325..d3a7b6fb75c 100644 --- a/src/main/scala/tilelink/ToAHB.scala +++ b/src/main/scala/tilelink/ToAHB.scala @@ -192,7 +192,7 @@ class TLToAHB(val aFlow: Boolean = false, val supportHints: Boolean = true, val hprot(0) := !x.fetch hprot(1) := x.privileged hprot(2) := x.bufferable - hprot(3) := x.cacheable + hprot(3) := x.modifiable out.hprot := Cat(hprot.reverse) } diff --git a/src/main/scala/tilelink/ToAXI4.scala b/src/main/scala/tilelink/ToAXI4.scala index d2c7f038d50..131e95c46bc 100644 --- a/src/main/scala/tilelink/ToAXI4.scala +++ b/src/main/scala/tilelink/ToAXI4.scala @@ -189,8 +189,8 @@ class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String prot(2) := x.fetch cache(0) := x.bufferable cache(1) := x.modifiable - cache(2) := x.cacheable - cache(3) := x.cacheable + cache(2) := x.readalloc + cache(3) := x.writealloc arw.prot := Cat(prot.reverse) arw.cache := Cat(cache.reverse) }