From 86e5fa8b67d39f00e1ceb17994b9a60ea7727ef9 Mon Sep 17 00:00:00 2001 From: Joshua Smith Date: Tue, 1 Sep 2020 18:51:42 -0700 Subject: [PATCH] Relax master parameter of RocketCrossingParams --- src/main/scala/subsystem/Configs.scala | 5 ++++- src/main/scala/subsystem/RocketSubsystem.scala | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala index bbfaca9c8f0..5085d6c8f86 100644 --- a/src/main/scala/subsystem/Configs.scala +++ b/src/main/scala/subsystem/Configs.scala @@ -234,7 +234,10 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => { */ class WithIncoherentTiles extends Config((site, here, up) => { case RocketCrossingKey => up(RocketCrossingKey, site) map { r => - r.copy(master = r.master.copy(cork = Some(true))) + r.copy(master = r.master match { + case x: TileMasterPortParams => x.copy(cork = Some(true)) + case _ => r.master + }) } case BankedL2Key => up(BankedL2Key, site).copy( coherenceManager = CoherenceManagerWrapper.incoherentManager diff --git a/src/main/scala/subsystem/RocketSubsystem.scala b/src/main/scala/subsystem/RocketSubsystem.scala index 7e4d1bf482e..305f1d9a803 100644 --- a/src/main/scala/subsystem/RocketSubsystem.scala +++ b/src/main/scala/subsystem/RocketSubsystem.scala @@ -15,7 +15,7 @@ import freechips.rocketchip.tile._ case class RocketCrossingParams( crossingType: ClockCrossingType = SynchronousCrossing(), - master: TileMasterPortParams = TileMasterPortParams(), + master: TilePortParamsLike = TileMasterPortParams(), slave: TileSlavePortParams = TileSlavePortParams(), mmioBaseAddressPrefixWhere: TLBusWrapperLocation = CBUS, stretchResetCycles: Option[Int] = None