From 8e1f0c8fd50847749ab61dd1c7d2e9d7b498f74a Mon Sep 17 00:00:00 2001
From: John Ingalls <43973001+johningalls-sifive@users.noreply.github.com>
Date: Sat, 4 Apr 2020 15:33:35 -0700
Subject: [PATCH] fix Chisel compile warnings in PseudoLRU.access(ways: Seq)
 (#2378)

---
 src/main/scala/util/Replacement.scala | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/main/scala/util/Replacement.scala b/src/main/scala/util/Replacement.scala
index ffe1d7930f2..d2a5a6c6306 100644
--- a/src/main/scala/util/Replacement.scala
+++ b/src/main/scala/util/Replacement.scala
@@ -44,8 +44,7 @@ class PseudoLRU(n: Int)
     state_reg := get_next_state(state_reg,way)
   }
   def access(ways: Seq[ValidIO[UInt]]) {
-    state_reg := ways.fold(state_reg) { case (prev: UInt, way: ValidIO[UInt]) =>
-      Mux(way.valid, get_next_state(prev, way.bits), prev) }
+    state_reg := ways.foldLeft(state_reg)((prev, way) => Mux(way.valid, get_next_state(prev, way.bits), prev))
   }
   def get_next_state(state: UInt, way: UInt) = {
     var next_state = state << 1