From c0bb78be53752c20a01f9c960f2b0805031a8bf0 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Mon, 3 Feb 2020 21:30:07 -0800 Subject: [PATCH] TLWidthWidget: one more fix for the port to chisel3 --- src/main/scala/tilelink/WidthWidget.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/tilelink/WidthWidget.scala b/src/main/scala/tilelink/WidthWidget.scala index 44a2f989700..f53d7bb5521 100644 --- a/src/main/scala/tilelink/WidthWidget.scala +++ b/src/main/scala/tilelink/WidthWidget.scala @@ -188,7 +188,9 @@ class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyMod if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) - out.e <> in.e + out.e.valid := in.e.valid + out.e.bits := in.e.bits + in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B