From db3003aae25b4bdbc4189c1680ab7ff5c313976f Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Tue, 15 Sep 2020 12:30:20 -0700 Subject: [PATCH] Remove Verilog delay from DPI outputs and use falling edge instead (#2635) Verilator ignores these delays (after warning the user), so they can result in race conditions. Co-authored-by: Ernie Edgar --- src/main/resources/vsrc/SimDTM.v | 38 +++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 11 deletions(-) diff --git a/src/main/resources/vsrc/SimDTM.v b/src/main/resources/vsrc/SimDTM.v index 293e7841bfe..9f403fdc161 100644 --- a/src/main/resources/vsrc/SimDTM.v +++ b/src/main/resources/vsrc/SimDTM.v @@ -35,10 +35,10 @@ module SimDTM( bit r_reset; - wire #0.1 __debug_req_ready = debug_req_ready; - wire #0.1 __debug_resp_valid = debug_resp_valid; - wire [31:0] #0.1 __debug_resp_bits_resp = {30'b0, debug_resp_bits_resp}; - wire [31:0] #0.1 __debug_resp_bits_data = debug_resp_bits_data; + wire __debug_req_ready = debug_req_ready; + wire __debug_resp_valid = debug_resp_valid; + wire [31:0] __debug_resp_bits_resp = {30'b0, debug_resp_bits_resp}; + wire [31:0] __debug_resp_bits_data = debug_resp_bits_data; bit __debug_req_valid; int __debug_req_bits_addr; @@ -47,14 +47,30 @@ module SimDTM( bit __debug_resp_ready; int __exit; - assign #0.1 debug_req_valid = __debug_req_valid; - assign #0.1 debug_req_bits_addr = __debug_req_bits_addr[6:0]; - assign #0.1 debug_req_bits_op = __debug_req_bits_op[1:0]; - assign #0.1 debug_req_bits_data = __debug_req_bits_data[31:0]; - assign #0.1 debug_resp_ready = __debug_resp_ready; - assign #0.1 exit = __exit; + reg debug_req_valid_reg; + reg [ 6:0] debug_req_bits_addr_reg; + reg [ 1:0] debug_req_bits_op_reg; + reg [31:0] debug_req_bits_data_reg; + reg debug_resp_ready_reg; + reg [31:0] exit_reg; - always @(posedge clk) + always @(posedge clk) begin + debug_req_valid_reg <= __debug_req_valid; + debug_req_bits_addr_reg <= __debug_req_bits_addr[6:0]; + debug_req_bits_op_reg <= __debug_req_bits_op[1:0]; + debug_req_bits_data_reg <= __debug_req_bits_data[31:0]; + debug_resp_ready_reg <= __debug_resp_ready; + exit_reg <= __exit; + end + + assign debug_req_valid = debug_req_valid_reg; + assign debug_req_bits_addr = debug_req_bits_addr_reg; + assign debug_req_bits_op = debug_req_bits_op_reg; + assign debug_req_bits_data = debug_req_bits_data_reg; + assign debug_resp_ready = debug_resp_ready_reg; + assign exit = exit_reg; + + always @(negedge clk) begin r_reset <= reset; if (reset || r_reset)