From ea701a19b1c504ad2755e58f0369dea7ac0ad541 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 8 Nov 2020 15:28:01 -0800 Subject: [PATCH] Fix regression introduced by 79dd73a38c4b6ba8f2261b1f24bd6fa7094b1316 I introduced some deadlock a couple days ago. --- src/main/scala/rocket/DCache.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index 1ac46a95d0d..2d5f2e51b8b 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -573,7 +573,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { tl_out_a.valid := !io.cpu.s2_kill && (s2_valid_uncached_pending || (s2_valid_cached_miss && - !(release_ack_wait && release_ack_dirty) && + !release_ack_wait && (cacheParams.acquireBeforeRelease && release_queue_empty || cacheParams.silentDrop && !s2_victim_dirty))) tl_out_a.bits := Mux(!s2_uncached, acquire(s2_vaddr, s2_req.addr, s2_grow_param), Mux(!s2_write, get, @@ -858,7 +858,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { when (releaseDone) { release_state := s_voluntary_write_meta } when (tl_out_c.fire() && c_first) { release_ack_wait := true - release_ack_dirty := release_state === s_voluntary_release + release_ack_dirty := inWriteback release_ack_addr := probe_bits.address } }