From f8fd6013f0ea09d8e0da79fa841b7ad839daefcf Mon Sep 17 00:00:00 2001
From: Pengcheng Xu <i@jsteward.moe>
Date: Fri, 4 Sep 2020 14:07:32 +0800
Subject: [PATCH] Make SimAXIMem start at expected memory boundary instead of
 zero

---
 src/main/scala/system/SimAXIMem.scala | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/main/scala/system/SimAXIMem.scala b/src/main/scala/system/SimAXIMem.scala
index 42fd238cc8d..42c94ddff89 100644
--- a/src/main/scala/system/SimAXIMem.scala
+++ b/src/main/scala/system/SimAXIMem.scala
@@ -5,14 +5,14 @@ package freechips.rocketchip.system // TODO this should really be in a testharne
 import chisel3._
 import freechips.rocketchip.amba._
 import freechips.rocketchip.amba.axi4._
-import freechips.rocketchip.config.{Parameters}
+import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MMIOPort, CanHaveMasterAXI4MemPort, ExtMem}
+import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MMIOPort, CanHaveMasterAXI4MemPort, ExtBus, ExtMem}
 
 /** Memory with AXI port for use in elaboratable test harnesses. */
-class SimAXIMem(edge: AXI4EdgeParameters, size: BigInt)(implicit p: Parameters) extends SimpleLazyModule {
+class SimAXIMem(edge: AXI4EdgeParameters, base: BigInt, size: BigInt)(implicit p: Parameters) extends SimpleLazyModule {
   val node = AXI4MasterNode(List(edge.master))
-  val srams = AddressSet.misaligned(0, size).map { aSet =>
+  val srams = AddressSet.misaligned(base, size).map { aSet =>
     LazyModule(new AXI4RAM(
       address = aSet,
       beatBytes = edge.bundle.dataBits/8,
@@ -28,7 +28,7 @@ object SimAXIMem {
   def connectMMIO(dut: CanHaveMasterAXI4MMIOPort)(implicit p: Parameters): Seq[SimAXIMem] = {
     dut.mmio_axi4.zip(dut.mmioAXI4Node.in).map { case (io, (_, edge)) =>
       // test harness size capped to 4KB (ignoring p(ExtMem).get.master.size)
-      val mmio_mem = LazyModule(new SimAXIMem(edge, size = 4096))
+      val mmio_mem = LazyModule(new SimAXIMem(edge, base = p(ExtBus).get.base, size = 4096))
       Module(mmio_mem.module).suggestName("mmio_mem")
       mmio_mem.io_axi4.head <> io
       mmio_mem
@@ -37,7 +37,7 @@ object SimAXIMem {
 
   def connectMem(dut: CanHaveMasterAXI4MemPort)(implicit p: Parameters): Seq[SimAXIMem] = {
     dut.mem_axi4.zip(dut.memAXI4Node.in).map { case (io, (_, edge)) =>
-      val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size))
+      val mem = LazyModule(new SimAXIMem(edge, base = p(ExtMem).get.master.base, size = p(ExtMem).get.master.size))
       Module(mem.module).suggestName("mem")
       mem.io_axi4.head <> io
       mem