From 8159b6cd935c5cf73f6f185d56074c9070ac13f7 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Tue, 3 Mar 2020 17:07:13 -0800
Subject: [PATCH] prci: allow configurable ClockGroupDriver drive fn

---
 src/main/scala/prci/ClockParameters.scala    | 26 ++++++++++++++++++--
 src/main/scala/subsystem/BaseSubsystem.scala |  5 +++-
 2 files changed, 28 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/prci/ClockParameters.scala b/src/main/scala/prci/ClockParameters.scala
index 0ea7687b1e9..1e05ed896e8 100644
--- a/src/main/scala/prci/ClockParameters.scala
+++ b/src/main/scala/prci/ClockParameters.scala
@@ -4,6 +4,8 @@ package freechips.rocketchip.prci
 import chisel3._
 import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy.{InModuleBody, ModuleValue, ValName}
+import freechips.rocketchip.util.{HeterogeneousBag}
 import scala.math.max
 
 // All Clock parameters specify only the PLL values required at power-on
@@ -77,9 +79,29 @@ case class ClockGroupEdgeParameters(
 }
 
 // Used to create simple clock group drivers that just use the Chisel implicit clock
-case class ClockGroupDriverParameters(num: Int = 1) {
-  def driveFromImplicitClock(groups: ClockGroupEphemeralNode)(implicit p: Parameters): Unit = {
+case class ClockGroupDriverParameters(
+  num: Int = 1,
+  driveFn: ClockGroupDriver.DriveFn = ClockGroupDriver.driveFromImplicitClock
+) {
+  def drive(node: ClockGroupEphemeralNode)(implicit p: Parameters, vn: ValName): ModuleValue[HeterogeneousBag[ClockGroupBundle]] = {
+    driveFn(node, num, p, vn)
+  }
+}
+
+object ClockGroupDriver {
+  type DriveFn = (ClockGroupEphemeralNode, Int, Parameters, ValName) => ModuleValue[HeterogeneousBag[ClockGroupBundle]]
+
+  def driveFromImplicitClock: DriveFn = { (groups, num, p, vn) =>
+    implicit val pp = p
     val dummyClockGroupSourceNode: ClockGroupSourceNode = SimpleClockGroupSource(num)
     groups :*= dummyClockGroupSourceNode
+    InModuleBody { HeterogeneousBag[ClockGroupBundle](Nil) }
+  }
+
+  def driveFromIOs: DriveFn = { (groups, num, p, vn) =>
+    implicit val pp = p
+    val ioClockGroupSourceNode = ClockGroupSourceNode(List.fill(num) { ClockGroupSourceParameters() })
+    groups :*= ioClockGroupSourceNode
+    InModuleBody { ioClockGroupSourceNode.makeIOs()(vn) }
   }
 }
diff --git a/src/main/scala/subsystem/BaseSubsystem.scala b/src/main/scala/subsystem/BaseSubsystem.scala
index 33baa0aabfa..23fa9c993ba 100644
--- a/src/main/scala/subsystem/BaseSubsystem.scala
+++ b/src/main/scala/subsystem/BaseSubsystem.scala
@@ -92,7 +92,10 @@ abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem
   }
 
   implicit val asyncClockGroupsNode = p(AsyncClockGroupsKey)
-  p(SubsystemDriveAsyncClockGroupsKey).foreach(_.driveFromImplicitClock(asyncClockGroupsNode))
+  val async_clock_groups =
+    p(SubsystemDriveAsyncClockGroupsKey)
+      .map(_.drive(asyncClockGroupsNode))
+      .getOrElse(InModuleBody { HeterogeneousBag[ClockGroupBundle](Nil) })
 
   // Collect information for use in DTS
   lazy val topManagers = sbus.unifyManagers