From 595e0e946b174ba8a36dc67aea8a8b0748c0c824 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Tue, 17 Mar 2020 22:06:54 -0700 Subject: [PATCH 1/9] Create OMErrorDevice.scala --- .../diplomaticobjectmodel/model/OMErrorDevice.scala | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 src/main/scala/diplomaticobjectmodel/model/OMErrorDevice.scala diff --git a/src/main/scala/diplomaticobjectmodel/model/OMErrorDevice.scala b/src/main/scala/diplomaticobjectmodel/model/OMErrorDevice.scala new file mode 100644 index 00000000000..ccf5ca5323a --- /dev/null +++ b/src/main/scala/diplomaticobjectmodel/model/OMErrorDevice.scala @@ -0,0 +1,11 @@ +// See LICENSE.SiFive for license details. + +package freechips.rocketchip.diplomaticobjectmodel.model + + +case class OMErrorDevice( + memoryRegions: Seq[OMMemoryRegion], + interrupts: Seq[OMInterrupt], + specifications: Seq[OMSpecification], + _types: Seq[String] = Seq("OMErrorDevice", "OMDevice", "OMComponent", "OMCompoundType") +) extends OMDevice From 0e083262277acecef1f8f8ad3319708c4a092145 Mon Sep 17 00:00:00 2001 From: Albert Chen Date: Fri, 10 Apr 2020 18:38:52 -0700 Subject: [PATCH 2/9] TLError: implement HasLogicalTreeNode BaseSubsystem: attach built-in TLError LogicalTreeNodes --- .../tilelink/CanHaveBuiltInDevices.scala | 14 +++++++++++--- src/main/scala/devices/tilelink/DevNull.scala | 2 +- src/main/scala/devices/tilelink/Error.scala | 18 ++++++++++++++++++ src/main/scala/subsystem/BaseSubsystem.scala | 16 +++++++++++++++- src/main/scala/subsystem/FrontBus.scala | 2 +- src/main/scala/subsystem/MemoryBus.scala | 2 +- src/main/scala/subsystem/PeripheryBus.scala | 2 +- src/main/scala/subsystem/SystemBus.scala | 2 +- 8 files changed, 49 insertions(+), 9 deletions(-) diff --git a/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala b/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala index b421b3eba2a..6b96851c1c8 100644 --- a/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala +++ b/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala @@ -11,22 +11,30 @@ trait HasBuiltInDeviceParams { val errorDevice: Option[DevNullParams] } +sealed trait BuiltInDevices { + def errorOpt: Option[TLError] + def zeroOpt: Option[TLZero] +} + /* Optionally add some built-in devices to a bus wrapper */ trait CanHaveBuiltInDevices { this: TLBusWrapper => - def attachBuiltInDevices(params: HasBuiltInDeviceParams) { - params.errorDevice.foreach { dnp => LazyScope("wrapped_error_device") { + def attachBuiltInDevices(params: HasBuiltInDeviceParams): BuiltInDevices = new BuiltInDevices { + val errorOpt = params.errorDevice.map { dnp => LazyScope("wrapped_error_device") { val error = LazyModule(new TLError( params = dnp, beatBytes = beatBytes)) + error.node := TLBuffer() := outwardNode + error }} - params.zeroDevice.foreach { addr => LazyScope("wrapped_zero_device") { + val zeroOpt = params.zeroDevice.map { addr => LazyScope("wrapped_zero_device") { val zero = LazyModule(new TLZero( address = addr, beatBytes = beatBytes)) zero.node := TLFragmenter(beatBytes, blockBytes) := TLBuffer() := outwardNode + zero }} } } diff --git a/src/main/scala/devices/tilelink/DevNull.scala b/src/main/scala/devices/tilelink/DevNull.scala index 46498f7b9b7..4c7ce547ef3 100644 --- a/src/main/scala/devices/tilelink/DevNull.scala +++ b/src/main/scala/devices/tilelink/DevNull.scala @@ -25,7 +25,7 @@ case class DevNullParams( * They may discard writes, refuse to respond to requests, issue error responses, * or otherwise violate 'expected' memory behavior. */ -abstract class DevNullDevice(params: DevNullParams, minLatency: Int, beatBytes: Int, device: SimpleDevice) +abstract class DevNullDevice(params: DevNullParams, minLatency: Int, beatBytes: Int, protected val device: SimpleDevice) (implicit p: Parameters) extends LazyModule with HasClockDomainCrossing { val xfer = if (params.maxTransfer > 0) TransferSizes(1, params.maxTransfer) else TransferSizes.none diff --git a/src/main/scala/devices/tilelink/Error.scala b/src/main/scala/devices/tilelink/Error.scala index 6931b87175c..5609f3ed96f 100644 --- a/src/main/scala/devices/tilelink/Error.scala +++ b/src/main/scala/devices/tilelink/Error.scala @@ -9,12 +9,30 @@ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import scala.math.min +import freechips.rocketchip.diplomaticobjectmodel.{DiplomaticObjectModelAddressing, HasLogicalTreeNode} +import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode +import freechips.rocketchip.diplomaticobjectmodel.model.{OMErrorDevice, OMComponent} + /** Adds a /dev/null slave that generates TL error response messages */ class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends DevNullDevice(params, minLatency = if (buffer) 1 else 0, beatBytes, new SimpleDevice("error-device", Seq("sifive,error0"))) + with HasLogicalTreeNode { + lazy val logicalTreeNode: LogicalTreeNode = new LogicalTreeNode(() => Some(device)) { + def getOMComponents(resourceBindings: ResourceBindings, children: Seq[OMComponent] = Nil) = { + val Description(name, mapping) = device.describe(resourceBindings) + val memRegions = DiplomaticObjectModelAddressing.getOMMemoryRegions(name, resourceBindings, None) + val interrupts = DiplomaticObjectModelAddressing.describeInterrupts(name, resourceBindings) + Seq(OMErrorDevice( + memoryRegions = memRegions, + interrupts = interrupts, + specifications = Nil + )) + } + } + lazy val module = new LazyModuleImp(this) { import TLMessages._ import TLPermissions._ diff --git a/src/main/scala/subsystem/BaseSubsystem.scala b/src/main/scala/subsystem/BaseSubsystem.scala index a920017523f..d408c4d9d10 100644 --- a/src/main/scala/subsystem/BaseSubsystem.scala +++ b/src/main/scala/subsystem/BaseSubsystem.scala @@ -134,7 +134,21 @@ abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem } } - lazy val logicalTreeNode = new SubsystemLogicalTreeNode() + lazy val logicalTreeNode = { + val subsystemLogicalTreeNode = new SubsystemLogicalTreeNode() + val builtInDevices = Seq( + pbus.builtInDevices, + fbus.builtInDevices, + mbus.builtInDevices, + cbus.builtInDevices + ) + for (builtIn <- builtInDevices) { + builtIn.errorOpt.foreach { error => + LogicalModuleTree.add(subsystemLogicalTreeNode, error.logicalTreeNode) + } + } + subsystemLogicalTreeNode + } } diff --git a/src/main/scala/subsystem/FrontBus.scala b/src/main/scala/subsystem/FrontBus.scala index 4b4adc69a8f..4c45c9bc29d 100644 --- a/src/main/scala/subsystem/FrontBus.scala +++ b/src/main/scala/subsystem/FrontBus.scala @@ -20,5 +20,5 @@ class FrontBus(params: FrontBusParams)(implicit p: Parameters) with CanHaveBuiltInDevices with CanAttachTLMasters with HasTLXbarPhy { - attachBuiltInDevices(params) + val builtInDevices = attachBuiltInDevices(params) } diff --git a/src/main/scala/subsystem/MemoryBus.scala b/src/main/scala/subsystem/MemoryBus.scala index e3573d8745c..7210d686d6d 100644 --- a/src/main/scala/subsystem/MemoryBus.scala +++ b/src/main/scala/subsystem/MemoryBus.scala @@ -59,7 +59,7 @@ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) if (params.replicatorMask == 0) xbar.node else { xbar.node :=* RegionReplicator(params.replicatorMask) } def outwardNode: TLOutwardNode = ProbePicker() :*= xbar.node def busView: TLEdge = xbar.node.edges.in.head - attachBuiltInDevices(params) + val builtInDevices = attachBuiltInDevices(params) def toDRAMController[D,U,E,B <: Data] (name: Option[String] = None, buffer: BufferParams = BufferParams.none) diff --git a/src/main/scala/subsystem/PeripheryBus.scala b/src/main/scala/subsystem/PeripheryBus.scala index 1378b2f48b6..e29224ad9d3 100644 --- a/src/main/scala/subsystem/PeripheryBus.scala +++ b/src/main/scala/subsystem/PeripheryBus.scala @@ -51,7 +51,7 @@ class PeripheryBus(params: PeripheryBusParams, name: String)(implicit p: Paramet def outwardNode: TLOutwardNode = node def busView: TLEdge = fixer.node.edges.in.head - attachBuiltInDevices(params) + val builtInDevices = attachBuiltInDevices(params) def toTile (name: Option[String] = None, buffer: BufferParams = BufferParams.none) diff --git a/src/main/scala/subsystem/SystemBus.scala b/src/main/scala/subsystem/SystemBus.scala index 1c815f0bd01..91546927e91 100644 --- a/src/main/scala/subsystem/SystemBus.scala +++ b/src/main/scala/subsystem/SystemBus.scala @@ -29,7 +29,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) def outwardNode: TLOutwardNode = system_bus_xbar.node def busView: TLEdge = system_bus_xbar.node.edges.in.head - attachBuiltInDevices(params) + val builtInDevices = attachBuiltInDevices(params) def fromTile (name: Option[String], buffer: BufferParams = BufferParams.none, cork: Option[Boolean] = None) From 8ad2f8aa018b131cc8fc68485c6a3f4f315851fb Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Sat, 11 Apr 2020 14:57:48 -0700 Subject: [PATCH 3/9] OMErrorDevice: remove specifications Error device: remove call to specifications in OM --- src/main/scala/devices/tilelink/Error.scala | 3 +-- src/main/scala/diplomaticobjectmodel/model/OMErrorDevice.scala | 1 - 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/src/main/scala/devices/tilelink/Error.scala b/src/main/scala/devices/tilelink/Error.scala index 5609f3ed96f..076b6fa79be 100644 --- a/src/main/scala/devices/tilelink/Error.scala +++ b/src/main/scala/devices/tilelink/Error.scala @@ -27,8 +27,7 @@ class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4) val interrupts = DiplomaticObjectModelAddressing.describeInterrupts(name, resourceBindings) Seq(OMErrorDevice( memoryRegions = memRegions, - interrupts = interrupts, - specifications = Nil + interrupts = interrupts )) } } diff --git a/src/main/scala/diplomaticobjectmodel/model/OMErrorDevice.scala b/src/main/scala/diplomaticobjectmodel/model/OMErrorDevice.scala index ccf5ca5323a..aa344ea8237 100644 --- a/src/main/scala/diplomaticobjectmodel/model/OMErrorDevice.scala +++ b/src/main/scala/diplomaticobjectmodel/model/OMErrorDevice.scala @@ -6,6 +6,5 @@ package freechips.rocketchip.diplomaticobjectmodel.model case class OMErrorDevice( memoryRegions: Seq[OMMemoryRegion], interrupts: Seq[OMInterrupt], - specifications: Seq[OMSpecification], _types: Seq[String] = Seq("OMErrorDevice", "OMDevice", "OMComponent", "OMCompoundType") ) extends OMDevice From f5db4b4b67e7cb971e45e133f8cc0da36b5e9f1a Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Sat, 11 Apr 2020 14:57:33 -0700 Subject: [PATCH 4/9] Add Object model for Zero device OMZeroDevice: fix typos --- .../diplomaticobjectmodel/model/OMZeroDevice.scala | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 src/main/scala/diplomaticobjectmodel/model/OMZeroDevice.scala diff --git a/src/main/scala/diplomaticobjectmodel/model/OMZeroDevice.scala b/src/main/scala/diplomaticobjectmodel/model/OMZeroDevice.scala new file mode 100644 index 00000000000..f641ea25248 --- /dev/null +++ b/src/main/scala/diplomaticobjectmodel/model/OMZeroDevice.scala @@ -0,0 +1,10 @@ +// See LICENSE.SiFive for license details. + +package freechips.rocketchip.diplomaticobjectmodel.model + + +case class OMZeroDevice( + memoryRegions: Seq[OMMemoryRegion], + interrupts: Seq[OMInterrupt], + _types: Seq[String] = Seq("OMZeroDevice", "OMDevice", "OMComponent", "OMCompoundType") +) extends OMDevice From 86ba877946440bda14537ca94696e6c7ee1943a3 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Sat, 11 Apr 2020 15:19:27 -0700 Subject: [PATCH 5/9] TLZero: add OM calls --- src/main/scala/devices/tilelink/Zero.scala | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/src/main/scala/devices/tilelink/Zero.scala b/src/main/scala/devices/tilelink/Zero.scala index 5ea99840d25..2b3f2d229af 100644 --- a/src/main/scala/devices/tilelink/Zero.scala +++ b/src/main/scala/devices/tilelink/Zero.scala @@ -7,6 +7,10 @@ import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink.TLMessages +import freechips.rocketchip.diplomaticobjectmodel.{DiplomaticObjectModelAddressing, HasLogicalTreeNode} +import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode +import freechips.rocketchip.diplomaticobjectmodel.model.{OMZeroDevice, OMComponent} + /** This /dev/null device accepts single beat gets/puts, as well as atomics. * Response data is always 0. Reequests to write data have no effect. */ @@ -22,7 +26,22 @@ class TLZero(address: AddressSet, beatBytes: Int = 4)(implicit p: Parameters) mayDenyPut = false), minLatency = 1, beatBytes = beatBytes, - device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0"))) { + device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0"))) + with HasLogicalTreeNode +{ + + lazy val logicalTreeNode: LogicalTreeNode = new LogicalTreeNode(() => Some(device)) { + def getOMComponents(resourceBindings: ResourceBindings, children: Seq[OMComponent] = Nil) = { + val Description(name, mapping) = device.describe(resourceBindings) + val memRegions = DiplomaticObjectModelAddressing.getOMMemoryRegions(name, resourceBindings, None) + val interrupts = DiplomaticObjectModelAddressing.describeInterrupts(name, resourceBindings) + Seq(OMZeroDevice( + memoryRegions = memRegions, + interrupts = interrupts + )) + } + } + lazy val module = new LazyModuleImp(this) { val (in, edge) = node.in(0) From ba744ca668ac6eb057d1a1ad03af2d57a28921bd Mon Sep 17 00:00:00 2001 From: Albert Chen Date: Sat, 11 Apr 2020 17:43:06 -0700 Subject: [PATCH 6/9] BaseSubsystem: move LogicalTree add out of lazy val include sbus built-in devices LogicalTreeNode --- src/main/scala/subsystem/BaseSubsystem.scala | 25 +++++++++----------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/src/main/scala/subsystem/BaseSubsystem.scala b/src/main/scala/subsystem/BaseSubsystem.scala index d408c4d9d10..6b5d7c711e4 100644 --- a/src/main/scala/subsystem/BaseSubsystem.scala +++ b/src/main/scala/subsystem/BaseSubsystem.scala @@ -134,20 +134,17 @@ abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem } } - lazy val logicalTreeNode = { - val subsystemLogicalTreeNode = new SubsystemLogicalTreeNode() - val builtInDevices = Seq( - pbus.builtInDevices, - fbus.builtInDevices, - mbus.builtInDevices, - cbus.builtInDevices - ) - for (builtIn <- builtInDevices) { - builtIn.errorOpt.foreach { error => - LogicalModuleTree.add(subsystemLogicalTreeNode, error.logicalTreeNode) - } - } - subsystemLogicalTreeNode + lazy val logicalTreeNode = new SubsystemLogicalTreeNode() + + private val builtInDevices = Seq( + sbus.builtInDevices, + pbus.builtInDevices, + fbus.builtInDevices, + mbus.builtInDevices, + cbus.builtInDevices + ) + for (builtIn <- builtInDevices; error <- builtIn.errorOpt) { + LogicalModuleTree.add(logicalTreeNode, error.logicalTreeNode) } } From 5b6f37c61730019bf86cb450ac598c07e626420b Mon Sep 17 00:00:00 2001 From: Albert Chen <40366337+albertchen-sifive@users.noreply.github.com> Date: Sun, 12 Apr 2020 23:01:43 -0700 Subject: [PATCH 7/9] BaseSubsystem: add TLZero LogicalTreeNodes Co-Authored-By: Megan Wachs --- src/main/scala/subsystem/BaseSubsystem.scala | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/main/scala/subsystem/BaseSubsystem.scala b/src/main/scala/subsystem/BaseSubsystem.scala index 6b5d7c711e4..5c0ea797569 100644 --- a/src/main/scala/subsystem/BaseSubsystem.scala +++ b/src/main/scala/subsystem/BaseSubsystem.scala @@ -143,8 +143,13 @@ abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem mbus.builtInDevices, cbus.builtInDevices ) - for (builtIn <- builtInDevices; error <- builtIn.errorOpt) { - LogicalModuleTree.add(logicalTreeNode, error.logicalTreeNode) + builtInDevices.foreach { builtIn => + builtIn.errorOpt.foreach { error => + LogicalModuleTree.add(logicalTreeNode, error.logicalTreeNode) + } + builtIn.zeroOpt.foreach { zero => + LogicalModuleTree.add(logicalTreeNode, zero.logicalTreeNode) + } } } From 1910582708d4aed6d3e5a0bb235d4f6a4b3ceb68 Mon Sep 17 00:00:00 2001 From: Albert Chen Date: Sun, 12 Apr 2020 23:04:47 -0700 Subject: [PATCH 8/9] CanHaveBuiltInDevices: move attach fn to object also add abstract field builtInDevices and fix typos --- .../tilelink/CanHaveBuiltInDevices.scala | 19 +++++++++------ src/main/scala/subsystem/BaseSubsystem.scala | 24 ++++++++++--------- src/main/scala/subsystem/FrontBus.scala | 2 +- src/main/scala/subsystem/MemoryBus.scala | 2 +- src/main/scala/subsystem/PeripheryBus.scala | 2 +- src/main/scala/subsystem/SystemBus.scala | 2 +- 6 files changed, 29 insertions(+), 22 deletions(-) diff --git a/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala b/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala index 6b96851c1c8..016c3684217 100644 --- a/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala +++ b/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala @@ -16,14 +16,14 @@ sealed trait BuiltInDevices { def zeroOpt: Option[TLZero] } -/* Optionally add some built-in devices to a bus wrapper */ -trait CanHaveBuiltInDevices { this: TLBusWrapper => - - def attachBuiltInDevices(params: HasBuiltInDeviceParams): BuiltInDevices = new BuiltInDevices { +object BuiltInDevices { + def attach( + params: HasBuiltInDeviceParams with HasTLBusParams, + outwardNode: TLOutwardNode)(implicit p: Parameters) = new BuiltInDevices { val errorOpt = params.errorDevice.map { dnp => LazyScope("wrapped_error_device") { val error = LazyModule(new TLError( params = dnp, - beatBytes = beatBytes)) + beatBytes = params.beatBytes)) error.node := TLBuffer() := outwardNode error @@ -32,10 +32,15 @@ trait CanHaveBuiltInDevices { this: TLBusWrapper => val zeroOpt = params.zeroDevice.map { addr => LazyScope("wrapped_zero_device") { val zero = LazyModule(new TLZero( address = addr, - beatBytes = beatBytes)) - zero.node := TLFragmenter(beatBytes, blockBytes) := TLBuffer() := outwardNode + beatBytes = params.beatBytes)) + zero.node := TLFragmenter(params.beatBytes, params.blockBytes) := TLBuffer() := outwardNode zero }} } } +/* Optionally add some built-in devices to a bus wrapper */ +trait CanHaveBuiltInDevices { + def builtInDevices: BuiltInDevices +} + diff --git a/src/main/scala/subsystem/BaseSubsystem.scala b/src/main/scala/subsystem/BaseSubsystem.scala index 5c0ea797569..9f54ace1937 100644 --- a/src/main/scala/subsystem/BaseSubsystem.scala +++ b/src/main/scala/subsystem/BaseSubsystem.scala @@ -81,7 +81,7 @@ case object ResetAsynchronousFull extends SubsystemResetScheme case object SubsystemResetSchemeKey extends Field[SubsystemResetScheme](ResetSynchronous) /** Base Subsystem class with no peripheral devices or ports added */ -abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem +abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem with Attachable { override val module: BaseSubsystemModuleImp[BaseSubsystem] @@ -136,18 +136,20 @@ abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem lazy val logicalTreeNode = new SubsystemLogicalTreeNode() - private val builtInDevices = Seq( - sbus.builtInDevices, - pbus.builtInDevices, - fbus.builtInDevices, - mbus.builtInDevices, - cbus.builtInDevices + private val buses = Seq( + sbus, + pbus, + fbus, + mbus, + cbus ) - builtInDevices.foreach { builtIn => - builtIn.errorOpt.foreach { error => + + buses.foreach { bus => + val builtIn = bus.builtInDevices + builtIn.errorOpt.foreach { error => LogicalModuleTree.add(logicalTreeNode, error.logicalTreeNode) - } - builtIn.zeroOpt.foreach { zero => + } + builtIn.zeroOpt.foreach { zero => LogicalModuleTree.add(logicalTreeNode, zero.logicalTreeNode) } } diff --git a/src/main/scala/subsystem/FrontBus.scala b/src/main/scala/subsystem/FrontBus.scala index 4c45c9bc29d..432ca419c9e 100644 --- a/src/main/scala/subsystem/FrontBus.scala +++ b/src/main/scala/subsystem/FrontBus.scala @@ -20,5 +20,5 @@ class FrontBus(params: FrontBusParams)(implicit p: Parameters) with CanHaveBuiltInDevices with CanAttachTLMasters with HasTLXbarPhy { - val builtInDevices = attachBuiltInDevices(params) + val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } diff --git a/src/main/scala/subsystem/MemoryBus.scala b/src/main/scala/subsystem/MemoryBus.scala index 7210d686d6d..6cbe2d85261 100644 --- a/src/main/scala/subsystem/MemoryBus.scala +++ b/src/main/scala/subsystem/MemoryBus.scala @@ -59,7 +59,7 @@ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) if (params.replicatorMask == 0) xbar.node else { xbar.node :=* RegionReplicator(params.replicatorMask) } def outwardNode: TLOutwardNode = ProbePicker() :*= xbar.node def busView: TLEdge = xbar.node.edges.in.head - val builtInDevices = attachBuiltInDevices(params) + val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) def toDRAMController[D,U,E,B <: Data] (name: Option[String] = None, buffer: BufferParams = BufferParams.none) diff --git a/src/main/scala/subsystem/PeripheryBus.scala b/src/main/scala/subsystem/PeripheryBus.scala index e29224ad9d3..1a3c4ce6f7b 100644 --- a/src/main/scala/subsystem/PeripheryBus.scala +++ b/src/main/scala/subsystem/PeripheryBus.scala @@ -51,7 +51,7 @@ class PeripheryBus(params: PeripheryBusParams, name: String)(implicit p: Paramet def outwardNode: TLOutwardNode = node def busView: TLEdge = fixer.node.edges.in.head - val builtInDevices = attachBuiltInDevices(params) + val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) def toTile (name: Option[String] = None, buffer: BufferParams = BufferParams.none) diff --git a/src/main/scala/subsystem/SystemBus.scala b/src/main/scala/subsystem/SystemBus.scala index 91546927e91..4025d398ff9 100644 --- a/src/main/scala/subsystem/SystemBus.scala +++ b/src/main/scala/subsystem/SystemBus.scala @@ -29,7 +29,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) def outwardNode: TLOutwardNode = system_bus_xbar.node def busView: TLEdge = system_bus_xbar.node.edges.in.head - val builtInDevices = attachBuiltInDevices(params) + val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) def fromTile (name: Option[String], buffer: BufferParams = BufferParams.none, cork: Option[Boolean] = None) From 042c8af2d59f73f766e5db8f5bdc66802f7469cd Mon Sep 17 00:00:00 2001 From: Albert Chen Date: Wed, 15 Apr 2020 20:10:51 -0700 Subject: [PATCH 9/9] update OM names and descriptions --- src/main/scala/devices/tilelink/Error.scala | 5 ++++- src/main/scala/devices/tilelink/Zero.scala | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/main/scala/devices/tilelink/Error.scala b/src/main/scala/devices/tilelink/Error.scala index 076b6fa79be..431d7f6742e 100644 --- a/src/main/scala/devices/tilelink/Error.scala +++ b/src/main/scala/devices/tilelink/Error.scala @@ -26,7 +26,10 @@ class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4) val memRegions = DiplomaticObjectModelAddressing.getOMMemoryRegions(name, resourceBindings, None) val interrupts = DiplomaticObjectModelAddressing.describeInterrupts(name, resourceBindings) Seq(OMErrorDevice( - memoryRegions = memRegions, + memoryRegions = memRegions.map(_.copy( + name = "errordevice", + description = "Error Device" + )), interrupts = interrupts )) } diff --git a/src/main/scala/devices/tilelink/Zero.scala b/src/main/scala/devices/tilelink/Zero.scala index 2b3f2d229af..299ba97f9d3 100644 --- a/src/main/scala/devices/tilelink/Zero.scala +++ b/src/main/scala/devices/tilelink/Zero.scala @@ -36,7 +36,10 @@ class TLZero(address: AddressSet, beatBytes: Int = 4)(implicit p: Parameters) val memRegions = DiplomaticObjectModelAddressing.getOMMemoryRegions(name, resourceBindings, None) val interrupts = DiplomaticObjectModelAddressing.describeInterrupts(name, resourceBindings) Seq(OMZeroDevice( - memoryRegions = memRegions, + memoryRegions = memRegions.map(_.copy( + name = "zerodevice", + description = "Zero Device" + )), interrupts = interrupts )) }