From 599562780e15a198894afb29e87144a20fc6d3eb Mon Sep 17 00:00:00 2001
From: John Ingalls <john.ingalls@sifive.com>
Date: Wed, 20 May 2020 22:14:56 -0700
Subject: [PATCH 1/2] BEU ICacheErrors TileLink bus I$ D-channel corrupt or
 denied

---
 src/main/scala/rocket/ICache.scala     | 3 +++
 src/main/scala/tile/BusErrorUnit.scala | 7 ++++---
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala
index 6b2fc87e866..6ab10704ad1 100644
--- a/src/main/scala/rocket/ICache.scala
+++ b/src/main/scala/rocket/ICache.scala
@@ -49,6 +49,7 @@ class ICacheErrors(implicit p: Parameters) extends CoreBundle()(p)
     with CanHaveErrors {
   val correctable = (cacheParams.tagCode.canDetect || cacheParams.dataCode.canDetect).option(Valid(UInt(width = paddrBits)))
   val uncorrectable = (cacheParams.itimAddr.nonEmpty && cacheParams.dataCode.canDetect).option(Valid(UInt(width = paddrBits)))
+  val bus = Valid(UInt(width = paddrBits))
 }
 
 class ICache(val icacheParams: ICacheParams, val hartId: Int)(implicit p: Parameters) extends LazyModule {
@@ -220,6 +221,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
 
     ccover(tl_out.d.bits.corrupt, "D_CORRUPT", "I$ D-channel corrupt")
   }
+  io.errors.bus.valid := tl_out.d.fire() && (tl_out.d.bits.denied || tl_out.d.bits.corrupt)
+  io.errors.bus.bits  := refill_paddr
 
   val vb_array = Reg(init=Bits(0, nSets*nWays))
   when (refill_one_beat) {
diff --git a/src/main/scala/tile/BusErrorUnit.scala b/src/main/scala/tile/BusErrorUnit.scala
index 38d10426f2c..cbb92a682b7 100644
--- a/src/main/scala/tile/BusErrorUnit.scala
+++ b/src/main/scala/tile/BusErrorUnit.scala
@@ -24,11 +24,12 @@ class L1BusErrors(implicit p: Parameters) extends CoreBundle()(p) with BusErrors
   val icache = new ICacheErrors
   val dcache = new DCacheErrors
 
-  def toErrorList = List(None, None,
-      icache.correctable.map((_, "I_CORRECTABLE", "Instruction cache or ITIM correctable ECC error ")),
+  def toErrorList = List(None,
+      Some((icache.bus, "IBUS", "Instruction cache TileLink bus error")),
+      icache.correctable.map((_, "I_CORRECTABLE", "Instruction cache or ITIM correctable ECC error")),
       icache.uncorrectable.map((_, "I_UNCORRECTABLE", "ITIM uncorrectable ECC error")),
       None,
-      Some((dcache.bus, "DBUS", "Load or store TileLink bus error")),
+      Some((dcache.bus, "DBUS", "Load/Store/PTW TileLink bus error")),
       dcache.correctable.map((_, "D_CORRECTABLE", "Data cache correctable ECC error")),
       dcache.uncorrectable.map((_, "D_UNCORRECTABLE", "Data cache uncorrectable ECC error")))
 }

From ae60ff3d7e3ad993f111ff65f8f500c07a9406d8 Mon Sep 17 00:00:00 2001
From: John Ingalls <john.ingalls@sifive.com>
Date: Wed, 20 May 2020 22:38:30 -0700
Subject: [PATCH 2/2] ICache bus error D-Channel address match A-Channel
 request

---
 src/main/scala/rocket/ICache.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala
index 6ab10704ad1..b3c53cd23c6 100644
--- a/src/main/scala/rocket/ICache.scala
+++ b/src/main/scala/rocket/ICache.scala
@@ -222,7 +222,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
     ccover(tl_out.d.bits.corrupt, "D_CORRUPT", "I$ D-channel corrupt")
   }
   io.errors.bus.valid := tl_out.d.fire() && (tl_out.d.bits.denied || tl_out.d.bits.corrupt)
-  io.errors.bus.bits  := refill_paddr
+  io.errors.bus.bits  := (refill_paddr >> blockOffBits) << blockOffBits
 
   val vb_array = Reg(init=Bits(0, nSets*nWays))
   when (refill_one_beat) {