From bf225c0d409d16a8dc2fd7b06af5b1a453f1a54a Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 8 Sep 2020 21:24:27 -0700 Subject: [PATCH 1/3] tilelink: add user bits to the C channel We are still experimenting with user bits in the TL-C setting. However, it does appear necessary to control these bits at the very least for Releases and ProbeAcks which get transformed into Puts. --- src/main/scala/tilelink/Bundles.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/scala/tilelink/Bundles.scala b/src/main/scala/tilelink/Bundles.scala index 1ca08a8d02b..ffcc84c2346 100644 --- a/src/main/scala/tilelink/Bundles.scala +++ b/src/main/scala/tilelink/Bundles.scala @@ -212,6 +212,8 @@ final class TLBundleC(params: TLBundleParameters) val size = UInt(width = params.sizeBits) val source = UInt(width = params.sourceBits) // from val address = UInt(width = params.addressBits) // to + val user = BundleMap(params.requestFields) + val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(width = params.dataBits) val corrupt = Bool() // only applies to *Data messages From 979a45d636dc3c46ce5cc3e2777dde76d2551485 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 8 Sep 2020 21:25:39 -0700 Subject: [PATCH 2/3] CacheCork: don't hardcode AMBAProt; use the masters values This was a total hack. Let's do things properly. --- src/main/scala/tilelink/CacheCork.scala | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/src/main/scala/tilelink/CacheCork.scala b/src/main/scala/tilelink/CacheCork.scala index 661d8af1795..00e8c99d68c 100644 --- a/src/main/scala/tilelink/CacheCork.scala +++ b/src/main/scala/tilelink/CacheCork.scala @@ -6,7 +6,6 @@ import Chisel._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ -import freechips.rocketchip.amba.AMBAProt import scala.math.{min,max} import TLMessages._ @@ -92,15 +91,7 @@ class TLCacheCork(unsafe: Boolean = false, sinkIds: Int = 8)(implicit p: Paramet lgSize = in.c.bits.size, data = in.c.bits.data, corrupt = in.c.bits.corrupt)._2 - c_a.bits.user.lift(AMBAProt).foreach { x => - x.fetch := false.B - x.secure := true.B - x.privileged := true.B - x.bufferable := true.B - x.modifiable := true.B - x.readalloc := true.B - x.writealloc := true.B - } + c_a.bits.user :<= in.c.bits.user // Releases without Data succeed instantly val c_d = Wire(in.d) From 3497cf8217d954883c2ab3421066891c062f4514 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 8 Sep 2020 21:28:57 -0700 Subject: [PATCH 3/3] DCache: providing AMBAProt on C channel is now the cache's responsibility Since the CacheCork does not hard-code this, the cache should. --- src/main/scala/rocket/DCache.scala | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index c7e2d00962e..a9960f81bc3 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -734,6 +734,16 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val newCoh = Wire(init = probeNewCoh) releaseWay := s2_probe_way + tl_out_c.bits.user.lift(AMBAProt).foreach { x => + x.fetch := false.B + x.secure := true.B + x.privileged := true.B + x.bufferable := true.B + x.modifiable := true.B + x.readalloc := true.B + x.writealloc := true.B + } + if (!usingDataScratchpad) { when (s2_victimize) { assert(s2_valid_flush_line || s2_flush_valid || io.cpu.s2_nack)