From 29962dd93d4fc2847a8f038dfa39c36b5a52169e Mon Sep 17 00:00:00 2001 From: John Ingalls Date: Tue, 29 Dec 2020 19:59:25 -0800 Subject: [PATCH] D-Cache TileLink C-Channel drive AMBA PROT bits last connect --- src/main/scala/rocket/DCache.scala | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index 8ba3767d5d3..86ea84fc536 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -784,16 +784,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val newCoh = Wire(init = probeNewCoh) releaseWay := s2_probe_way - tl_out_c.bits.user.lift(AMBAProt).foreach { x => - x.fetch := false.B - x.secure := true.B - x.privileged := true.B - x.bufferable := true.B - x.modifiable := true.B - x.readalloc := true.B - x.writealloc := true.B - } - if (!usingDataScratchpad) { when (s2_victimize) { assert(s2_valid_flush_line || s2_flush_valid || io.cpu.s2_nack) @@ -870,6 +860,16 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { tl_out_c.bits.corrupt := inWriteback && s2_data_error_uncorrectable } + tl_out_c.bits.user.lift(AMBAProt).foreach { x => + x.fetch := false.B + x.secure := true.B + x.privileged := true.B + x.bufferable := true.B + x.modifiable := true.B + x.readalloc := true.B + x.writealloc := true.B + } + dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles dataArb.io.in(2).bits := dataArb.io.in(1).bits dataArb.io.in(2).bits.write := false