diff --git a/Xilinx/VIO/DuplicateInputNames.hs b/Xilinx/VIO/DuplicateInputNames.hs
new file mode 100644
index 0000000..74ecc56
--- /dev/null
+++ b/Xilinx/VIO/DuplicateInputNames.hs
@@ -0,0 +1,15 @@
+module DuplicateInputNames where
+
+import Clash.Prelude
+import Clash.Cores.Xilinx.VIO
+
+type Dom = XilinxSystem
+
+inNames = "a" :> "a" :> Nil
+outNames = "b" :> Nil
+
+topEntity ::
+  "clk" ::: Clock Dom ->
+  "in" ::: Signal Dom (Bit, Bit) ->
+  "out" ::: Signal Dom Bit
+topEntity = vioProbe @Dom inNames outNames 0
diff --git a/Xilinx/VIO/DuplicateInputOutputNames.hs b/Xilinx/VIO/DuplicateInputOutputNames.hs
new file mode 100644
index 0000000..18ef81f
--- /dev/null
+++ b/Xilinx/VIO/DuplicateInputOutputNames.hs
@@ -0,0 +1,15 @@
+module DuplicateInputOutputNames where
+
+import Clash.Prelude
+import Clash.Cores.Xilinx.VIO
+
+type Dom = XilinxSystem
+
+inNames = "a" :> Nil
+outNames = "a" :> Nil
+
+topEntity ::
+  "clk" ::: Clock Dom ->
+  "in" ::: Signal Dom Bit ->
+  "out" ::: Signal Dom Bit
+topEntity = vioProbe @Dom inNames outNames 0
diff --git a/Xilinx/VIO/DuplicateOutputNames.hs b/Xilinx/VIO/DuplicateOutputNames.hs
new file mode 100644
index 0000000..78d29ce
--- /dev/null
+++ b/Xilinx/VIO/DuplicateOutputNames.hs
@@ -0,0 +1,14 @@
+module DuplicateOutputNames where
+
+import Clash.Prelude
+import Clash.Cores.Xilinx.VIO
+
+type Dom = XilinxSystem
+
+inNames = Nil
+outNames = "a" :> "a" :> Nil
+
+topEntity ::
+  "clk" ::: Clock Dom ->
+  "out" ::: Signal Dom (Bit, Bit)
+topEntity = vioProbe @Dom inNames outNames (0, 0)