From 029a821fdde2bfb9cfef43242e8e9104c557df99 Mon Sep 17 00:00:00 2001 From: Ryan Tsien Date: Wed, 7 Aug 2024 10:35:00 +0800 Subject: [PATCH] =?UTF-8?q?new=20presentation:=20=E5=9F=BA=E4=BA=8E=20RISC?= =?UTF-8?q?-V=20=E7=9A=84=20DSP=20=E4=B8=AD=E5=A2=9E=E5=BC=BA=E5=9E=8B=20P?= =?UTF-8?q?WM=20=E7=9A=84=E8=AE=BE=E8=AE=A1=E4=B8=8E=E5=BA=94=E7=94=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Ryan Tsien --- content/en/agenda.md | 6 ++++++ content/zh/agenda.md | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/content/en/agenda.md b/content/en/agenda.md index 2142aa9..e59f192 100644 --- a/content/en/agenda.md +++ b/content/en/agenda.md @@ -414,6 +414,12 @@ a22_B: authors: - name: Sergey Yakushkin title: Director of Software Engineering, Syntacore + - title: 基于 RISC-V 的 DSP 中增强型 PWM 的设计与应用 + time: 13:45 + duration: 15 + authors: + - name: 冯新华 + title: 北京中科昊芯科技有限公司,研发工程师 - title: 使用 RISC-V CPU ASIL B/D 开发集成中的挑战与方法 time: 14:00 duration: 20 diff --git a/content/zh/agenda.md b/content/zh/agenda.md index 3ad1904..aff839f 100644 --- a/content/zh/agenda.md +++ b/content/zh/agenda.md @@ -414,6 +414,12 @@ a22_B: authors: - name: Sergey Yakushkin title: Director of Software Engineering, Syntacore + - title: 基于 RISC-V 的 DSP 中增强型 PWM 的设计与应用 + time: 13:45 + duration: 15 + authors: + - name: 冯新华 + title: 北京中科昊芯科技有限公司,研发工程师 - title: 使用 RISC-V CPU ASIL B/D 开发集成中的挑战与方法 time: 14:00 duration: 20