This RTL package generates a complete coreplex by gluing together a variety of components from other packages, including: tiled Rocket cores, a system bus network, coherence agents, debug devices, interrupt handlers, externally-facing peripherals, clock-crossers and converters from TileLink to external bus protocols (e.g. AXI or AHB).
- BaseCoreplex the base class of a Rocket-chip.
- Configs configure the parameters of a core complex.
- InterruptBus the coreplex interrupt bus.
- MemoryBus the memory bus after LLC.
- PeripheryBus the periphery bus.
- Ports provide various traits to add ports to the system, in some cases converting to different interconnect standards.
- ResetVector constants to define the reset addresses.
- RocketCoreplex extending Rocket coreplex with Rocket Tiles.
- RTC real-time counter.
- SystemBus the coherent bus between tiles and coherent hubs (also split memory and I/O spaces).
Last updated: 16/08/2017
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