RegisterCrossing.md

Rocket/regmapper/RegisterCrossing

Register interface for crossing power domains.

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class BusyRegisterCrossing

A cross domain register interface. When io.bypass is asserted, it ignores the next request with an immediated response. Used as the control logic for an actual data crossing.

class BusyRegisterCrossing extends Module

• I/O

name	type	direction	description
bypass	Bool	I	ignore the next request
master_request_valid	Bool	I	request valid from master
master_request_ready	Bool	O	ready for a request from master
master_response_valid	Bool	O	a request is sent
master_response_ready	Bool	I	master ready for response
crossing_request_valid	Bool	O	a request forwarded to slave
crossing_request_ready	Bool	I	a request is received by slave

class RegisterWriteCrossing

Register crossing write interface module.

class RegisterWriteCrossing[T <: Data](gen: T, sync: Int = 3) extends Module

• I/O

name	type	direction	description
master_clock	Clock	I	clock of the master domain
master_reset	Bool	I	reset of the master domain
master_port.request	DecoupledIO[T]	I	request from master
master_port.response	IrrevocableIO[Bool]	O	response for master
master_bypass	Bool	I	ignore the next request
slave_clock	Clock	I	clock of the slave domain
slave_reset	Bool	I	reset of the slave domain

_{Last updated: 08/07/2017
CC BY-NC-SA 4.0, © (2017) Wei Song
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