Interrupts.md

Rocket/tile/Interrupts

---

class TileInterrupts

The interrupt ports for a Rocket core (CSRFile).

class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p)

• debug Bool debug interrupt.
• mtip Bool timer interrupt pending for machine mode.
• msip Bool software interrupt pending for machine mode.
• meip Bool external interrupt pending for machine mode.
• seip Option[Bool] external interrupt pending for supervisor mode (only when VM is enabled, why?).
• lip Vec[Bool] local interrupt lines. (what for?)

trait HasExternalInterrupts

Use diplomatic interrupts to external interrupts from the coreplex into the tile.

trait HasExternalInterrupts extends HasTileParameters {
  implicit val p: Parameters
  val module: HasExternalInterruptsModule
}

• module HasExternalInterruptsModule pointer to the module implementation.
• intNode IntSinkNode(IntSinkPortSimple())
• csrIntMap () => List[Int] map interrupt to their pin in CSR: mip.
  List(debug:65535, msip:3, mtip:7, meip:11, Option[seip:9], Option[local interrupts:_+16])

trait HasExternalInterruptsBundle

trait HasExternalInterruptsBundle {
  val outer: HasExternalInterrupts
  val interrupts = outer.intNode.bundleIn
}

trait HasExternalInterruptsModule

trait HasExternalInterruptsModule {
  val outer: HasExternalInterrupts
  val io: HasExternalInterruptsBundle
}

• outer HasExternalInterrupts pointer to the LazyModule.
• io HasExternalInterruptsBundle IO ports, inputs only.
• decodeCoreInterrupts (core:TileInterrupts) => Unit assign input signals to internal interrupt lines core.

_{Last updated: 25/07/2017
CC BY-NC-SA 4.0, © (2017) Wei Song
Apache 2.0, © (2016-2017) SiFive, Inc
BSD, © (2012-2014, 2016) The Regents of the University of California (Regents)}