ClockDivider.md

Rocket/util/ClockDivider

Verilog blackbox of clock divider. Utilizing the Chisel2 compatability layer.

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class ClockDivider2

Blockbox of dividing clock by 2.

module ClockDivider2 (output reg clk_out, input clk_in);
   initial clk_out = 1'b0;
   always @(posedge clk_in) begin
      clk_out = ~clk_out; // Must use =, NOT <=
   end
endmodule // ClockDivider2

class Pow2ClockDivider

A configurable clock divider.

class Pow2ClockDivider(pow2: Int) extends Module

• I/O, type and Paramter

name	type	direction	description
pow2	Int	param	set divide ratio to 2^pow2
clock_out	Clock	O	divided clock

_{Last updated: 09/07/2017
CC BY-NC-SA 4.0, © (2017) Wei Song
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