decodercase.vhd

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-- Company: 
-- Engineer: 
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-- Create Date:    19:50:35 04/20/2024 
-- Design Name: 
-- Module Name:    decodercase - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
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-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decodercase is
    Port ( i : in  STD_LOGIC_VECTOR (1 downto 0);
           d : out  STD_LOGIC_VECTOR (3 downto 0));
end decodercase;

architecture Behavioral of decodercase is

begin

process(i)
begin

case i is

when "00" => d <= "0001";
when "01" => d <= "0010";
when "10" => d <= "0100";
when others => d <= "1000";

end case;

end process;

end Behavioral;