CPU_Template.vl

/* CS 354 - Digital Design
   Template for the CPU project (Project 3)

   This file compiles. Don't change the existing code, only add more code 
   using the instructions given as comment.
*/

module D_flip_flop(D,CLK,Q);
   input D,CLK; 
   output Q; 
   wire CLK1, Y;
   not  not1 (CLK1,CLK);
   D_latch D1(D,CLK, Y),
           D2(Y,CLK1,Q);
endmodule 


module D_latch(D,C,Q);
   input D,C; 
   output Q;
   wire x,y,D1,Q1; 
   nand nand1 (x,D, C), 
        nand2 (y,D1,C), 
        nand3 (Q,x,Q1),
        nand4 (Q1,y,Q); 
   not  not1  (D1,D);
endmodule 


module adder(X,Y,Z,S,C);
	input X,Y,Z;
	output S,C;
	wire a,b,c,d,e;
	xor		g1(a,X,Y),
			g2(S,a,Z);
	and		g3(b,X,Y),
			g4(c,X,Z),
			g5(d,Y,Z);
	or		g6(e,b,c),
			g7(C,e,d);
endmodule

module two_input_mux(S,I0,I1,Y);
	input S,I0,I1;
	output Y;
	wire x,y;
	and g1 (x,I0,!S),
		g2 (y,I1,S);
	or	g4 (Y,x,y);
endmodule

module alu(A,B,Less,Bin,Cin,O,Cout,Result);
	input A,B,Less,Bin,Cin;
	input[1:0] O;
	output Result,Cout;
	wire u,v,w,x,y,z;
	two_input_mux 	m1 (Bin,B,!B,x);
	and				g1 (y,A,x);
	or				g2 (z,A,x);
	adder			a1 (A,x,Cin,w,Cout);
	two_input_mux	m2 (O[0],y,z,v),
					m3 (O[0],w,Less,u),
					m4 (O[1],v,u,Result);
endmodule

module sig_alu(A,B,Less,Bin,Cin,O,Result,Set,Overflow);
	input A,B,Less,Bin,Cin;
	input[1:0] O;
	output Result,Set,Overflow;
	wire t,u,v,w,x,y,z;
	two_input_mux 	m1 (Bin,B,!B,x);
	and				g1 (y,A,x);
	or				g2 (z,A,x);
	adder			a1 (A,x,Cin,w,t);
	two_input_mux	m2 (O[0],y,z,v),
					m3 (O[0],w,Less,u),
					m4 (O[1],v,u,Result);
	xor				x1 (Overflow,Bin,A,x,t,w);
	and				g3(Set,w,w);
endmodule

module full_alu(Bin,O,A,B,Result,Zero,Overflow);
	input[3:0] A;
	input[3:0] B;
	input[1:0] O;
	input Bin;
	output[3:0] Result;
	output Zero,Overflow;
	wire set,x,y,z,ze;
	alu			alu0 (A[0],B[0],set,Bin,Bin,O,x,Result[0]),
				alu1 (A[1],B[1],1'b0,Bin,x,O,y,Result[1]),
				alu2 (A[2],B[2],1'b0,Bin,y,O,z,Result[2]);
	sig_alu 	alu3 (A[3],B[3],1'b0,Bin,z,O,Result[3],set,Overflow);
	or			m1	 (ze,Result[0],Result[1],Result[2],Result[3]);
	not 		not1 (Zero,ze);
endmodule

module quad_mux (A,B,S,E,Y);
	input [3:0] A,B;
	input S,E;
	output [3:0] Y;
	
	wire wa,xa,ya,za,wb,xb,yb,zb,aa,ba,ca,da,ab,bb,cb,db;
	
	and 	a1(wa,A[0],!S,!E),
			a2(xa,A[1],!S,!E),
			a3(ya,A[2],!S,!E),
			a4(za,A[3],!S,!E),
			
			a5(wb,B[0],S,!E),
			a6(xb,B[1],S,!E),
			a7(yb,B[2],S,!E),
			a8(zb,B[3],S,!E);
			
	or		o1(Y[0],wa,wb),
			o2(Y[1],xa,xb),
			o3(Y[2],ya,yb),
			o1(Y[3],za,zb);
endmodule

module li_decoder (X,Y,Z,F);
	input X,Y,Z;
	output F;
	
	and 	a1(F,X,!Y,!Z);
endmodule

module cpu (Instruction, WriteData, CLK);
   input [8:0] Instruction;
   input CLK;
   output [3:0] WriteData;

   wire [3:0] A,B;
   wire [8:0] IR;
   wire [3:0] aluOut;
   wire Li;
   wire z,o;
// Declare more wires as needed


/* The instruction register is instantiated below. You have to provide 
   the module definition (the module header and ports are already provided
   below). The OP code and other fiels of this register that have to be 
   passed to other modules must be represented by their respective 
   indices (see the register file instance below).
*/
	instr_reg 	instr(Instruction,IR,CLK);


// Define a module for the quadruple 2x1 mux and instatiate it here.

	quad_mux	qmux(IR[5:2],aluOut[3:0],Li,1'b0,WriteData[3:0]);

// Define a module for the LI decoder and instantiate it here.

	li_decoder	lid(Instruction[8],Instruction[7],Instruction[6],Li);

// register file (the module definition is incuded in this file)

	regfile 	regs(IR[5:4],IR[3:2],IR[1:0],WriteData,A,B,CLK);


// Define a module for the ALU and instantiate it here.
	full_alu	alus(IR[8],IR[7:6],A,B,aluOut[3:0],z,o);
	//full_alu(Bin,O,A,B,Result,Zero,Overflow);
endmodule


// Instruction register. Must be completed. 

module instr_reg (Instruction,IR,CLK);
   input [8:0] Instruction;
   input CLK;
   output [8:0] IR;

// add D flip-flops here  
	D_flip_flop		d0 (Instruction[0],CLK,IR[0]),
					d1 (Instruction[1],CLK,IR[1]),
					d2 (Instruction[2],CLK,IR[2]),
					d3 (Instruction[3],CLK,IR[3]),
					d4 (Instruction[4],CLK,IR[4]),
					d5 (Instruction[5],CLK,IR[5]),
					d6 (Instruction[6],CLK,IR[6]),
					d7 (Instruction[7],CLK,IR[7]),
					d8 (Instruction[8],CLK,IR[8]);
endmodule



/* 4-bit register file implemented in behavioral modeling (don't change it). 
   Dont't use behavioral modeling for the other CPU modules. They 
   must be implemented at gate level (no reg data, assign, and always).
*/

module regfile (ReadReg1,ReadReg2,WriteReg,WriteData,ReadData1,ReadData2,CLK);
  input [1:0] ReadReg1,ReadReg2,WriteReg;
  input [3:0] WriteData;
  input CLK;
  output [3:0] ReadData1,ReadData2;
  reg [3:0] Regs[0:3]; 
  assign ReadData1 = Regs[ReadReg1];
  assign ReadData2 = Regs[ReadReg2];
  initial Regs[0] = 0;
  always @(negedge CLK)
     Regs[WriteReg] <= WriteData;
endmodule


// Test module. Add more instructions as provided in the test program.

module test_cpu;
   reg [8:0] Instruction;
   reg CLK;
   wire [3:0] WriteData;
   cpu cpu1 (Instruction, WriteData, CLK);

   initial
   begin
			Instruction = 9'b100111110; // LI  $2, 15  # load decimal 15 in $2
		#1 CLK=1;
		#1 CLK=0; // negative edge - execute instruction
			Instruction = 9'b100100011; // LI  $3, 8  # load decimal 8 in $3
		#1 CLK=1;
		#1 CLK=0; // negative edge - execute instruction
			Instruction = 9'b000101101; // AND $1, $2, $3   # $1 = $2 AND $3 (two's complement -8) 
		#1 CLK=1;
		#1 CLK=0; // negative edge - execute instruction
			Instruction = 9'b110011011; // SUB $3, $1, $2   # $3 = $1 - $2 = -8 - (-1) = -7 
		#1 CLK=1;
		#1 CLK=0; // negative edge - execute instruction
			Instruction = 9'b111110010; // SLT $2, $3, $0   # $2 = 1 ($3 < 0)
		#1 CLK=1;
		#1 CLK=0; // negative edge - execute instruction
	  		Instruction = 9'b010101101; // ADD $1, $2, $3   # $1 = $2 + $3 = 1 + (-7) = -6
		#1 CLK=1;
		#1 CLK=0; // negative edge - execute instruction
			Instruction = 9'b110000101; // SUB $1, $0, $1   # $1 = $0 - $1 = 0 - (-6) = 6 
		#1 CLK=1;
		#1 CLK=0; // negative edge - execute instruction
			Instruction = 9'b001011011; // OR  $3, $1, $2   # $3 = $1 OR $2 = 7
		#1 CLK=1;
		#1 CLK=0; // negative edge - execute instruction
/* Add machine code for the test program instructions here.
   Use the format shown above. Pay attention to the register
   order - the destination register is first in the assembly code
   and last (LSB) in the machine code.
   After each instruction a negative edge must be generated.
*/

   end

   initial
   begin
      $display("\nCLK Instruction WriteData\n-------------------------"); 
      $monitor("%b   %b   %b", CLK, Instruction, WriteData);
   end

endmodule