Make TYP_SIMD32 be xarch only (#82624)

* Make `TYP_SIMD32` be xarch only * Applying formatting patch
dotnet · Feb 24, 2023 · 4aa1571 · 4aa1571
1 parent 319fcd9
commit 4aa1571
Show file tree

Hide file tree

Showing 19 changed files with 107 additions and 28 deletions.
diff --git a/src/coreclr/jit/assertionprop.cpp b/src/coreclr/jit/assertionprop.cpp
@@ -3220,6 +3220,7 @@ GenTree* Compiler::optVNConstantPropOnTree(BasicBlock* block, GenTree* tree)
             break;
         }
 
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
         {
             simd32_t value = vnStore->ConstantValue<simd32_t>(vnCns);
@@ -3230,7 +3231,7 @@ GenTree* Compiler::optVNConstantPropOnTree(BasicBlock* block, GenTree* tree)
             conValTree = vecCon;
             break;
         }
-        break;
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
         case TYP_BYREF:

diff --git a/src/coreclr/jit/compiler.h b/src/coreclr/jit/compiler.h
@@ -7638,7 +7638,7 @@ class Compiler
         return ((type == TYP_SIMD16) || (type == TYP_SIMD12));
     }
 #else // !defined(TARGET_AMD64) && !defined(TARGET_ARM64)
-#error("Unknown target architecture for FEATURE_SIMD")
+#error("Unknown target architecture for FEATURE_PARTIAL_SIMD_CALLEE_SAVE")
 #endif // !defined(TARGET_AMD64) && !defined(TARGET_ARM64)
 #endif // FEATURE_PARTIAL_SIMD_CALLEE_SAVE
 
@@ -8511,8 +8511,10 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
                     return NO_CLASS_HANDLE;
                 }
 
+#if defined(TARGET_XARCH)
                 case TYP_SIMD32:
                     break;
+#endif // TARGET_XARCH
 
                 default:
                     unreached();
@@ -8615,8 +8617,10 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
                 return m_simdHandleCache->SIMDVector3Handle;
             case TYP_SIMD16:
                 return m_simdHandleCache->CanonicalSimd16Handle;
+#if defined(TARGET_XARCH)
             case TYP_SIMD32:
                 return m_simdHandleCache->CanonicalSimd32Handle;
+#endif // TARGET_XARCH
             default:
                 unreached();
         }
@@ -8859,10 +8863,12 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
         {
             simdType = TYP_SIMD16;
         }
+#if defined(TARGET_XARCH)
         else if (size == 32)
         {
             simdType = TYP_SIMD32;
         }
+#endif // TARGET_XARCH
         else
         {
             noway_assert(!"Unexpected size for SIMD type");

diff --git a/src/coreclr/jit/emit.cpp b/src/coreclr/jit/emit.cpp
@@ -7892,6 +7892,7 @@ CORINFO_FIELD_HANDLE emitter::emitFltOrDblConst(double constValue, emitAttr attr
     return emitComp->eeFindJitDataOffs(cnum);
 }
 
+#if defined(FEATURE_SIMD)
 //------------------------------------------------------------------------
 // emitSimd8Const: Create a simd8 data section constant.
 //
@@ -7908,7 +7909,6 @@ CORINFO_FIELD_HANDLE emitter::emitSimd8Const(simd8_t constValue)
     // to constant data, not a real static field.
     CLANG_FORMAT_COMMENT_ANCHOR;
 
-#if defined(FEATURE_SIMD)
     unsigned cnsSize  = 8;
     unsigned cnsAlign = cnsSize;
 
@@ -7921,9 +7921,6 @@ CORINFO_FIELD_HANDLE emitter::emitSimd8Const(simd8_t constValue)
 
     UNATIVE_OFFSET cnum = emitDataConst(&constValue, cnsSize, cnsAlign, TYP_SIMD8);
     return emitComp->eeFindJitDataOffs(cnum);
-#else
-    unreached();
-#endif // !FEATURE_SIMD
 }
 
 CORINFO_FIELD_HANDLE emitter::emitSimd16Const(simd16_t constValue)
@@ -7933,7 +7930,6 @@ CORINFO_FIELD_HANDLE emitter::emitSimd16Const(simd16_t constValue)
     // to constant data, not a real static field.
     CLANG_FORMAT_COMMENT_ANCHOR;
 
-#if defined(FEATURE_SIMD)
     unsigned cnsSize  = 16;
     unsigned cnsAlign = cnsSize;
 
@@ -7946,35 +7942,29 @@ CORINFO_FIELD_HANDLE emitter::emitSimd16Const(simd16_t constValue)
 
     UNATIVE_OFFSET cnum = emitDataConst(&constValue, cnsSize, cnsAlign, TYP_SIMD16);
     return emitComp->eeFindJitDataOffs(cnum);
-#else
-    unreached();
-#endif // !FEATURE_SIMD
 }
 
+#if defined(TARGET_XARCH)
 CORINFO_FIELD_HANDLE emitter::emitSimd32Const(simd32_t constValue)
 {
     // Access to inline data is 'abstracted' by a special type of static member
     // (produced by eeFindJitDataOffs) which the emitter recognizes as being a reference
     // to constant data, not a real static field.
     CLANG_FORMAT_COMMENT_ANCHOR;
 
-#if defined(FEATURE_SIMD)
     unsigned cnsSize  = 32;
     unsigned cnsAlign = cnsSize;
 
-#ifdef TARGET_XARCH
     if (emitComp->compCodeOpt() == Compiler::SMALL_CODE)
     {
         cnsAlign = dataSection::MIN_DATA_ALIGN;
     }
-#endif // TARGET_XARCH
 
     UNATIVE_OFFSET cnum = emitDataConst(&constValue, cnsSize, cnsAlign, TYP_SIMD32);
     return emitComp->eeFindJitDataOffs(cnum);
-#else
-    unreached();
-#endif // !FEATURE_SIMD
 }
+#endif // TARGET_XARCH
+#endif // FEATURE_SIMD
 
 /*****************************************************************************
  *

diff --git a/src/coreclr/jit/emit.h b/src/coreclr/jit/emit.h
@@ -2058,9 +2058,13 @@ class emitter
 #endif // TARGET_AMD64
 
     CORINFO_FIELD_HANDLE emitFltOrDblConst(double constValue, emitAttr attr);
+#if defined(FEATURE_SIMD)
     CORINFO_FIELD_HANDLE emitSimd8Const(simd8_t constValue);
     CORINFO_FIELD_HANDLE emitSimd16Const(simd16_t constValue);
+#if defined(TARGET_XARCH)
     CORINFO_FIELD_HANDLE emitSimd32Const(simd32_t constValue);
+#endif // TARGET_XARCH
+#endif // FEATURE_SIMD
     regNumber emitInsBinary(instruction ins, emitAttr attr, GenTree* dst, GenTree* src);
     regNumber emitInsTernary(instruction ins, emitAttr attr, GenTree* dst, GenTree* src1, GenTree* src2);
     void emitInsLoadInd(instruction ins, emitAttr attr, regNumber dstReg, GenTreeIndir* mem);

diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp
@@ -3045,6 +3045,7 @@ unsigned Compiler::gtHashValue(GenTree* tree)
                 switch (vecCon->TypeGet())
                 {
 #if defined(FEATURE_SIMD)
+#if defined(TARGET_XARCH)
                     case TYP_SIMD32:
                     {
                         add = genTreeHashAdd(ulo32(add), vecCon->gtSimd32Val.u32[7]);
@@ -3053,6 +3054,7 @@ unsigned Compiler::gtHashValue(GenTree* tree)
                         add = genTreeHashAdd(ulo32(add), vecCon->gtSimd32Val.u32[4]);
                         FALLTHROUGH;
                     }
+#endif // TARGET_XARCH
 
                     case TYP_SIMD16:
                     {
@@ -7274,13 +7276,17 @@ GenTree* Compiler::gtNewAllBitsSetConNode(var_types type)
         case TYP_SIMD8:
         case TYP_SIMD12:
         case TYP_SIMD16:
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
+#endif // TARGET_XARCH
+        {
             allBitsSet                                 = gtNewVconNode(type);
             allBitsSet->AsVecCon()->gtSimd32Val.i64[0] = -1;
             allBitsSet->AsVecCon()->gtSimd32Val.i64[1] = -1;
             allBitsSet->AsVecCon()->gtSimd32Val.i64[2] = -1;
             allBitsSet->AsVecCon()->gtSimd32Val.i64[3] = -1;
             break;
+        }
 #endif // FEATURE_SIMD
 
         default:
@@ -7315,7 +7321,9 @@ GenTree* Compiler::gtNewZeroConNode(var_types type)
         case TYP_SIMD8:
         case TYP_SIMD12:
         case TYP_SIMD16:
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
+#endif // TARGET_XARCH
         {
             zero                          = gtNewVconNode(type);
             zero->AsVecCon()->gtSimd32Val = {};
@@ -7355,7 +7363,9 @@ GenTree* Compiler::gtNewOneConNode(var_types type, var_types simdBaseType /* = T
         case TYP_SIMD8:
         case TYP_SIMD12:
         case TYP_SIMD16:
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
+#endif // TARGET_XARCH
         {
             GenTreeVecCon* vecCon = gtNewVconNode(type);
 
@@ -11559,13 +11569,15 @@ void Compiler::gtDispConst(GenTree* tree)
                     break;
                 }
 
+#if defined(TARGET_XARCH)
                 case TYP_SIMD32:
                 {
                     simd32_t simdVal = vecCon->gtSimd32Val;
                     printf("<0x%016llx, 0x%016llx, 0x%016llx, 0x%016llx>", simdVal.u64[0], simdVal.u64[1],
                            simdVal.u64[2], simdVal.u64[3]);
                     break;
                 }
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
                 default:

diff --git a/src/coreclr/jit/gentree.h b/src/coreclr/jit/gentree.h
@@ -3386,11 +3386,13 @@ struct GenTreeVecCon : public GenTree
                 return (gtSimd16Val.u64[0] == 0xFFFFFFFFFFFFFFFF) && (gtSimd16Val.u64[1] == 0xFFFFFFFFFFFFFFFF);
             }
 
+#if defined(TARGET_XARCH)
             case TYP_SIMD32:
             {
                 return (gtSimd32Val.u64[0] == 0xFFFFFFFFFFFFFFFF) && (gtSimd32Val.u64[1] == 0xFFFFFFFFFFFFFFFF) &&
                        (gtSimd32Val.u64[2] == 0xFFFFFFFFFFFFFFFF) && (gtSimd32Val.u64[3] == 0xFFFFFFFFFFFFFFFF);
             }
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
             default:
@@ -3430,13 +3432,15 @@ struct GenTreeVecCon : public GenTree
                        (left->gtSimd16Val.u64[1] == right->gtSimd16Val.u64[1]);
             }
 
+#if defined(TARGET_XARCH)
             case TYP_SIMD32:
             {
                 return (left->gtSimd32Val.u64[0] == right->gtSimd32Val.u64[0]) &&
                        (left->gtSimd32Val.u64[1] == right->gtSimd32Val.u64[1]) &&
                        (left->gtSimd32Val.u64[2] == right->gtSimd32Val.u64[2]) &&
                        (left->gtSimd32Val.u64[3] == right->gtSimd32Val.u64[3]);
             }
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
             default:
@@ -3467,11 +3471,13 @@ struct GenTreeVecCon : public GenTree
                 return (gtSimd16Val.u64[0] == 0x0000000000000000) && (gtSimd16Val.u64[1] == 0x0000000000000000);
             }
 
+#if defined(TARGET_XARCH)
             case TYP_SIMD32:
             {
                 return (gtSimd32Val.u64[0] == 0x0000000000000000) && (gtSimd32Val.u64[1] == 0x0000000000000000) &&
                        (gtSimd32Val.u64[2] == 0x0000000000000000) && (gtSimd32Val.u64[3] == 0x0000000000000000);
             }
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
             default:

diff --git a/src/coreclr/jit/hwintrinsic.cpp b/src/coreclr/jit/hwintrinsic.cpp
@@ -126,7 +126,7 @@ CORINFO_CLASS_HANDLE Compiler::gtGetStructHandleForHWSIMD(var_types simdType, Co
                 assert(!"Didn't find a class handle for simdType");
         }
     }
-#ifdef TARGET_XARCH
+#if defined(TARGET_XARCH)
     else if (simdType == TYP_SIMD32)
     {
         switch (simdBaseJitType)

diff --git a/src/coreclr/jit/importervectorization.cpp b/src/coreclr/jit/importervectorization.cpp
@@ -82,7 +82,7 @@ static bool ConvertToLowerCase(WCHAR* input, WCHAR* mask, int length)
 //
 static GenTreeVecCon* CreateConstVector(Compiler* comp, var_types simdType, WCHAR* cns)
 {
-#ifdef TARGET_XARCH
+#if defined(TARGET_XARCH)
     if (simdType == TYP_SIMD32)
     {
         simd32_t       simd32Val = {};

diff --git a/src/coreclr/jit/instr.cpp b/src/coreclr/jit/instr.cpp
@@ -802,11 +802,13 @@ CodeGen::OperandDesc CodeGen::genOperandDesc(GenTree* op)
                         return OperandDesc(emit->emitSimd16Const(constValue));
                     }
 
+#if defined(TARGET_XARCH)
                     case TYP_SIMD32:
                     {
                         simd32_t constValue = op->AsVecCon()->gtSimd32Val;
                         return OperandDesc(emit->emitSimd32Const(constValue));
                     }
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
                     default:

diff --git a/src/coreclr/jit/lclvars.cpp b/src/coreclr/jit/lclvars.cpp
@@ -3792,7 +3792,9 @@ void Compiler::lvaSortByRefCount()
                 case TYP_SIMD8:
                 case TYP_SIMD12:
                 case TYP_SIMD16:
+#if defined(TARGET_XARCH)
                 case TYP_SIMD32:
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
                 case TYP_STRUCT:
                     break;

diff --git a/src/coreclr/jit/lowerarmarch.cpp b/src/coreclr/jit/lowerarmarch.cpp
@@ -1085,8 +1085,6 @@ void Lowering::LowerHWIntrinsicFusedMultiplyAddScalar(GenTreeHWIntrinsic* node)
 //
 GenTree* Lowering::LowerHWIntrinsic(GenTreeHWIntrinsic* node)
 {
-    assert(node->TypeGet() != TYP_SIMD32);
-
     if (node->TypeGet() == TYP_SIMD12)
     {
         // GT_HWINTRINSIC node requiring to produce TYP_SIMD12 in fact

diff --git a/src/coreclr/jit/lsra.cpp b/src/coreclr/jit/lsra.cpp
@@ -733,7 +733,12 @@ LinearScan::LinearScan(Compiler* theCompiler)
             availableRegs[i] = &availableDoubleRegs;
         }
 #ifdef FEATURE_SIMD
+#if defined(TARGET_XARCH)
         else if ((thisType >= TYP_SIMD8) && (thisType <= TYP_SIMD32))
+#else
+        else if ((thisType >= TYP_SIMD8) && (thisType <= TYP_SIMD16))
+#endif // TARGET_XARCH
+
         {
             availableRegs[i] = &availableDoubleRegs;
         }
@@ -1595,8 +1600,12 @@ bool LinearScan::isRegCandidate(LclVarDsc* varDsc)
         case TYP_SIMD8:
         case TYP_SIMD12:
         case TYP_SIMD16:
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
+#endif // TARGET_XARCH
+        {
             return !varDsc->lvPromoted;
+        }
 #endif // FEATURE_SIMD
 
         case TYP_STRUCT:

diff --git a/src/coreclr/jit/morphblock.cpp b/src/coreclr/jit/morphblock.cpp
@@ -596,11 +596,16 @@ void MorphInitBlockHelper::TryInitFieldByField()
             case TYP_SIMD8:
             case TYP_SIMD12:
             case TYP_SIMD16:
+#if defined(TARGET_XARCH)
             case TYP_SIMD32:
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
+            {
                 assert(initPattern == 0);
                 src = m_comp->gtNewZeroConNode(fieldType);
                 break;
+            }
+
             default:
                 unreached();
         }

diff --git a/src/coreclr/jit/optcse.cpp b/src/coreclr/jit/optcse.cpp
@@ -2655,9 +2655,10 @@ class CSE_Heuristic
                 //
                 int spillSimdRegInProlog = 1;
 
-                // If we have a SIMD32 that is live across a call we have even higher spill costs
-                //
-                if (candidate->Expr()->TypeGet() == TYP_SIMD32)
+// If we have a SIMD32 that is live across a call we have even higher spill costs
+//
+#if defined(TARGET_XARCH)
+                if (candidate->Expr()->TypeIs(TYP_SIMD32))
                 {
                     // Additionally for a simd32 CSE candidate we assume that and second spilled/restore will be needed.
                     // (to hold the upper half of the simd32 register that isn't preserved across the call)
@@ -2669,6 +2670,7 @@ class CSE_Heuristic
                     //
                     cse_use_cost += 2;
                 }
+#endif // TARGET_XARCH
 
                 extra_yes_cost = (BB_UNITY_WEIGHT_UNSIGNED * spillSimdRegInProlog) * 3;
             }