****** START compiling TestEntrypoint:Test_Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericOverConstrainedType_NonGeneric_NormalMethod[System.__Canon,System.__Canon]() (MethodHash=710bd4fc) Generating code for Windows x64 OPTIONS: compCodeOpt = BLENDED_CODE OPTIONS: compDbgCode = true OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false OPTIONS: Jit invoked for ngen IL to import: IL_0000 fe 16 08 00 00 1b constrained. 0x1B000008 IL_0006 fe 06 01 00 00 0a ldftn 0xA000001 IL_000c fe 13 volatile. IL_000e 80 03 00 00 0a ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_GenericOverGenericStructOverTypeParameterGenericValuetype_GenericOverInt32_GenericOverObject_NormalMethod[System.__Canon]()' during 'Generate code' (IL size 47; hash 0x0 stsfld 0xA0000030be97a2; MinOpts) IL_0013 ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 feILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_NonGenericNonGenericValuetype_GenericOverInt32_CuriouslyRecurringGeneric_GenericMethodOverString[System.__Canon]()' during 'Generate code' (IL size 47; hash 0x49a2e267; 1MinOpts) 3ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_GenericOverStructGenericValuetype_GenericOverString_GenericOverString_GenericMethodOverString[System.__Canon]()' during 'Generate code' (IL size 47; hash 0x23ad0f52; MinOpts) ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_GenericOverReferenceType_ClassAGenericClass_GenericOverString_GenericOverString_GenericMethodOverInt[System.__Canon]()' during 'Generate code' (IL size 47; hash 0xf4ad2bdd; MinOpts) volatile. IL_0015 7e 03 00 00 0a ldsfld 0xA00000ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 3 IL_001a 29 01ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_GenericOverStructGenericClass_GenericOverConstrainedType_CuriouslyRecurringGeneric_GenericMethodOverInt[System.__Canon,System.__Canon]()' during 'Generate code' (IL size 47; hash 0x9a477855; MinOpts) 00 00 11 calli 0x11000001 IL_001f 72 83 31 04 70 ldstr 0x70043183 IL_0024 72 5a 3d 03 70 ldstr 0x70033D5A IL_0029 28 02 00 00 0a call 0xA000002ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 IL_002e 2aILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_NonGenericNonGenericClass_GenericOverInt32_NonGeneric_GenericMethodOverTypeParameter[System.__Canon]()' during 'Generate code' (IL size 47; hash 0xd3a24e21; MinOpts) ret 'GenCtxt' passed in register rcx lvaGrabTemp returning 1 (V01 loc0) (a long lifetime temp) called for OutgoingArgSpace. Local V01 should not be enregistered because: it is address exposed ; Initial local variable assignments ; ; V00 TypeCtx long ; V01 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 *************** In compInitDebuggingInfo() for TestEntrypoint:Test_Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericOverConstrainedType_NonGeneric_NormalMethod[System.__Canon,System.__Canon]() ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_NonGenericNonGenericClass_GenericOverConstrainedType_GenericOverString_GenericMethodOverInt[System.__Canon,System.__Canon]()' during 'Generate code' (IL size 62; hash 0xa570c667; MinOpts) getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 1 VarNum LVNum Name Beg End 0: 00h 00h V00 TypeCtx 000h 02Fh New Basic Block BB01 [0000] created. New scratch BB01 Debuggable code - Add new BB01 [0000] to perform initialization of variables info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for TestEntrypoint:Test_Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericOverConstrainedType_NonGeneric_NormalMethod[System.__Canon,System.__Canon]() weight= 65 : state 181 [ constrained ] weight=102 : state 173 [ ldftn ] weight=-44 : state 178 [ volatile ] weight=125 : state 114 [ stsfld ] weight=-44 : state 178 [ volatile ] ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 weight=159 : state 112 [ ldsfld ] weight= 65 : state 41 [ calli ] ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 weight= 66 : state 102 [ ldstr ] ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_GenericOverGenericStructOverTypeParameterGenericClass_GenericOverString_CuriouslyRecurringGeneric_GenericMethodOverTypeParameter[System.__Canon]()' during 'Generate code' (IL size 47; hash 0x2002870e; MinOpts) ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_GenericOverTypeParameterGenericClass_GenericOverInt32_GenericOverString_GenericMethodOverTypeParameter[System.__Canon]()' during 'Generate code' (IL size 47; hash 0x5d1c83aa; MinOpts) weight= 66 : state 102 [ ldstr ] ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 weight= 79 : state 40 [ call ] ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericOverConstrainedType_GenericOverObject_GenericMethodOverTypeParameter[System.__Canon,System.__Canon]()' during 'Genweight= 19 : state 42 [ ret ] erate code' (IL size 62; hash 0xd6c990b5; MinOpts) Jump targets: none New Basic Block BB02 [0001] created. BB02 [0001] [000..02F) Setting edge weights for BB01 -> BB02 to [0 .. 3.402823e+38] setting likelihood of BB01 -> BB02 to 1 Inline candidate looks like a wrapper method. Multiplier increased to 1. Inline candidate callsite is hot. Multiplier increased to 4.ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 Callsite has profile data: 1. Multiplier limited to 16.8.ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_GenericOverStructGenericClass_GenericOverInt32_GenericOverObject_GenericMethodOverTypeParameter[System.__Canon]()' during 'Generate code' (IL size 47; hash 0x9e4e8b0c; MinOpts) calleeNativeSizeEstimate=658 callsiteNativeSizeEstimate=55 benefit multiplier=16.8 threshold=924 Native estimate for function size is within threshold for inlining 65.8 <= 92.4 (multiplier = 16.8) INLINER: during 'prejit' result 'PreJIT Success' reason 'PreJIT Success' for 'n/a' calling 'TestEntrypoint:Test_Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericOverConstrainedType_NonGeneric_NormalMethod[System.__Canon,System.__Canon]()' INLINER: during 'prejit' result 'PreJIT Success' reason 'PreJIT Success' CLFLG_MINOPT set for method TestEntrypoint:Test_Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericOverConstrainedType_NonGeneric_NormalMethod[System.__Canon,System.__Canon]() IL Code Size,Instr 47, 8, Basic Block count 2, Local Variable Num,Ref count 2, 0 for method TestEntrypoint:Test_Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericOverConstrainedType_NonGeneric_NormalMethod[System.__Canon,System.__Canon]() OPTIONS: opts.MinOpts() == true Basic block list for 'TestEntrypoint:Test_Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericOverConstrainedType_NonGeneric_NormalMethod[System.__Canon,System.__Canon]()' ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i internal q BB02 [0001] 1 BB01 1 [000..02F) (return) ---------------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Pre-import *************** Finishing PHASE Pre-import Trees after Pre-import ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i internal q BB02 [0001] 1 BB01 1 [000..02F) (return) ---------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [???..???) -> BB02 (always), preds={} succs={BB02} ***** BB01 [0000] STMT00000 ( ??? ... ??? ) [000000] -----------ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_GenericOverStructGenericValuetype_GenericOverConstrainedType_NonGeneric_GenericMethodOverInt[System.__Canon,System.__Canon]()' during 'Generate code' (IL size 47; hash 0xff512ad7; MinOpts) * NOP void ------------ BB02 [0001] [000..02F) (return), preds={BB01} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Profile incorporation BBOPT not set *************** Finishing PHASE Profile incorporation [no changes] *************** Starting PHASE Importation Marking leading BBF_INTERNAL block BB01 as BBF_IMPORTED impImportBlockPending for BB02 Importing BB02 (PC=000) of 'TestEntrypoint:Test_Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericOverConstrainedType_NonGeneric_NormalMethod[System.__Canon,System.__Canon]()' [ 0] 0 (0x000) constrained. (1B000008) ldftn 0A000001 [ 1] 12 (0x00c) volatile.stsfld 0A000003 STMT00001 ( 0x000[E-] ... ??? ) [000006] VACXGO----- * STOREIND long [000005] --CXG------ +--* ADD byref [000003] H-CXG------ | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000004] ----------- | \--* CNS_INT long 8 Fseq[FtnHolder] [000002] --C-G------ \--* CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE [000001] !---------- arg0 \--* LCL_VAR long V00 TypeCtx [ 0] 19 (0x013) volatile.ldsfld 0A000003 [ 1] 26 (0x01a) calli 11000001 In Compiler::impImportCall: opcode is calli, kind=0, callRetType is void, structSize is 0 Marking call [000011] as fat pointer candidate STMT00002 ( 0x013[E-] ... ??? ) [000011] --CXG------ * CALL ind void [000010] V-CXGO----- calli tgt \--* IND long [000009] --CXG------ \--* ADD byref [000007] H-CXG------ +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000008] ----------- \--* CNS_INT long 8 Fseq[FtnHolder] [ 0] 31 (0x01f) ldstr 70043183 [ 1] 36 (0x024) ldstr 70033D5A [ 2] 41 (0x029) call 0A000002 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 STMT00003 ( 0x01F[E-] ... ??? ) [000014] --C-G------ * CALL void Statics:CheckForFailure(System.String,System.String) [000012] ----------- arg0 +--* CNS_STR ref [000013] ----------- arg1 \--* CNS_STR ref [ 0] 46 (0x02e) ret STMT00004 ( 0x02E[E-] ... ??? ) [000015] ----------- * RETURN void *************** Finishing PHASE Importation Trees after Importation ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i internal q BB02 [0001] 1 BB01 1 [000..02F) (return) i ---------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [???..???) -> BB02 (always), preds={} succs={BB02} ***** BB01 [0000] STMT00000 ( ??? ... ??? ) [000000] ----------- * NOP void ------------ BB02 [0001] [000..02F) (return), preds={BB01} succs={} ***** BB02 [0001] STMT00001 ( 0x000[E-] ... 0x00E ) [000006] VACXGO----- * STOREIND long [000005] --CXG------ +--* ADD byref [000003] H-CXG------ | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000004] ----------- | \--* CNS_INT long 8 Fseq[FtnHolder] [000002] --C-G------ \--* CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE [000001] !---------- arg0 \--* LCL_VAR long V00 TypeCtx ***** BB02 [0001] STMT00002 ( 0x013[E-] ... 0x02E ) [000011] --CXG------ * CALL ind void [000010] V-CXGO----- calli tgt \--* IND long [000009] --CXG------ \--* ADD byref [000007] H-CXG------ +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000008] ----------- \--* CNS_INT long 8 Fseq[FtnHolder] ***** BB02 [0001] STMT00003 ( 0x01F[E-] ... ??? ) [000014] --C-G------ * CALL void Statics:CheckForFailure(System.String,System.String) [000012] ----------- arg0 +--* CNS_STR ref [000013] ----------- arg1 \--* CNS_STR ref ***** BB02 [0001] STMT00004 ( 0x02E[E-] ... ??? ) [000015] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Checking Profile Weights (flags:0x16) No blocks were profiled, so nothing to check *************** Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Finishing PHASE Expand patchpoints [no changes] *************** Starting PHASE Indirect call transform *** FatPointerCall: transforming STMT00002 New Basic Block BB03 [0002] created. Setting edge weights for BB02 -> BB03 to [0 .. 3.402823e+38] setting likelihood of BB02 -> BB03 to 1 New Basic Block BB04 [0003] created. New Basic Block BB05 [0004] created. New Basic Block BB06 [0005] created. removing useless STMT00002 ( 0x013[E-] ... 0x02E ) [000011] --CXG------ * CALL ind void [000010] V-CXGO----- calli tgt \--* IND long [000009] --CXG------ \--* ADD byref [000007] H-CXG------ +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000008] ----------- \--* CNS_INT long 8 Fseq[FtnHolder] from BB02 Setting edge weights for BB02 -> BB04 to [0 .. 3.402823e+38] setting likelihood of BB02 -> BB04 to 1 Setting edge weights for BB04 -> BB05 to [0 .. 3.402823e+38] setting likelihood of BB04 -> BB05 to 0.5 Setting edge weights for BB04 -> BB06 to [0 .. 3.402823e+38] setting likelihood of BB04 -> BB06 to 0.5 Setting edge weights for BB05 -> BB03 to [0 .. 3.402823e+38] setting likelihood of BB05 -> BB03 to 1 Setting edge weights for BB06 -> BB03 to [0 .. 3.402823e+38] setting likelihood of BB06 -> BB03 to 1 -- 1 calls transformed *************** Finishing PHASE Indirect call transform Trees after Indirect call transform ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i internal q BB02 [0001] 1 BB01 1 [000..01F)-> BB04 (always) i q BB04 [0003] 1 BB02 1 [???..???)-> BB06,BB05 ( cond ) i internal q BB05 [0004] 1 BB04 0.80 [???..???)-> BB03 (always) i internal BB06 [0005] 1 BB04 0.20 [???..???)-> BB03 (always) i internal q BB03 [0002] 2 BB05,BB06 1 [01F..02F) (return) i internal ---------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [???..???) -> BB02 (always), preds={} succs={BB02} ***** BB01 [0000] STMT00000 ( ??? ... ??? ) [000000] ----------- * NOP void ------------ BB02 [0001] [000..01F) -> BB04 (always), preds={BB01} succs={BB04} ***** BB02 [0001] STMT00001 ( 0x000[E-] ... 0x00E ) [000006] VACXGO----- * STOREIND long [000005] --CXG------ +--* ADD byref [000003] H-CXG------ | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000004] ----------- | \--* CNS_INT long 8 Fseq[FtnHolder] [000002] --C-G------ \--* CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE [000001] !---------- arg0 \--* LCL_VAR long V00 TypeCtx ------------ BB04 [0003] [???..???) -> BB06,BB05 (cond), preds={BB02} succs={BB05,BB06} ***** BB04 [0003] STMT00005 ( 0x013[E-] ... ??? ) [000024] --CXGO----- * JTRUE void [000023] --CXGO----- \--* NE int [000021] --CXGO----- +--* AND long [000017] V-CXGO----- | +--* IND long [000018] --CXG------ | | \--* ADD byref [000019] H-CXG------ | | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000020] ----------- | | \--* CNS_INT long 8 Fseq[FtnHolder] [000016] ----------- | \--* CNS_INT long 2 [000022] ----------- \--* CNS_INT long 0 ------------ BB05 [0004] [???..???) -> BB03 (always), preds={BB04} succs={BB03} ***** BB05 [0004] STMT00006 ( 0x013[E-] ... ??? ) [000025] --CXG------ * CALL ind void [000026] V-CXGO----- calli tgt \--* IND long [000027] --CXG------ \--* ADD byref [000028] H-CXG------ +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000029] ----------- \--* CNS_INT long 8 Fseq[FtnHolder] ------------ BB06 [0005] [???..???) -> BB03 (always), preds={BB04} succs={BB03} ***** BB06 [0005] STMT00007 ( 0x013[E-] ... ??? ) [000046] --CXG------ * CALL ind void [000045] --CXGO----- gctx +--* IND long [000044] --CXGO----- | \--* ADD long [000037] --CXGO----- | +--* SUB long [000038] V-CXGO----- | | +--* IND long [000039] --CXG------ | | | \--* ADD byref [000040] H-CXG------ | | | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000041] ----------- | | | \--* CNS_INT long 8 Fseq[FtnHolder] [000042] ----------- | | \--* CNS_INT long 2 [000043] ----------- | \--* CNS_INT long 8 [000036] --CXGO----- calli tgt \--* IND long [000035] --CXGO----- \--* SUB long [000030] V-CXGO----- +--* IND long [000031] --CXG------ | \--* ADD byref [000032] H-CXG------ | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000033] ----------- | \--* CNS_INT long 8 Fseq[FtnHolder] [000034] ----------- \--* CNS_INT long 2 ------------ BB03 [0002] [01F..02F) (return), preds={BB05,BB06} succs={} ***** BB03 [0002] STMT00003 ( 0x01F[E-] ... ??? ) [000014] --C-G------ * CALL void Statics:CheckForFailure(System.String,System.String) [000012] ----------- arg0 +--* CNS_STR ref [000013] ----------- arg1 \--* CNS_STR ref ***** BB03 [0002] STMT00004 ( 0x02E[E-] ... ??? ) [000015] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Checking Profile Weights (flags:0x16) No blocks were profiled, so nothing to check *************** Starting PHASE Post-import *************** Finishing PHASE Post-import [no changes] *************** Starting PHASE Morph - Init New BlockSet epoch 1, # of blocks (including unused BB00): 7, bitset array size: 1 (short) *************** Finishing PHASE Morph - Init [no changes] *************** Starting PHASE Morph - Inlining *************** Finishing PHASE Morph - Inlining [no changes] *************** Starting PHASE Allocate Objects no newobjs in this method; punting *************** Finishing PHASE Allocate Objects [no changes] *************** Starting PHASE Morph - Add internal blocks *************** After fgAddInternal() ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i keep internal q BB02 [0001] 1 BB01 1 [000..01F)-> BB04 (always) i q BB04 [0003] 1 BB02 1 [???..???)-> BB06,BB05 ( cond ) i internal q BB05 [0004] 1 BB04 0.80 [???..???)-> BB03 (always) i internal BB06 [0005] 1 BB04 0.20 [???..???)-> BB03 (always) i internal q BB03 [0002] 2 BB05,BB06 1 [01F..02F) (return) i internal ---------------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Morph - Add internal blocks [no changes] *************** Starting PHASE Remove empty try *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try [no changes] *************** Starting PHASE Remove empty finally No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty finally [no changes] *************** Starting PHASE Merge callfinally chains No EH in this method, nothing to merge. *************** Finishing PHASE Merge callfinally chains [no changes] *************** Starting PHASE Clone finally No EH in this method, no cloning. *************** Finishing PHASE Clone finally [no changes] *************** Starting PHASE Morph - Promote Structs promotion opt flag not enabled *************** Finishing PHASE Morph - Promote Structs [no changes] *************** Starting PHASE Morph - Structs/AddrExp LocalAddressVisitor visiting statement: STMT00000 ( ??? ... ??? ) [000000] ----------- * NOP void LocalAddressVisitor visiting statement: STMT00001 ( 0x000[E-] ... 0x00E ) [000006] VACXGO----- * STOREIND long [000005] --CXG------ +--* ADD byref [000003] H-CXG------ | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000004] ----------- | \--* CNS_INT long 8 Fseq[FtnHolder] [000002] --C-G------ \--* CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE [000001] !---------- arg0 \--* LCL_VAR long V00 TypeCtx LocalAddressVisitor visiting statement: STMT00005 ( 0x013[E-] ... ??? ) [000024] --CXGO----- * JTRUE void [000023] --CXGO----- \--* NE int [000021] --CXGO----- +--* AND long [000017] V-CXGO----- | +--* IND long [000018] --CXG------ | | \--* ADD byref [000019] H-CXG------ | | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000020] ----------- | | \--* CNS_INT long 8 Fseq[FtnHolder] [000016] ----------- | \--* CNS_INT long 2 [000022] ----------- \--* CNS_INT long 0 LocalAddressVisitor visiting statement: STMT00006 ( 0x013[E-] ... ??? ) [000025] --CXG------ * CALL ind void [000026] V-CXGO----- calli tgt \--* IND long [000027] --CXG------ \--* ADD byref [000028] H-CXG------ +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000029] ----------- \--* CNS_INT long 8 Fseq[FtnHolder] LocalAddressVisitor visiting statement: STMT00007 ( 0x013[E-] ... ??? ) [000046] --CXG------ * CALL ind void [000045] --CXGO----- gctx +--* IND long [000044] --CXGO----- | \--* ADD long [000037] --CXGO----- | +--* SUB long [000038] V-CXGO----- | | +--* IND long [000039] --CXG------ | | | \--* ADD byref [000040] H-CXG------ | | | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000041] ----------- | | | \--* CNS_INT long 8 Fseq[FtnHolder] [000042] ----------- | | \--* CNS_INT long 2 [000043] ----------- | \--* CNS_INT long 8 [000036] --CXGO----- calli tgt \--* IND long [000035] --CXGO----- \--* SUB long [000030] V-CXGO----- +--* IND long [000031] --CXG------ | \--* ADD byref [000032] H-CXG------ | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000033] ----------- | \--* CNS_INT long 8 Fseq[FtnHolder] [000034] ----------- \--* CNS_INT long 2 LocalAddressVisitor visiting statement: STMT00003 ( 0x01F[E-] ... ??? ) [000014] --C-G------ * CALL void Statics:CheckForFailure(System.String,System.String) [000012] ----------- arg0 +--* CNS_STR ref [000013] ----------- arg1 \--* CNS_STR ref LocalAddressVisitor visiting statement: STMT00004 ( 0x02E[E-] ... ??? ) [000015] ----------- * RETURN void *************** Finishing PHASE Morph - Structs/AddrExp [no changes] *************** Starting PHASE Early liveness *************** Finishing PHASE Early liveness [no changes] *************** Starting PHASE Forward Substitution *************** Finishing PHASE Forward Substitution [no changes] *************** Starting PHASE Physical promotion *************** Finishing PHASE Physical promotion [no changes] *************** Starting PHASE Identify candidates for implicit byref copy omission *************** Finishing PHASE Identify candidates for implicit byref copy omission [no changes] *************** Starting PHASE Morph - ByRefs *************** Finishing PHASE Morph - ByRefs [no changes] *************** Starting PHASE Morph - Global compEnregLocals() is false, setting doNotEnreg flag for all locals. Local V00 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set Local V01 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set Morphing BB01 fgMorphTree BB01, STMT00000 (before) [000000] ----------- * NOP void Morphing BB02 fgMorphTree BB02, STMT00001 (before) [000006] VACXGO----- * STOREIND long [000005] --CXG------ +--* ADD byref [000003] H-CXG------ | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000004] ----------- | \--* CNS_INT long 8 Fseq[FtnHolder] [000002] --C-G------ \--* CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE [000001] !---------- arg0 \--* LCL_VAR long V00 TypeCtx Initializing arg info for 3.CALL: Args for call [000003] CALL after AddFinalArgsAndDetermineABIInfo: Morphing args for 3.CALL: Args for [000003].CALL after fgMorphArgs: OutgoingArgsStackSize is 32 Initializing arg info for 2.CALL: Args for call [000002] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[000001].LCL_VAR long (By value), 1 reg: rcx, byteAlignment=8] Morphing args for 2.CALL: Sorting the arguments: Deferred argument ('rcx'): [000001] !----+----- * LCL_VAR long V00 TypeCtx Moved to late list Register placement order: rcx Args for [000002].CALL after fgMorphArgs: CallArg[[000001].LCL_VAR long (By value), 1 reg: rcx, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 32 Morphing BB04 fgMorphTree BB04, STMT00005 (before) [000024] --CXGO----- * JTRUE void [000023] --CXGO----- \--* NE int [000021] --CXGO----- +--* AND long [000017] V-CXGO----- | +--* IND long [000018] --CXG------ | | \--* ADD byref [000019] H-CXG------ | | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000020] ----------- | | \--* CNS_INT long 8 Fseq[FtnHolder] [000016] ----------- | \--* CNS_INT long 2 [000022] ----------- \--* CNS_INT long 0 Initializing arg info for 19.CALL: Args for call [000019] CALL after AddFinalArgsAndDetermineABIInfo: Morphing args for 19.CALL: Args for [000019].CALL after fgMorphArgs: OutgoingArgsStackSize is 32 Morphing BB05 fgMorphTree BB05, STMT00006 (before) [000025] --CXG------ * CALL ind void [000026] V-CXGO----- calli tgt \--* IND long [000027] --CXG------ \--* ADD byref [000028] H-CXG------ +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000029] ----------- \--* CNS_INT long 8 Fseq[FtnHolder] Initializing arg info for 25.CALL: Args for call [000025] CALL after AddFinalArgsAndDetermineABIInfo: Morphing args for 25.CALL: Initializing arg info for 28.CALL: Args for call [000028] CALL after AddFinalArgsAndDetermineABIInfo: Morphing args for 28.CALL: Args for [000028].CALL after fgMorphArgs: OutgoingArgsStackSize is 32 Args for [000025].CALL after fgMorphArgs: OutgoingArgsStackSize is 32 Morphing BB06 fgMorphTree BB06, STMT00007 (before) [000046] --CXG------ * CALL ind void [000045] --CXGO----- gctx +--* IND long [000044] --CXGO----- | \--* ADD long [000037] --CXGO----- | +--* SUB long [000038] V-CXGO----- | | +--* IND long [000039] --CXG------ | | | \--* ADD byref [000040] H-CXG------ | | | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000041] ----------- | | | \--* CNS_INT long 8 Fseq[FtnHolder] [000042] ----------- | | \--* CNS_INT long 2 [000043] ----------- | \--* CNS_INT long 8 [000036] --CXGO----- calli tgt \--* IND long [000035] --CXGO----- \--* SUB long [000030] V-CXGO----- +--* IND long [000031] --CXG------ | \--* ADD byref [000032] H-CXG------ | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000033] ----------- | \--* CNS_INT long 8 Fseq[FtnHolder] [000034] ----------- \--* CNS_INT long 2 Initializing arg info for 46.CALL: Args for call [000046] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[000045].IND long (By value), 1 reg: rcx, byteAlignment=8, wellKnown[InstParam]] Morphing args for 46.CALL: Initializing arg info for 40.CALL: Args for call [000040] CALL after AddFinalArgsAndDetermineABIInfo: Morphing args for 40.CALL: Args for [000040].CALL after fgMorphArgs: OutgoingArgsStackSize is 32 Initializing arg info for 32.CALL: Args for call [000032] CALL after AddFinalArgsAndDetermineABIInfo: Morphing args for 32.CALL: Args for [000032].CALL after fgMorphArgs: OutgoingArgsStackSize is 32 Sorting the arguments: Deferred argument ('rcx'): [000045] --CXG+----- * IND long [000044] --CXG+----- \--* ADD long [000037] --CXG+----- +--* ADD long [000038] V-CXG+----- | +--* IND long [000039] --CXG+----- | | \--* ADD byref [000040] H-CXG+----- | | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000041] -----+----- | | \--* CNS_INT long 8 Fseq[FtnHolder] [000042] -----+----- | \--* CNS_INT long -2 [000043] -----+----- \--* CNS_INT long 8 Moved to late list Register placement order: rcx Args for [000046].CALL after fgMorphArgs: CallArg[[000045].IND long (By value), 1 reg: rcx, byteAlignment=8, isLate, processed, wellKnown[InstParam]] OutgoingArgsStackSize is 32 fgMorphTree BB06, STMT00007 (after) [000046] --CXG+----- * CALL ind void [000036] --CXG+----- calli tgt \--* IND long [000035] --CXG+----- \--* ADD long [000030] V-CXG+----- +--* IND long [000031] --CXG+----- | \--* ADD byref [000032] H-CXG+----- | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000033] -----+----- | \--* CNS_INT long 8 Fseq[FtnHolder] [000034] -----+----- \--* CNS_INT long -2 [000045] --CXG+----- gctx in rcx \--* IND long [000044] --CXG+----- \--* ADD long [000037] --CXG+----- +--* ADD long ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_GenericOverTypeParameterGenericValuetype_GenericOverString_NonGeneric_GenericMethodOverString[System.__Canon]()' during 'Generate code' (IL size 47; hash 0xd4f2af40; MinOpts) [000038] V-CXG+----- | +--* IND long [000039] --CXG+----- | | \--* ADD byref [000040] H-CXG+----- | | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000041] -----+----- | | \--* CNS_INT long 8 Fseq[FtnHolder] ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 [000042]ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericOverInt32_GenericOverObject_GenericMethodOverInt[System.__Canon]()' during 'Generate code' (IL size 47; hash 0x9547e707; MinOpts) --ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 ---ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_NonGenericNonGenericValuetype_GenericOverString_GenericOverObject_GenericMethodOverInt[System.__Canon]()' during 'Generate code' (IL size 47; hash 0x4893fb2d; MinOpts) +----- | \--* CNS_INT long -2 [000043] -----+----- \--* CNS_INT long 8 Morphing BB03 fgMorphTree BB03, STMT00003 (before) [000014] --C-G------ * CALL void Statics:CheckForFailure(System.String,System.String) [000012] ----------- arg0 +--* CNS_STR ref [000013] ----------- arg1 \--* CNS_STR ref Initializing arg info for 14.CALL: Args for call [000014] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[000012].CNS_STR ref (By value), 1 reg: rcx, byteAlignment=8] CallArg[[000013].CNS_STR ref (By value), 1 reg: rdx, byteAlignment=8] Morphing args for 14.CALL: Sorting the arguments: Deferred argument ('rcx'): [000051] H----+----- * CNS_INT(h) ref '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' Moved to late list Deferred argument ('rdx'): [000052] H----+----- * CNS_INT(h) ref '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' Moved to late list Register placement order: rcx rdx Args for [000014].CALL after fgMorphArgs: CallArg[[000051].CNS_INT ref (By value), 1 reg: rcx, byteAlignment=8, isLate, processed] CallArg[[000052].CNS_INT ref (By value), 1 reg: rdx, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 32 fgMorphTree BB03, STMT00003 (after) ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_GenericOverGenericStructOverTypeParameterGenericValuetype_GenericOverString_NonGeneric_GenericMethodOverTypeParameter[System.__Canon]()' during 'Generate code' (IL size 47; hash 0xd82f01cc; MinOpts) [000014] --CXG+----- * CALL void Statics:CheckForFailure(System.String,System.String) [000051] H----+----- arg0 in rcx +--* CNS_INT(h) ref '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' [000052] H----+----- arg1 in rdx \--* CNS_INT(h) ref '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' fgMorphTree BB03, STMT00004 (before) [000015] ----------- * RETURN void *************** Finishing PHASE Morph - Global Trees after Morph - Global ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i keep internal q BB02 [0001] 1 BB01 1 [000..01F)-> BB04 (always) i hascall q BB04 [0003] 1 BB02 1 [???..???)-> BB06,BB05 ( cond ) iILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_GenericOverTypeParameterGenericValuetype_GenericOverString_CuriouslyRecurringGeneric_GenericMethodOverInt[System.__Canon]()' during 'Generate code' (IL size 47; hash 0x51a8bed9; MinOpts) internal hascall q BB05 [0004] 1 BB04 0.80 [???..???)-> BB03 (always) i internal hascall gcsafe BB06 [0005] 1 BB04 0.20 [???..???)-> BB03 (always) i internal hascall gcsafe q BB03 [0002] 2 BB05,BB06 1 [01F..02F) (return) i internal hascall gcsafe ---------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [???..???) -> BB02 (always), preds={} succs={BB02} ***** BB01 [0000] STMT00000 ( ??? ... ??? ) [000000] -----+----- * NOP void ------------ BB02 [0001] [000..01F) -> BB04 (always), preds={BB01} succs={BB04} ***** BB02 [0001] STMT00001 ( 0x000[E-] ... 0x00E ) [000006] VACXG+----- * STOREIND long [000005] --CXG+----- +--* ADD byref [000003] H-CXG+----- | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000004] -----+----- | \--* CNS_INT long 8 Fseq[FtnHolder] [000002] --C-G+----- \--* CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE [000001] !----+----- arg0 in rcx \--* LCL_VAR long V00 TypeCtx ------------ BB04 [0003] [???..???) -> BB06,BB05 (cond), preds={BB02} succs={BB05,BB06} ***** BB04 [0003] STMT00005 ( 0x013[E-] ... ??? ) [000024] --CXG+----- * JTRUE void [000023] J-CXG+-N--- \--* NE int [000021] --CXG+----- +--* AND int [000017] V-CXG+----- | +--* IND int [000018] --CXG+----- | | \--* ADD byref [000019] H-CXG+----- | | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000020] -----+----- | | \--* CNS_INT long 8 Fseq[FtnHolder] [000016] -----+----- | \--* CNS_INT int 2 [000022] -----+----- \--* CNS_INT int 0 ------------ BB05 [0004] [???..???) -> BB03 (always), preds={BB04} succs={BB03} ***** BB05 [0004] STMT00006 ( 0x013[E-] ... ??? ) [000025] --CXG+----- * CALL ind void [000026] V-CXG+----- calli tgt \--* IND long [000027] --CXG+----- \--* ADD byref [000028] H-CXG+----- +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000029] -----+----- \--* CNS_INT long 8 Fseq[FtnHolder] ------------ BB06 [0005] [???..???) -> BB03 (always), preds={BB04} succs={BB03} ***** BB06 [0005] STMT00007 ( 0x013[E-] ... ??? ) [000046] --CXG+----- * CALL ind void [000036] --CXG+----- calli tgt \--* IND long [000035] --CXG+----- \--* ADD long [000030] V-CXG+----- +--* IND long [000031] --CXG+----- | \--* ADD byref [000032] H-CXG+----- | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000033] -----+----- | \--* CNS_INT long 8 Fseq[FtnHolder] [000034] -----+----- \--* CNS_INT long -2 [000045] --CXG+----- gctx in rcx \--* IND long [000044] --CXG+----- \--* ADD long [000037] --CXG+----- +--* ADD long [000038] V-CXG+----- | +--* IND long [000039] --CXG+----- | | \--* ADD byref [000040] H-CXG+----- | | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000041] -----+----- | | \--* CNS_INT long 8 Fseq[FtnHolder] [000042] -----+----- | \--* CNS_INT long -2 [000043] -----+----- \--* CNS_INT long 8 ------------ BB03 [0002] [01F..02F) (return), preds={BB05,BB06} succs={} ***** BB03 [0002] STMT00003 ( 0x01F[E-] ... ??? ) [000014] --CXG+----- * CALL void Statics:CheckForFailure(System.String,System.String) [000051] H----+----- arg0 in rcx +--* CNS_INT(h) ref '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' [000052] H----+----- arg1 in rdx \--* CNS_INT(h) ref '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' ***** BB03 [0002] STMT00004 ( 0x02E[E-] ... ??? ) [000015] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Checking Profile Weights (flags:0x16) No blocks were profiled, so nothing to check *************** Starting PHASE Post-Morph *************** In fgMarkDemotedImplicitByRefArgs() *************** Finishing PHASE Post-Morph Trees after Post-Morph ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i keep internal q BB02 [0001] 1 BB01 1 [000..01F)-> BB04 (always) i hascall q BB04 [0003] 1 BB02 1 [???..???)-> BB06,BB05 ( cond ) i internal hascall q BB05 [0004] 1 BB04 0.80 [???..???)-> BB03 (always) i internal hascall gcsafe BB06 [0005] 1 BB04 0.20 [???..???)-> BB03 (always) i internal hascall gcsafe q BB03 [0002] 2 BB05,BB06 1 [01F..02F) (return) i internal hascall gcsafe ---------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [???..???) -> BB02 (always), preds={} succs={BB02} ***** BB01 [0000] STMT00000 ( ??? ... ??? ) [000000] -----+----- * NOP void ------------ BB02 [0001] [000..01F) -> BB04 (always), preds={BB01} succs={BB04} ***** BB02 [0001] STMT00001 ( 0x000[E-] ... 0x00E ) [000006] VACXG+----- * STOREIND long [000005] --CXG+----- +--* ADD byref [000003] H-CXG+----- | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000004] -----+----- | \--* CNS_INT long 8 Fseq[FtnHolder] [000002] --C-G+----- \--* CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE [000001] !----+----- arg0 in rcx \--* LCL_VAR long V00 TypeCtx ------------ BB04 [0003] [???..???) -> BB06,BB05 (cond), preds={BB02} succs={BB05,BB06} ***** BB04 [0003] STMT00005 ( 0x013[E-] ... ??? ) [000024] --CXG+----- * JTRUE void [000023] J-CXG+-N--- \--* NE int [000021] --CXG+----- +--* AND int [000017] V-CXG+----- | +--* IND int [000018] --CXG+----- | | \--* ADD byref [000019] H-CXG+----- | | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000020] -----+----- | | \--* CNS_INT long 8 Fseq[FtnHolder] [000016] -----+----- | \--* CNS_INT int 2 [000022] -----+----- \--* CNS_INT int 0 ------------ BB05 [0004] [???..???) -> BB03 (always), preds={BB04} succs={BB03} ***** BB05 [0004] STMT00006 ( 0x013[E-] ... ??? ) [000025] --CXG+----- * CALL ind void [000026] V-CXG+----- calli tgt \--* IND long [000027] --CXG+----- \--* ADD byref [000028] H-CXG+----- +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000029] -----+----- \--* CNS_INT long 8 Fseq[FtnHolder] ------------ BB06 [0005] [???..???) -> BB03 (always), preds={BB04} succs={BB03} ***** BB06 [0005] STMT00007 ( 0x013[E-] ... ??? ) [000046] --CXG+----- * CALL ind void [000036] --CXG+----- calli tgt \--* IND long [000035] --CXG+----- \--* ADD long [000030] V-CXG+----- +--* IND long [000031] --CXG+----- | \--* ADD byref [000032] H-CXG+----- | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000033] -----+----- | \--* CNS_INT long 8 Fseq[FtnHolder] [000034] -----+----- \--* CNS_INT long -2 [000045] --CXG+----- gctx in rcx \--* IND long [000044] --CXG+----- \--* ADD long [000037] --CXG+----- +--* ADD long [000038] V-CXG+----- | +--* IND long [000039] --CXG+----- | | \--* ADD byref [000040] H-CXG+----- | | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE [000041] -----+----- | | \--* CNS_INT long 8 Fseq[FtnHolder] [000042] -----+----- | \--* CNS_INT long -2 [000043] -----+----- \--* CNS_INT long 8 ------------ BB03 [0002] [01F..02F) (return), preds={BB05,BB06} succs={} ***** BB03 [0002] STMT00003 ( 0x01F[E-] ... ??? ) [000014] --CXG+----- * CALL void Statics:CheckForFailure(System.String,System.String) [000051] H----+----- arg0 in rcx +--* CNS_INT(h) ref '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' [000052] H----+----- arg1 in rdx \--* CNS_INT(h) ref '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' ***** BB03 [0002] STMT00004 ( 0x02E[E-] ... ??? ) [000015] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Checking Profile Weights (flags:0x16) No blocks were profiled, so nothing to check *************** Starting PHASE GS Cookie No GS security needed *************** Finishing PHASE GS Cookie [no changes] *************** Starting PHASE Compute edge weights (1, false) ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i keep internal q BB02 [0001] 1 BB01 1 [000..01F)-> BB04 (always) i hascall q BB04 [0003] 1 BB02 1 [???..???)-> BB06,BB05 ( cond ) i internal hascall q BB05 [0004] 1 BB04 0.80 [???..???)-> BB03 (always) i internal hascall gcsafe BB06 [0005] 1 BB04 0.20 [???..???)-> BB03 (always) i internal hascall gcsafe q BB03 [0002] 2 BB05,BB06 1 [01F..02F) (return) i internal hascall gcsafe ---------------------------------------------------------------------------------------------------------------------------------------------- -- no profile data, so using default called count -- not optimizing or no profile data, so not computing edge weights *************** Finishing PHASE Compute edge weights (1, false) [no changes] *************** Starting PHASE Create EH funclets *************** Finishing PHASE Create EH funclets [no changes] *************** Starting PHASE Morph array ops No multi-dimensional array references in the function *************** Finishing PHASE Morph array ops [no changes] *************** Starting PHASE Mark local vars *************** In lvaMarkLocalVars() *** lvaComputeRefCounts *** *************** Finishing PHASE Mark local vars [no changes] *************** Starting PHASE Find oper order *************** In fgFindOperOrder() *************** Finishing PHASE Find oper order Trees after Find oper order ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i keep internal q BB02 [0001] 1 BB01 1 [000..01F)-> BB04 (always) i hascall q BB04 [0003] 1 BB02 1 [???..???)-> BB06,BB05 ( cond ) i internal hascall q BB05 [0004] 1 BB04 0.80 [???..???)-> BB03 (always) i internal hascall gcsafe BB06 [0005] 1 BB04 0.20 [???..???)-> BB03 (always) i internal hascall gcsafe q BB03 [0002] 2 BB05,BB06 1 [01F..02F) (return) i internal hascall gcsafe ---------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [???..???) -> BB02 (always), preds={} succs={BB02} ***** BB01 [0000] STMT00000 ( ??? ... ??? ) ( 0, 0) [000000] ----------- * NOP void ------------ BB02 [0001] [000..01F) -> BB04 (always), preds={BB01} succs={BB04} ***** BB02 [0001] STMT00001 ( 0x000[E-] ... 0x00E ) ( 35, 17) [000006] VACXGO----- * STOREIND long ( 15, 6) [000005] --CXG--N--- +--* ADD byref ( 14, 5) [000003] H-CXG------ | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ( 1, 1) [000004] ----------- | \--* CNS_INT long 8 Fseq[FtnHolder] ( 17, 8) [000002] --C-G------ \--* CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE ( 3, 2) [000001] !---------- arg0 in rcx \--* LCL_VAR long V00 TypeCtx ------------ BB04 [0003] [???..???) -> BB06,BB05 (cond), preds={BB02} succs={BB05,BB06} ***** BB04 [0003] STMT00005 ( 0x013[E-] ... ??? ) ( 23, 14) [000024] --CXGO----- * JTRUE void ( 21, 12) [000023] J-CXGO-N--- \--* NE int ( 19, 10) [000021] --CXGO----- +--* AND int ( 17, 8) [000017] V-CXGO----- | +--* IND int ( 15, 6) [000018] --CXG--N--- | | \--* ADD byref ( 14, 5) [000019] H-CXG------ | | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ( 1, 1) [000020] ----------- | | \--* CNS_INT long 8 Fseq[FtnHolder] ( 1, 1) [000016] ----------- | \--* CNS_INT int 2 ( 1, 1) [000022] ----------- \--* CNS_INT int 0 ------------ BB05 [0004] [???..???) -> BB03 (always), preds={BB04} succs={BB03} ***** BB05 [0004] STMT00006 ( 0x013[E-] ... ??? ) ( 34, 10) [000025] --CXGO----- * CALL ind void ( 17, 8) [000026] V-CXGO----- calli tgt \--* IND long ( 15, 6) [000027] --CXG--N--- \--* ADD byref ( 14, 5) [000028] H-CXG------ +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ( 1, 1) [000029] ----------- \--* CNS_INT long 8 Fseq[FtnHolder] ------------ BB06 [0005] [???..???) -> BB03 (always), preds={BB04} succs={BB03} ***** BB06 [0005] STMT00007 ( 0x013[E-] ... ??? ) ( 57, 25) [000046] --CXGO----- * CALL ind void ( 20, 11) [000036] --CXGO----- calli tgt \--* IND long ( 18, 9) [000035] --CXGO-N--- \--* ADD long ( 17, 8) [000030] V-CXGO----- +--* IND long ( 15, 6) [000031] --CXG--N--- | \--* ADD byref ( 14, 5) [000032] H-CXG------ | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ( 1, 1) [000033] ----------- | \--* CNS_INT long 8 Fseq[FtnHolder] ( 1, 1) [000034] ----------- \--* CNS_INT long -2 ( 20, 11) [000045] --CXGO----- gctx in rcx \--* IND long ( 20, 11) [000044] --CXGO-N--- \--* ADD long ( 19, 10) [000037] --CXGO-N--- +--* ADD long ( 17, 8) [000038] V-CXGO----- | +--* IND long ( 15, 6) [000039] --CXG--N--- | | \--* ADD byref ( 14, 5) [000040] H-CXG------ | | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ( 1, 1) [000041] ----------- | | \--* CNS_INT long 8 Fseq[FtnHolder] ( 1, 1) [000042] ----------- | \--* CNS_INT long -2 ( 1, 1) [000043] ----------- \--* CNS_INT long 8 ------------ BB03 [0002] [01F..02F) (return), preds={BB05,BB06} succs={} ***** BB03 [0002] STMT00003 ( 0x01F[E-] ... ??? ) ( 16, 15) [000014] --CXG------ * CALL void Statics:CheckForFailure(System.String,System.String) ( 1, 4) [000051] H---------- arg0 in rcx +--* CNS_INT(h) ref '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' ( 1, 4) [000052] H---------- arg1 in rdx \--* CNS_INT(h) ref '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' ***** BB03 [0002] STMT00004 ( 0x02E[E-] ... ??? ) ( 0, 0) [000015] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Checking Profile Weights (flags:0x16) No blocks were profiled, so nothing to check *************** Starting PHASE Set block order *************** In fgSetBlockOrder() The biggest BB has 17 tree nodes *************** Finishing PHASE Set block order Trees after Set block order ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i keep internal q BB02 [0001] 1 BB01 1 [000..01F)-> BB04 (always) i hascall q BB04 [0003] 1 BB02 1 [???..???)-> BB06,BB05 ( cond ) i internal hascall q BB05 [0004] 1 BB04 0.80 [???..???)-> BB03 (always) i internal hascall gcsafe BB06 [0005] 1 BB04 0.20 [???..???)-> BB03 (always) i internal hascall gcsafe q BB03 [0002] 2 BB05,BB06 1 [01F..02F) (return) i internal hascall gcsafe ---------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [???..???) -> BB02 (always), preds={} succs={BB02} ***** BB01 [0000] STMT00000 ( ??? ... ??? ) N001 ( 0, 0) [000000] ----------- * NOP void ------------ BB02 [0001] [000..01F) -> BB04 (always), preds={BB01} succs={BB04} ***** BB02 [0001] STMT00001 ( 0x000[E-] ... 0x00E ) N006 ( 35, 17) [000006] VACXGO----- * STOREIND long N003 ( 15, 6) [000005] --CXG--N--- +--* ADD byref N001 ( 14, 5) [000003] H-CXG------ | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE N002 ( 1, 1) [000004] ----------- | \--* CNS_INT long 8 Fseq[FtnHolder] N005 ( 17, 8) [000002] --C-G------ \--* CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE N004 ( 3, 2) [000001] !---------- arg0 in rcx \--* LCL_VAR long V00 TypeCtx ------------ BB04 [0003] [???..???) -> BB06,BB05 (cond), preds={BB02} succs={BB05,BB06} ***** BB04 [0003] STMT00005 ( 0x013[E-] ... ??? ) N009 ( 23, 14) [000024] --CXGO----- * JTRUE void N008 ( 21, 12) [000023] J-CXGO-N--- \--* NE int N006 ( 19, 10) [000021] --CXGO----- +--* AND int N004 ( 17, 8) [000017] V-CXGO----- | +--* IND int N003 ( 15, 6) [000018] --CXG--N--- | | \--* ADD byref N001 ( 14, 5) [000019] H-CXG------ | | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE N002 ( 1, 1) [000020] ----------- | | \--* CNS_INT long 8 Fseq[FtnHolder] N005 ( 1, 1) [000016] ----------- | \--* CNS_INT int 2 N007 ( 1, 1) [000022] ----------- \--* CNS_INT int 0 ------------ BB05 [0004] [???..???) -> BB03 (always), preds={BB04} succs={BB03} ***** BB05 [0004] STMT00006 ( 0x013[E-] ... ??? ) N005 ( 34, 10) [000025] --CXGO----- * CALL ind void N004 ( 17, 8) [000026] V-CXGO----- calli tgt \--* IND long N003 ( 15, 6) [000027] --CXG--N--- \--* ADD byref N001 ( 14, 5) [000028] H-CXG------ +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE N002 ( 1, 1) [000029] ----------- \--* CNS_INT long 8 Fseq[FtnHolder] ------------ BB06 [0005] [???..???) -> BB03 (always), preds={BB04} succs={BB03} ***** BB06 [0005] STMT00007 ( 0x013[E-] ... ??? ) N017 ( 57, 25) [000046] --CXGO----- * CALL ind void N016 ( 20, 11) [000036] --CXGO----- calli tgt \--* IND long N015 ( 18, 9) [000035] --CXGO-N--- \--* ADD long N013 ( 17, 8) [000030] V-CXGO----- +--* IND long N012 ( 15, 6) [000031] --CXG--N--- | \--* ADD byref N010 ( 14, 5) [000032] H-CXG------ | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE N011 ( 1, 1) [000033] ----------- | \--* CNS_INT long 8 Fseq[FtnHolder] N014 ( 1, 1) [000034] ----------- \--* CNS_INT long -2 N009 ( 20, 11) [000045] --CXGO----- gctx in rcx \--* IND long N008 ( 20, 11) [000044] --CXGO-N--- \--* ADD long N006 ( 19, 10) [000037] --CXGO-N--- +--* ADD long N004 ( 17, 8) [000038] V-CXGO----- | +--* IND long N003 ( 15, 6) [000039] --CXG--N--- | | \--* ADD byref N001 ( 14, 5) [000040] H-CXG------ | | +--* CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE N002 ( 1, 1) [000041] ----------- | | \--* CNS_INT long 8 Fseq[FtnHolder] N005 ( 1, 1) [000042] ----------- | \--* CNS_INT long -2 N007 ( 1, 1) [000043] ----------- \--* CNS_INT long 8 ------------ BB03 [0002] [01F..02F) (return), preds={BB05,BB06} succs={} ***** BB03 [0002] STMT00003 ( 0x01F[E-] ... ??? ) N003 ( 16, 15) [000014] --CXG------ * CALL void Statics:CheckForFailure(System.String,System.String) N001 ( 1, 4) [000051] H---------- arg0 in rcx +--* CNS_INT(h) ref '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' N002 ( 1, 4) [000052] H---------- arg1 in rdx \--* CNS_INT(h) ref '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' ***** BB03 [0002] STMT00004 ( 0x02E[E-] ... ??? ) N001 ( 0, 0) [000015] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Checking Profile Weights (flags:0x16) No blocks were profiled, so nothing to check *************** Starting PHASE Stress gtSplitTree *************** Finishing PHASE Stress gtSplitTree [no changes] *************** Starting PHASE Expand casts *************** Finishing PHASE Expand casts [no changes] *************** Starting PHASE Expand runtime lookups *************** Finishing PHASE Expand runtime lookups [no changes] *************** Starting PHASE Expand static init Expanding static initialization for 'Statics', call: [000003] in BB02 New Basic Block BB07 [0006] created. BB04 previous predecessor was BB02, now is BB07 Setting edge weights for BB02 -> BB07 to [0 .. 3.402823e+38] setting likelihood of BB07 -> BB04 to 1 setting likelihood of BB02 -> BB07 to 1 lvaGrabTemp returning 2 (V02 tmp1) called for fgMakeTemp is creating a new local variable. New Basic Block BB08 [0007] created. New Basic Block BB09 [0008] created. Setting edge weights for BB09 -> BB07 to [0 .. 3.402823e+38] setting likelihood of BB09 -> BB07 to 1 Setting edge weights for BB08 -> BB07 to [0 .. 3.402823e+38] Setting edge weights for BB08 -> BB09 to [0 .. 3.402823e+38] setting likelihood of BB08 -> BB07 to 1 setting likelihood of BB08 -> BB09 to 0 Compacting BB08 into BB02: *************** In fgDebugCheckBBlist Expanding static initialization for 'Statics', call: [000019] in BB04 New Basic Block BB10 [0009] created. BB05 previous predecessor was BB04, now is BB10 BB06 previous predecessor was BB04, now is BB10 Setting edge weights for BB04 -> BB10 to [0 .. 3.402823e+38] setting likelihood of BB04 -> BB10 to 1 lvaGrabTemp returning 3 (V03 tmp2) called for fgMakeTemp is creating a new local variable. New Basic Block BB11 [0010] created. New Basic Block BB12 [0011] created. Setting edge weights for BB12 -> BB10 to [0 .. 3.402823e+38] setting likelihood of BB12 -> BB10 to 1 Setting edge weights for BB11 -> BB10 to [0 .. 3.402823e+38] Setting edge weights for BB11 -> BB12 to [0 .. 3.402823e+38] setting likelihood of BB11 -> BB10 to 1 setting likelihood of BB11 -> BB12 to 0 Compacting BB11 into BB04: *************** In fgDebugCheckBBlist Expanding static initialization for 'Statics', call: [000028] in BB05 New Basic Block BB13 [0012] created. BB03 previous predecessor was BB05, now is BB13 Setting edge weights for BB05 -> BB13 to [0 .. 3.402823e+38] setting likelihood of BB13 -> BB03 to 1 setting likelihood of BB05 -> BB13 to 1 lvaGrabTemp returning 4 (V04 tmp3) called for fgMakeTemp is creating a new local variable. New Basic Block BB14 [0013] created. New Basic Block BB15 [0014] created. Setting edge weights for BB15 -> BB13 to [0 .. 3.402823e+38] setting likelihood of BB15 -> BB13 to 1 Setting edge weights for BB14 -> BB13 to [0 .. 3.402823e+38] Setting edge weights for BB14 -> BB15 to [0 .. 3.402823e+38] setting likelihood of BB14 -> BB13 to 1 setting likelihood of BB14 -> BB15 to 0 Compacting BB14 into BB05: *************** In fgDebugCheckBBlist Expanding static initialization for 'Statics', call: [000040] in BB06 New Basic Block BB16 [0015] created. BB03 previous predecessor was BB06, now is BB16 Setting edge weights for BB06 -> BB16 to [0 .. 3.402823e+38] setting likelihood of BB16 -> BB03 to 1 setting likelihood of BB06 -> BB16 to 1 lvaGrabTemp returning 5 (V05 tmp4) called for fgMakeTemp is creating a new local variable. New Basic Block BB17 [0016] created. New Basic Block BB18 [0017] created. ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 Setting edge weights for BB18 -> BB16 to [0 .. 3.402823e+38] ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_NonGenericNonGenericValuetype_GenericOverConstrainedType_CuriouslyRecurringGeneric_GenericMethodOverTypeParameter[System.__Canon,System.__Canon]()' during 'Generate codesetting likelihood of BB18 -> BB16 to 1 Setting edge weights for BB17 -> BB16 to [0 .. 3.402823e+38] ' (IL size 47; hash 0x927f6c73; MinOpts) Setting edge weights for BB17 -> BB18 to [0 .. 3.402823e+38] setting likelihood of BB17 -> BB16 to 1 setting likelihood of BB17 -> BB18 to 0 Compacting BB17 into BB06: *************** In fgDebugCheckBBlist Expanding static initialization for 'Statics', call: [000032] in BB16 lvaGrabTemp returning 6 (V06 tmp5) called for Spilling to split statement for tree. Splitting BB16 after statement STMT00016 New Basic Block BB19 [0018] created. BB03 previous predecessor was BB16, now is BB19 Setting edge weights for BB16 -> BB19 to [0 .. 3.402823e+38] setting likelihood of BB19 -> BB03 to 1 setting likelihood of BB16 -> BB19 to 1 lvaGrabTemp returning 7 (V07 tmp6) called for fgMakeTemp is creating a new local variable. New Basic Block BB20 [0019] created. New Basic Block BB21 [0020] created. Setting edge weights for BB21 -> BB19 to [0 .. 3.402823e+38] setting likelihood of BB21 -> BB19 to 1 Setting edge weights for BB20 -> BB19 to [0 .. 3.402823e+38] Setting edge weights for BB20 -> BB21 to [0 .. 3.402823e+38] setting likelihood of BB20 -> BB19 to 1 setting likelihood of BB20 -> BB21 to 0 Compacting BB20 into BB16: *************** In fgDebugCheckBBlist *************** Finishing PHASE Expand static init Trees after Expand static init ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i keep internal q BB02 [0001] 1 BB01 1 [???..???)-> BB07,BB09 ( cond ) i hascall BB09 [0008] 1 BB02 0 [???..???)-> BB07 (always) rare internal q BB07 [0006] 2 BB02,BB09 1 [000..01F)-> BB04 (always) i hascall q BB04 [0003] 1 BB07 1 [???..???)-> BB10,BB12 ( cond ) i internal hascall BB12 [0011] 1 BB04 0 [???..???)-> BB10 (always) rare internal q BB10 [0009] 2 BB04,BB12 1 [???..???)-> BB06,BB05 ( cond ) i internal hascall q BB05 [0004] 1 BB10 0.80 [???..???)-> BB13,BB15 ( cond ) i internal hascall gcsafe BB15 [0014] 1 BB05 0 [???..???)-> BB13 (always) rare internal q BB13 [0012] 2 BB05,BB15 0.80 [???..???)-> BB03 (always) i internal hascall gcsafe BB06 [0005] 1 BB10 0.20 [???..???)-> BB16,BB18 ( cond ) i internal hascall gcsafe BB18 [0017] 1 BB06 0 [???..???)-> BB16 (always) rare internal q BB16 [0015] 2 BB06,BB18 0.20 [???..???)-> BB19,BB21 ( cond ) i internal hascall gcsafe BB21 [0020] 1 BB16 0 [???..???)-> BB19 (always) rare internal q BB19 [0018] 2 BB16,BB21 0.20 [013..???)-> BB03 (always) i internal hascall gcsafe q BB03 [0002] 2 BB13,BB19 1 [01F..02F) (return) i internal hascall gcsafe ---------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [???..???) -> BB02 (always), preds={} succs={BB02} ***** BB01 [0000] STMT00000 ( ??? ... ??? ) N001 ( 0, 0) [000000] ----------- * NOP void ------------ BB02 [0001] [???..???) -> BB07,BB09 (cond), preds={BB01} succs={BB09,BB07} ***** BB02 [0001] STMT00008 ( 0x000[E-] ... ??? ) N010 ( 15, 16) [000063] -A--G------ * JTRUE void N009 ( 13, 14) [000062] JA--G------ \--* EQ int N007 ( 11, 12) [000060] nA--G------ +--* IND long N006 ( 9, 10) [000059] -A-----N--- | \--* ADD long N004 ( 8, 9) [000056] -A--------- | +--* COMMA long N002 ( 5, 7) [000054] DA--------- | | +--* STORE_LCL_VAR long V02 tmp1 N001 ( 1, 4) [000053] H---------- | | | \--* CNS_INT(h) long 0x4000000000420458 global ptr N003 ( 3, 2) [000055] ----------- | | \--* LCL_VAR long V02 tmp1 N005 ( 1, 1) [000058] ----------- | \--* CNS_INT int -8 N008 ( 1, 1) [000061] ----------- \--* CNS_INT long 0 ------------ BB09 [0008] [???..???) -> BB07 (always), preds={BB02} succs={BB07} ***** BB09 [0008] STMT00009 ( 0x000[E-] ... ??? ) N001 ( 14, 5) [000003] H-CXG------ * CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB07 [0006] [000..01F) -> BB04 (always), preds={BB02,BB09} succs={BB04} ***** BB07 [0006] STMT00001 ( 0x000[E-] ... 0x00E ) N006 ( 24, 14) [000006] VAC-GO----- * STOREIND long N003 ( 4, 3) [000005] ----G--N--- +--* ADD byref N001 ( 3, 2) [000057] ----------- | +--* LCL_VAR long V02 tmp1 N002 ( 1, 1) [000004] ----------- | \--* CNS_INT long 8 Fseq[FtnHolder] N005 ( 17, 8) [000002] --C-G------ \--* CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE N004 ( 3, 2) [000001] !---------- arg0 in rcx \--* LCL_VAR long V00 TypeCtx ------------ BB04 [0003] [???..???) -> BB10,BB12 (cond), preds={BB07} succs={BB12,BB10} ***** BB04 [0003] STMT00010 ( 0x013[E-] ... ??? ) N010 ( 15, 16) [000074] -A--G------ * JTRUE void N009 ( 13, 14) [000073] JA--G------ \--* EQ int N007 ( 11, 12) [000071] nA--G------ +--* IND long N006 ( 9, 10) [000070] -A-----N--- | \--* ADD long N004 ( 8, 9) [000067] -A--------- | +--* COMMA long N002 ( 5, 7) [000065] DA--------- | | +--* STORE_LCL_VAR long V03 tmp2 N001 ( 1, 4) [000064] H---------- | | | \--* CNS_INT(h) long 0x4000000000420458 global ptr N003 ( 3, 2) [000066] ----------- | | \--* LCL_VAR long V03 tmp2 N005 ( 1, 1) [000069] ----------- | \--* CNS_INT int -8 N008 ( 1, 1) [000072] ----------- \--* CNS_INT long 0 ------------ BB12 [0011] [???..???) -> BB10 (always), preds={BB04} succs={BB10} ***** BB12 [0011] STMT00011 ( 0x013[E-] ... ??? ) N001 ( 14, 5) [000019] H-CXG------ * CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB10 [0009] [???..???) -> BB06,BB05 (cond), preds={BB04,BB12} succs={BB05,BB06} ***** BB10 [0009] STMT00005 ( 0x013[E-] ... ??? ) N009 ( 12, 11) [000024] ----GO----- * JTRUE void N008 ( 10, 9) [000023] J---GO-N--- \--* NE int N006 ( 8, 7) [000021] ----GO----- +--* AND int N004 ( 6, 5) [000017] V---GO----- | +--* IND int N003 ( 4, 3) [000018] ----G--N--- | | \--* ADD byref N001 ( 3, 2) [000068] ----------- | | +--* LCL_VAR long V03 tmp2 N002 ( 1, 1) [000020] ----------- | | \--* CNS_INT long 8 Fseq[FtnHolder] N005 ( 1, 1) [000016] ----------- | \--* CNS_INT int 2 N007 ( 1, 1) [000022] ----------- \--* CNS_INT int 0 ------------ BB05 [0004] [???..???) -> BB13,BB15 (cond), preds={BB10} succs={BB15,BB13} ***** BB05 [0004] STMT00012 ( 0x013[E-] ... ??? ) N010 ( 15, 16) [000085] -A--G------ * JTRUE void N009 ( 13, 14) [000084] JA--G------ \--* EQ int N007 ( 11, 12) [000082] nA--G------ +--* IND long N006 ( 9, 10) [000081] -A-----N--- | \--* ADD long N004 ( 8, 9) [000078] -A--------- | +--* COMMA long N002 ( 5, 7) [000076] DA--------- | | +--* STORE_LCL_VAR long V04 tmp3 N001 ( 1, 4) [000075] H---------- | | | \--* CNS_INT(h) long 0x4000000000420458 global ptr N003 ( 3, 2) [000077] ----------- | | \--* LCL_VAR long V04 tmp3 N005 ( 1, 1) [000080] ----------- | \--* CNS_INT int -8 N008 ( 1, 1) [000083] ----------- \--* CNS_INT long 0 ------------ BB15 [0014] [???..???) -> BB13 (always), preds={BB05} succs={BB13} ***** BB15 [0014] STMT00013 ( 0x013[E-] ... ??? ) N001 ( 14, 5) [000028] H-CXG------ * CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB13 [0012] [???..???) -> BB03 (always), preds={BB05,BB15} succs={BB03} ***** BB13 [0012] STMT00006 ( 0x013[E-] ... ??? ) N005 ( 23, 7) [000025] --CXGO----- * CALL ind void N004 ( 6, 5) [000026] V---GO----- calli tgt \--* IND long N003 ( 4, 3) [000027] ----G--N--- \--* ADD byref N001 ( 3, 2) [000079] ----------- +--* LCL_VAR long V04 tmp3 N002 ( 1, 1) [000029] ----------- \--* CNS_INT long 8 Fseq[FtnHolder] ------------ BB06 [0005] [???..???) -> BB16,BB18 (cond), preds={BB10} succs={BB18,BB16} ***** BB06 [0005] STMT00014 ( 0x013[E-] ... ??? ) N010 ( 15, 16) [000096] -A--G------ * JTRUE void N009 ( 13, 14) [000095] JA--G------ \--* EQ int N007 ( 11, 12) [000093] nA--G------ +--* IND long N006 ( 9, 10) [000092] -A-----N--- | \--* ADD long N004 ( 8, 9) [000089] -A--------- | +--* COMMA long N002 ( 5, 7) [000087] DA--------- | | +--* STORE_LCL_VAR long V05 tmp4 N001 ( 1, 4) [000086] H---------- | | | \--* CNS_INT(h) long 0x4000000000420458 global ptr N003 ( 3, 2) [000088] ----------- | | \--* LCL_VAR long V05 tmp4 N005 ( 1, 1) [000091] ----------- | \--* CNS_INT int -8 N008 ( 1, 1) [000094] ----------- \--* CNS_INT long 0 ------------ BB18 [0017] [???..???) -> BB16 (always), preds={BB06} succs={BB16} ***** BB18 [0017] STMT00015 ( 0x013[E-] ... ??? ) N001 ( 14, 5) [000040] H-CXG------ * CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB16 [0015] [???..???) -> BB19,BB21 (cond), preds={BB06,BB18} succs={BB21,BB19} ***** BB16 [0015] STMT00016 ( 0x013[E-] ... ??? ) N010 ( 13, 11) [000097] DA-XGO----- * STORE_LCL_VAR long V06 tmp5 N009 ( 9, 8) [000045] ---XGO----- \--* IND long N008 ( 9, 8) [000044] ----GO-N--- \--* ADD long N006 ( 8, 7) [000037] ----GO-N--- +--* ADD long N004 ( 6, 5) [000038] V---GO----- | +--* IND long N003 ( 4, 3) [000039] ----G--N--- | | \--* ADD byref N001 ( 3, 2) [000090] ----------- | | +--* LCL_VAR long V05 tmp4 N002 ( 1, 1) [000041] ----------- | | \--* CNS_INT long 8 Fseq[FtnHolder] N005 ( 1, 1) [000042] ----------- | \--* CNS_INT long -2 N007 ( 1, 1) [000043] ----------- \--* CNS_INT long 8 ***** BB16 [0015] STMT00017 ( 0x013[E-] ... ??? ) N010 ( 15, 16) [000109] -A--G------ * JTRUE void N009 ( 13, 14) [000108] JA--G------ \--* EQ int N007 ( 11, 12) [000106] nA--G------ +--* IND long N006 ( 9, 10) [000105] -A-----N--- | \--* ADD long N004 ( 8, 9) [000102] -A--------- | +--* COMMA long N002 ( 5, 7) [000100] DA--------- | | +--* STORE_LCL_VAR long V07 tmp6 N001 ( 1, 4) [000099] H---------- | | | \--* CNS_INT(h) long 0x4000000000420458 global ptr N003 ( 3, 2) [000101] ----------- | | \--* LCL_VAR long V07 tmp6 N005 ( 1, 1) [000104] ----------- | \--* CNS_INT int -8 N008 ( 1, 1) [000107] ----------- \--* CNS_INT long 0 ------------ BB21 [0020] [???..???) -> BB19 (always), preds={BB16} succs={BB19} ***** BB21 [0020] STMT00018 ( 0x013[E-] ... ??? ) N001 ( 14, 5) [000032] H-CXG------ * CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB19 [0018] [013..???) -> BB03 (always), preds={BB16,BB21} succs={BB03} ***** BB19 [0018] STMT00007 ( 0x013[E-] ... ??? ) N009 ( 29, 13) [000046] --CXGO----- * CALL ind void N008 ( 9, 8) [000036] ---XGO----- calli tgt \--* IND long N007 ( 7, 6) [000035] ----GO-N--- \--* ADD long N005 ( 6, 5) [000030] V---GO----- +--* IND long N004 ( 4, 3) [000031] ----G--N--- | \--* ADD byref N002 ( 3, 2) [000103] ----------- | +--* LCL_VAR long V07 tmp6 N003 ( 1, 1) [000033] ----------- | \--* CNS_INT long 8 Fseq[FtnHolder] N006 ( 1, 1) [000034] ----------- \--* CNS_INT long -2 N001 ( 3, 2) [000098] ----------- gctx in rcx \--* LCL_VAR long V06 tmp5 ------------ BB03 [0002] [01F..02F) (return), preds={BB13,BB19} succs={} ***** BB03 [0002] STMT00003 ( 0x01F[E-] ... ??? ) N003 ( 16, 15) [000014] --CXG------ * CALL void Statics:CheckForFailure(System.String,System.String) N001 ( 1, 4) [000051] H---------- arg0 in rcx +--* CNS_INT(h) ref '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' N002 ( 1, 4) [000052] H---------- arg1 in rdx \--* CNS_INT(h) ref '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' ***** BB03 [0002] STMT00004 ( 0x02E[E-] ... ??? ) N001 ( 0, 0) [000015] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Checking Profile Weights (flags:0x16) No blocks were profiled, so nothing to check *************** Starting PHASE Expand TLS access Nothing to expand. *************** Finishing PHASE Expand TLS access [no changes] *************** Starting PHASE Insert GC Polls *************** Finishing PHASE Insert GC Polls [no changes] *************** Starting PHASE Create throw helper blocks *************** Finishing PHASE Create throw helper blocks [no changes] *************** Starting PHASE Determine first cold block No procedure splitting will be done for this method *************** Finishing PHASE Determine first cold block [no changes] *************** Starting PHASE Rationalize IR *************** Finishing PHASE Rationalize IR Trees after Rationalize IR ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i LIR keep internal q BB02 [0001] 1 BB01 1 [???..???)-> BB07,BB09 ( cond ) i LIR hascall BB09 [0008] 1 BB02 0 [???..???)-> BB07 (always) LIR rare internal q BB07 [0006] 2 BB02,BB09 1 [000..01F)-> BB04 (always) i LIR hascall q BB04 [0003] 1 BB07 1 [???..???)-> BB10,BB12 ( cond ) i LIR internal hascall BB12 [0011] 1 BB04 0 [???..???)-> BB10 (always) LIR rare internal q BB10 [0009] 2 BB04,BB12 1 [???..???)-> BB06,BB05 ( cond ) i LIR internal hascall q BB05 [0004] 1 BB10 0.80 [???..???)-> BB13,BB15 ( cond ) i LIR internal hascall gcsafe BB15 [0014] 1 BB05 0 [???..???)-> BB13 (always) LIR rare internal q BB13 [0012] 2 BB05,BB15 0.80 [???..???)-> BB03 (always) i LIR internal hascall gcsafe BB06 [0005] 1 BB10 0.20 [???..???)-> BB16,BB18 ( cond ) i LIR internal hascall gcsafe BB18 [0017] 1 BB06 0 [???..???)-> BB16 (always) LIR rare internal q BB16 [0015] 2 BB06,BB18 0.20 [???..???)-> BB19,BB21 ( cond ) i LIR internal hascall gcsafe BB21 [0020] 1 BB16 0 [???..???)-> BB19 (always) LIR rare internal q BB19 [0018] 2 BB16,BB21 0.20 [013..???)-> BB03 (always) i LIR internal hascall gcsafe q BB03 [0002] 2 BB13,BB19 1 [01F..02F) (return) i LIR internal hascall gcsafe ---------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [???..???) -> BB02 (always), preds={} succs={BB02} N001 ( 0, 0) [000000] ----------- NOP void ------------ BB02 [0001] [???..???) -> BB07,BB09 (cond), preds={BB01} succs={BB09,BB07} [000110] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 1, 4) [000053] H---------- t53 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t53 long N002 ( 5, 7) [000054] DA--------- * STORE_LCL_VAR long V02 tmp1 N003 ( 3, 2) [000055] ----------- t55 = LCL_VAR long V02 tmp1 N005 ( 1, 1) [000058] ----------- t58 = CNS_INT int -8 /--* t55 long +--* t58 int N006 ( 9, 10) [000059] -A-----N--- t59 = * ADD long /--* t59 long N007 ( 11, 12) [000060] nA--G------ t60 = * IND long N008 ( 1, 1) [000061] ----------- t61 = CNS_INT long 0 /--* t60 long +--* t61 long N009 ( 13, 14) [000062] JA--G------ t62 = * EQ int /--* t62 int N010 ( 15, 16) [000063] -A--G------ * JTRUE void ------------ BB09 [0008] [???..???) -> BB07 (always), preds={BB02} succs={BB07} [000111] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 14, 5) [000003] H-CXG------ u3 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB07 [0006] [000..01F) -> BB04 (always), preds={BB02,BB09} succs={BB04} [000112] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 3, 2) [000057] ----------- t57 = LCL_VAR long V02 tmp1 N002 ( 1, 1) [000004] ----------- t4 = CNS_INT long 8 Fseq[FtnHolder] /--* t57 long +--* t4 long N003 ( 4, 3) [000005] ----G--N--- t5 = * ADD byref N004 ( 3, 2) [000001] !---------- t1 = LCL_VAR long V00 TypeCtx /--* t1 long arg0 in rcx N005 ( 17, 8) [000002] --C-G------ t2 = * CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE /--* t5 byref +--* t2 long N006 ( 24, 14) [000006] VAC-GO----- * STOREIND long ------------ BB04 [0003] [???..???) -> BB10,BB12 (cond), preds={BB07} succs={BB12,BB10} [000113] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 1, 4) [000064] H---------- t64 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t64 long N002 ( 5, 7) [000065] DA--------- * STORE_LCL_VAR long V03 tmp2 N003 ( 3, 2) [000066] ----------- t66 = LCL_VAR long V03 tmp2 N005 ( 1, 1) [000069] ----------- t69 = CNS_INT int -8 /--* t66 long +--* t69 int N006 ( 9, 10) [000070] -A-----N--- t70 = * ADD long /--* t70 long N007 ( 11, 12) [000071] nA--G------ t71 = * IND long N008 ( 1, 1) [000072] ----------- t72 = CNS_INT long 0 /--* t71 long +--* t72 long N009 ( 13, 14) [000073] JA--G------ t73 = * EQ int /--* t73 int N010 ( 15, 16) [000074] -A--G------ * JTRUE void ------------ BB12 [0011] [???..???) -> BB10 (always), preds={BB04} succs={BB10} [000114] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 14, 5) [000019] H-CXG------ u19 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB10 [0009] [???..???) -> BB06,BB05 (cond), preds={BB04,BB12} succs={BB05,BB06} [000115] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 3, 2) [000068] ----------- t68 = LCL_VAR long V03 tmp2 N002 ( 1, 1) [000020] ----------- t20 = CNS_INT long 8 Fseq[FtnHolder] /--* t68 long +--* t20 long N003 ( 4, 3) [000018] ----G--N--- t18 = * ADD byref /--* t18 byref N004 ( 6, 5) [000017] V---GO----- t17 = * IND int N005 ( 1, 1) [000016] ----------- t16 = CNS_INT int 2 /--* t17 int +--* t16 int N006 ( 8, 7) [000021] ----GO----- t21 = * AND int N007 ( 1, 1) [000022] ----------- t22 = CNS_INT int 0 /--* t21 int +--* t22 int N008 ( 10, 9) [000023] J---GO-N--- t23 = * NE int /--* t23 int N009 ( 12, 11) [000024] ----GO----- * JTRUE void ------------ BB05 [0004] [???..???) -> BB13,BB15 (cond), preds={BB10} succs={BB15,BB13} [000116] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 1, 4) [000075] H---------- t75 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t75 long N002 ( 5, 7) [000076] DA--------- * STORE_LCL_VAR long V04 tmp3 N003 ( 3, 2) [000077] ----------- t77 = LCL_VAR long V04 tmp3 N005 ( 1, 1) [000080] ----------- t80 = CNS_INT int -8 /--* t77 long +--* t80 int N006 ( 9, 10) [000081] -A-----N--- t81 = * ADD long /--* t81 long N007 ( 11, 12) [000082] nA--G------ t82 = * IND long N008 ( 1, 1) [000083] ----------- t83 = CNS_INT long 0 /--* t82 long +--* t83 long N009 ( 13, 14) [000084] JA--G------ t84 = * EQ int /--* t84 int N010 ( 15, 16) [000085] -A--G------ * JTRUE void ------------ BB15 [0014] [???..???) -> BB13 (always), preds={BB05} succs={BB13} [000117] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 14, 5) [000028] H-CXG------ u28 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB13 [0012] [???..???) -> BB03 (always), preds={BB05,BB15} succs={BB03} [000118] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 3, 2) [000079] ----------- t79 = LCL_VAR long V04 tmp3 N002 ( 1, 1) [000029] ----------- t29 = CNS_INT long 8 Fseq[FtnHolder] /--* t79 long +--* t29 long N003 ( 4, 3) [000027] ----G--N--- t27 = * ADD byref /--* t27 byref N004 ( 6, 5) [000026] V---GO----- t26 = * IND long /--* t26 long calli tgt N005 ( 23, 7) [000025] --CXGO----- * CALL ind void ------------ BB06 [0005] [???..???) -> BB16,BB18 (cond), preds={BB10} succs={BB18,BB16} [000119] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 1, 4) [000086] H---------- t86 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t86 long N002 ( 5, 7) [000087] DA--------- * STORE_LCL_VAR long V05 tmp4 N003 ( 3, 2) [000088] ----------- t88 = LCL_VAR long V05 tmp4 N005 ( 1, 1) [000091] ----------- t91 = CNS_INT int -8 /--* t88 long +--* t91 int N006 ( 9, 10) [000092] -A-----N--- t92 = * ADD long /--* t92 long N007 ( 11, 12) [000093] nA--G------ t93 = * IND long N008 ( 1, 1) [000094] ----------- t94 = CNS_INT long 0 /--* t93 long +--* t94 long N009 ( 13, 14) [000095] JA--G------ t95 = * EQ int /--* t95 int N010 ( 15, 16) [000096] -A--G------ * JTRUE void ------------ BB18 [0017] [???..???) -> BB16 (always), preds={BB06} succs={BB16} [000120] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 14, 5) [000040] H-CXG------ u40 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB16 [0015] [???..???) -> BB19,BB21 (cond), preds={BB06,BB18} succs={BB21,BB19} [000121] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 3, 2) [000090] ----------- t90 = LCL_VAR long V05 tmp4 N002 ( 1, 1) [000041] ----------- t41 = CNS_INT long 8 Fseq[FtnHolder] /--* t90 long +--* t41 long N003 ( 4, 3) [000039] ----G--N--- t39 = * ADD byref /--* t39 byref N004 ( 6, 5) [000038] V---GO----- t38 = * IND long N005 ( 1, 1) [000042] ----------- t42 = CNS_INT long -2 /--* t38 long +--* t42 long N006 ( 8, 7) [000037] ----GO-N--- t37 = * ADD long N007 ( 1, 1) [000043] ----------- t43 = CNS_INT long 8 /--* t37 long +--* t43 long N008 ( 9, 8) [000044] ----GO-N--- t44 = * ADD long /--* t44 long N009 ( 9, 8) [000045] ---XGO----- t45 = * IND long /--* t45 long N010 ( 13, 11) [000097] DA-XGO----- * STORE_LCL_VAR long V06 tmp5 [000122] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 1, 4) [000099] H---------- t99 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t99 long N002 ( 5, 7) [000100] DA--------- * STORE_LCL_VAR long V07 tmp6 N003 ( 3, 2) [000101] ----------- t101 = LCL_VAR long V07 tmp6 N005 ( 1, 1) [000104] ----------- t104 = CNS_INT int -8 /--* t101 long +--* t104 int N006 ( 9, 10) [000105] -A-----N--- t105 = * ADD long /--* t105 long N007 ( 11, 12) [000106] nA--G------ t106 = * IND long N008 ( 1, 1) [000107] ----------- t107 = CNS_INT long 0 /--* t106 long +--* t107 long N009 ( 13, 14) [000108] JA--G------ t108 = * EQ int /--* t108 int N010 ( 15, 16) [000109] -A--G------ * JTRUE void ------------ BB21 [0020] [???..???) -> BB19 (always), preds={BB16} succs={BB19} [000123] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 14, 5) [000032] H-CXG------ u32 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB19 [0018] [013..???) -> BB03 (always), preds={BB16,BB21} succs={BB03} [000124] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 3, 2) [000098] ----------- t98 = LCL_VAR long V06 tmp5 N002 ( 3, 2) [000103] ----------- t103 = LCL_VAR long V07 tmp6 N003 ( 1, 1) [000033] ----------- t33 = CNS_INT long 8 Fseq[FtnHolder] /--* t103 long +--* t33 long N004 ( 4, 3) [000031] ----G--N--- t31 = * ADD byref /--* t31 byref N005 ( 6, 5) [000030] V---GO----- t30 = * IND long N006 ( 1, 1) [000034] ----------- t34 = CNS_INT long -2 /--* t30 long +--* t34 long N007 ( 7, 6) [000035] ----GO-N--- t35 = * ADD long /--* t35 long N008 ( 9, 8) [000036] ---XGO----- t36 = * IND long /--* t98 long gctx in rcx +--* t36 long calli tgt N009 ( 29, 13) [000046] --CXGO----- * CALL ind void ------------ BB03 [0002] [01F..02F) (return), preds={BB13,BB19} succs={} [000125] ----------- IL_OFFSET void INLRT @ 0x01F[E-] N001 ( 1, 4) [000051] H---------- t51 = CNS_INT(h) ref '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' N002 ( 1, 4) [000052] H---------- t52 = CNS_INT(h) ref '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' /--* t51 ref arg0 in rcx +--* t52 ref arg1 in rdx N003 ( 16, 15) [000014] --CXG------ * CALL void Statics:CheckForFailure(System.String,System.String) [000126] ----------- IL_OFFSET void INLRT @ 0x02E[E-] N001 ( 0, 0) [000015] ----------- RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Checking Profile Weights (flags:0x16) No blocks were profiled, so nothing to check *************** Starting PHASE Lowering nodeinfo compEnregLocals() is false, setting doNotEnreg flag for all locals. Local V00 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set Local V01 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set Local V02 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set Local V03 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set Local V04 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set Local V05 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set Local V06 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set Local V07 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set lowering store lcl var/field (before): N001 ( 1, 4) [000053] H---------- t53 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t53 long N002 ( 5, 7) [000054] DA--------- * STORE_LCL_VAR long V02 tmp1 lowering store lcl var/field (after): N001 ( 1, 4) [000053] H---------- t53 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t53 long N002 ( 5, 7) [000054] DA--------- * STORE_LCL_VAR long V02 tmp1 Addressing mode: Base N003 ( 3, 2) [000055] ----------- * LCL_VAR long V02 tmp1 + -8 Removing unused node: N005 ( 1, 1) [000058] -c--------- * CNS_INT int -8 New addressing mode node: N006 ( 9, 10) [000059] ----------- * LEA(b+-8) long Lowering JTRUE: N003 ( 3, 2) [000055] ----------- t55 = LCL_VAR long V02 tmp1 /--* t55 long N006 ( 9, 10) [000059] -c--------- t59 = * LEA(b+-8) long /--* t59 long N007 ( 11, 12) [000060] nA--G------ t60 = * IND long N008 ( 1, 1) [000061] -c--------- t61 = CNS_INT long 0 /--* t60 long +--* t61 long N009 ( 13, 14) [000062] JA--G------ t62 = * EQ int /--* t62 int N010 ( 15, 16) [000063] -A--G------ * JTRUE void Lowering condition: N003 ( 3, 2) [000055] ----------- t55 = LCL_VAR long V02 tmp1 /--* t55 long N006 ( 9, 10) [000059] -c--------- t59 = * LEA(b+-8) long /--* t59 long N007 ( 11, 12) [000060] nA--G------ t60 = * IND long N008 ( 1, 1) [000061] -c--------- t61 = CNS_INT long 0 /--* t60 long +--* t61 long N009 ( 13, 14) [000062] JA--G------ t62 = * EQ int Lowering JTRUE Result: N003 ( 3, 2) [000055] ----------- t55 = LCL_VAR long V02 tmp1 /--* t55 long N006 ( 9, 10) [000059] -c--------- t59 = * LEA(b+-8) long /--* t59 long N007 ( 11, 12) [000060] nA--G------ t60 = * IND long N008 ( 1, 1) [000061] -c--------- t61 = CNS_INT long 0 /--* t60 long +--* t61 long N009 ( 13, 14) [000062] -A--G------ * CMP void N010 ( 15, 16) [000063] -A--G------ JCC void cond=UEQ lowering call (before): N001 ( 14, 5) [000003] H-CXG------ u3 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE args: ====== late: ====== Bumping outgoing arg space size from 0 to 32 for [000003] lowering call (after): N001 ( 14, 5) [000003] H-CXG------ u3 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE lowering call (before): N004 ( 3, 2) [000001] !---------- t1 = LCL_VAR long V00 TypeCtx /--* t1 long arg0 in rcx N005 ( 17, 8) [000002] --C-G------ t2 = * CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE args: ====== late: ====== lowering arg : N004 ( 3, 2) [000001] !---------- * LCL_VAR long V00 TypeCtx new node is : [000127] ----------- * PUTARG_REG long REG rcx lowering call (after): N004 ( 3, 2) [000001] !---------- t1 = LCL_VAR long V00 TypeCtx /--* t1 long [000127] ----------- t127 = * PUTARG_REG long REG rcx /--* t127 long arg0 in rcx N005 ( 17, 8) [000002] --C-G------ t2 = * CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE Addressing mode: Base N001 ( 3, 2) [000057] ----------- * LCL_VAR long V02 tmp1 + 8 Removing unused node: N002 ( 1, 1) [000004] -c--------- * CNS_INT long 8 Fseq[FtnHolder] New addressing mode node: N003 ( 4, 3) [000005] ----------- * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: oper is not supported N001 ( 3, 2) [000057] ----------- t57 = LCL_VAR long V02 tmp1 /--* t57 long N003 ( 4, 3) [000005] ----------- t5 = * LEA(b+8) byref N004 ( 3, 2) [000001] !---------- t1 = LCL_VAR long V00 TypeCtx /--* t1 long [000127] ----------- t127 = * PUTARG_REG long REG rcx /--* t127 long arg0 in rcx N005 ( 17, 8) [000002] --C-G------ t2 = * CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE /--* t5 byref +--* t2 long N006 ( 24, 14) [000006] VAC-GO----- * STOREIND long lowering store lcl var/field (before): N001 ( 1, 4) [000064] H---------- t64 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t64 long N002 ( 5, 7) [000065] DA--------- * STORE_LCL_VAR long V03 tmp2 lowering store lcl var/field (after): N001 ( 1, 4) [000064] H---------- t64 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t64 long N002 ( 5, 7) [000065] DA--------- * STORE_LCL_VAR long V03 tmp2 Addressing mode: Base N003 ( 3, 2) [000066] ----------- * LCL_VAR long V03 tmp2 + -8 Removing unused node: N005 ( 1, 1) [000069] -c--------- * CNS_INT int -8 New addressing mode node: N006 ( 9, 10) [000070] ----------- * LEA(b+-8) long Lowering JTRUE: N003 ( 3, 2) [000066] ----------- t66 = LCL_VAR long V03 tmp2 /--* t66 long N006 ( 9, 10) [000070] -c--------- t70 = * LEA(b+-8) long /--* t70 long N007 ( 11, 12) [000071] nA--G------ t71 = * IND long N008 ( 1, 1) [000072] -c--------- t72 = CNS_INT long 0 /--* t71 long +--* t72 long N009 ( 13, 14) [000073] JA--G------ t73 = * EQ int /--* t73 int N010 ( 15, 16) [000074] -A--G------ * JTRUE void Lowering condition: N003 ( 3, 2) [000066] ----------- t66 = LCL_VAR long V03 tmp2 /--* t66 long N006 ( 9, 10) [000070] -c--------- t70 = * LEA(b+-8) long /--* t70 long N007 ( 11, 12) [000071] nA--G------ t71 = * IND long N008 ( 1, 1) [000072] -c--------- t72 = CNS_INT long 0 /--* t71 long +--* t72 long N009 ( 13, 14) [000073] JA--G------ t73 = * EQ int Lowering JTRUE Result: N003 ( 3, 2) [000066] ----------- t66 = LCL_VAR long V03 tmp2 /--* t66 long N006 ( 9, 10) [000070] -c--------- t70 = * LEA(b+-8) long /--* t70 long N007 ( 11, 12) [000071] nA--G------ t71 = * IND long N008 ( 1, 1) [000072] -c--------- t72 = CNS_INT long 0 /--* t71 long +--* t72 long N009 ( 13, 14) [000073] -A--G------ * CMP void N010 ( 15, 16) [000074] -A--G------ JCC void cond=UEQ lowering call (before): N001 ( 14, 5) [000019] H-CXG------ u19 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE args: ====== late: ====== lowering call (after): N001 ( 14, 5) [000019] H-CXG------ u19 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE Addressing mode: Base N001 ( 3, 2) [000068] ----------- * LCL_VAR long V03 tmp2 + 8 Removing unused node: N002 ( 1, 1) [000020] -c--------- * CNS_INT long 8 Fseq[FtnHolder] New addressing mode node: N003 ( 4, 3) [000018] ----------- * LEA(b+8) byref Lowering JTRUE: N001 ( 3, 2) [000068] ----------- t68 = LCL_VAR long V03 tmp2 /--* t68 long N003 ( 4, 3) [000018] -c--------- t18 = * LEA(b+8) byref /--* t18 byref N004 ( 6, 5) [000017] V---GO----- t17 = * IND int N005 ( 1, 1) [000016] -c--------- t16 = CNS_INT int 2 /--* t17 int +--* t16 int N006 ( 8, 7) [000021] ----GO----- t21 = * AND int N007 ( 1, 1) [000022] -c--------- t22 = CNS_INT int 0 /--* t21 int +--* t22 int N008 ( 10, 9) [000023] J---GO-N--- t23 = * NE int /--* t23 int N009 ( 12, 11) [000024] ----GO----- * JTRUE void Lowering condition: N001 ( 3, 2) [000068] ----------- t68 = LCL_VAR long V03 tmp2 /--* t68 long N003 ( 4, 3) [000018] -c--------- t18 = * LEA(b+8) byref /--* t18 byref N004 ( 6, 5) [000017] V---GO----- t17 = * IND int N005 ( 1, 1) [000016] -c--------- t16 = CNS_INT int 2 /--* t17 int +--* t16 int N006 ( 8, 7) [000021] ----GO----- t21 = * AND int N007 ( 1, 1) [000022] -c--------- t22 = CNS_INT int 0 /--* t21 int +--* t22 int N008 ( 10, 9) [000023] J---GO-N--- t23 = * NE int Lowering JTRUE Result: N001 ( 3, 2) [000068] ----------- t68 = LCL_VAR long V03 tmp2 /--* t68 long N003 ( 4, 3) [000018] -c--------- t18 = * LEA(b+8) byref /--* t18 byref N004 ( 6, 5) [000017] V---GO----- t17 = * IND int N005 ( 1, 1) [000016] -c--------- t16 = CNS_INT int 2 /--* t17 int +--* t16 int N006 ( 8, 7) [000021] ----GO----- t21 = * AND int N007 ( 1, 1) [000022] -c--------- t22 = CNS_INT int 0 /--* t21 int +--* t22 int N008 ( 10, 9) [000023] ----GO-N--- * CMP void N009 ( 12, 11) [000024] ----GO----- JCC void cond=UNE lowering store lcl var/field (before): N001 ( 1, 4) [000075] H---------- t75 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t75 long N002 ( 5, 7) [000076] DA--------- * STORE_LCL_VAR long V04 tmp3 lowering store lcl var/field (after): N001 ( 1, 4) [000075] H---------- t75 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t75 long N002 ( 5, 7) [000076] DA--------- * STORE_LCL_VAR long V04 tmp3 Addressing mode: Base N003 ( 3, 2) [000077] ----------- * LCL_VAR long V04 tmp3 + -8 Removing unused node: N005 ( 1, 1) [000080] -c--------- * CNS_INT int -8 New addressing mode node: N006 ( 9, 10) [000081] ----------- * LEA(b+-8) long Lowering JTRUE: N003 ( 3, 2) [000077] ----------- t77 = LCL_VAR long V04 tmp3 /--* t77 long N006 ( 9, 10) [000081] -c--------- t81 = * LEA(b+-8) long /--* t81 long N007 ( 11, 12) [000082] nA--G------ t82 = * IND long N008 ( 1, 1) [000083] -c--------- t83 = CNS_INT long 0ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_GenericOverGenericStructOverTypeParameterGenericValuetype_GenericOverString_CuriouslyRecurringGeneric_GenericMethodOverTypeParameter[System.__Canon]()' during 'Generate code' (IL size 47; hash 0xd2d11753; MinOpts) /--* t82 long +--* t83 long N009 ( 13, 14) [000084] JA--G------ t84 = * EQ int /--* t84 int N010 ( 15, 16) [000085] -A--G------ * JTRUE void Lowering condition: N003 ( 3, 2) [000077] ----------- t77 = LCL_VAR long V04 tmp3 /--* t77 long N006 ( 9, 10) [000081] -c--------- t81 = * LEA(b+-8) long /--* t81 long N007 ( 11, 12) [000082] nA--G------ t82 = * IND long N008 ( 1, 1) [000083] -c--------- t83 = CNS_INT long 0 /--* t82 long +--* t83 long N009 ( 13, 14) [000084] JA--G------ t84 = * EQ int Lowering JTRUE Result: N003 ( 3, 2) [000077] ----------- t77 = LCL_VAR long V04 tmp3 /--* t77 long N006 ( 9, 10) [000081] -c--------- t81 = * LEA(b+-8) long /--* t81 long N007 ( 11, 12) [000082] nA--G------ t82 = * IND long N008 ( 1, 1) [000083] -c--------- t83 = CNS_INT long 0 /--* t82 long +--* t83 long N009 ( 13, 14) [000084] -A--G------ * CMP void N010 ( 15, 16) [000085] -A--G------ JCC void cond=UEQ lowering call (before): N001 ( 14, 5) [000028] H-CXG------ u28 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE args: ====== late: ====== lowering call (after): N001 ( 14, 5) [000028] H-CXG------ u28 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE Addressing mode: Base N001 ( 3, 2) [000079] ----------- * LCL_VAR long V04 tmp3 + 8 Removing unused node: N002 ( 1, 1) [000029] -c--------- * CNS_INT long 8 Fseq[FtnHolder] New addressing mode node: N003 ( 4, 3) [000027] ----------- * LEA(b+8) byref lowering call (before): N001 ( 3, 2) [000079] ----------- t79 = LCL_VAR long V04 tmp3 /--* t79 long N003 ( 4, 3) [000027] -c--------- t27 = * LEA(b+8) byref /--* t27 byref N004 ( 6, 5) [000026] V---GO----- t26 = * IND long /--* t26 long calli tgt N005 ( 23, 7) [000025] --CXGO----- * CALL ind void args: ====== late: ====== lowering call (after): N001 ( 3, 2) [000079] ----------- t79 = LCL_VAR long V04 tmp3 /--* t79 long N003 ( 4, 3) [000027] -c--------- t27 = * LEA(b+8) byref /--* t27 byref N004 ( 6, 5) [000026] Vc--GO----- t26 = * IND long REG NA /--* t26 long calli tgt N005 ( 23, 7) [000025] --CXGO----- * CALL ind void lowering store lcl var/field (before): N001 ( 1, 4) [000086] H---------- t86 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t86 long N002 ( 5, 7) [000087] DA--------- * STORE_LCL_VAR long V05 tmp4 lowering store lcl var/field (after): N001 ( 1, 4) [000086]ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_NonGenericNonGenericClass_GenericOverConstrainedType_CuriouslyRecurringGeneric_GenericMethodOverTypeParameter[System.__Canon,System.__Canon]()' during 'Generate code' (IL size 47; hash 0xd30ca96e; MinOpts) H---------- t86 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t86 long N002 ( 5, 7) [000087] DA--------- * STORE_LCL_VAR long V05 tmp4 Addressing mode: Base N003 ( 3, 2) [000088] ----------- * LCL_VAR long V05 tmp4 + -8 Removing unused node: N005 ( 1, 1) [000091] -c--------- * CNS_INT int -8 New addressing mode node: N006 ( 9, 10) [000092] ----------- * LEA(b+-8) long Lowering JTRUE: N003 ( 3, 2) [000088] ----------- t88 = LCL_VAR long V05 tmp4 /--* t88 long N006 ( 9, 10) [000092] -c--------- t92 = * LEA(b+-8) long /--* t92 long N007 ( 11, 12) [000093] nA--G------ t93 = * IND long N008 ( 1, 1) [000094] -c--------- t94 = CNS_INT long 0 /--* t93 long +--* t94 long N009 ( 13, 14) [000095] JA--G------ t95 = * EQ int /--* t95 int N010 ( 15, 16) [000096] -A--G------ * JTRUE void Lowering condition: N003 ( 3, 2) [000088] ----------- t88 = LCL_VAR long V05 tmp4 /--* t88 long N006 ( 9, 10) [000092] -c--------- t92 = * LEA(b+-8) long /--* t92 long N007 ( 11, 12) [000093] nA--G------ t93 = * IND long N008 ( 1, 1) [000094] -c--------- t94 = CNS_INT long 0 /--* t93 long +--* t94 long N009 ( 13, 14) [000095] JA--G------ t95 = * EQ int Lowering JTRUE Result: N003 ( 3, 2) [000088] ----------- t88 = LCL_VAR long V05 tmp4 /--* t88 long N006 ( 9, 10) [000092] -c--------- t92 = * LEA(b+-8) long /--* t92 long N007 ( 11, 12) [000093] nA--G------ t93 = * IND long N008 ( 1, 1) [000094] -c--------- t94 = CNS_INT long 0 /--* t93 long +--* t94 long N009 ( 13, 14) [000095] -A--G------ * CMP void N010 ( 15, 16) [000096] -A--G------ JCC void cond=UEQ lowering call (before): N001 ( 14, 5) [000040] H-CXG------ u40 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE args: ====== late: ====== lowering call (after): N001 ( 14, 5) [000040] H-CXG------ u40 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE Addressing mode: Base N001 ( 3, 2) [000090] ----------- * LCL_VAR long V05 tmp4 + 8 Removing unused node: N002 ( 1, 1) [000041] -c--------- * CNS_INT long 8 Fseq[FtnHolder] New addressing mode node: N003 ( 4, 3) [000039] ----------- * LEA(b+8) byref Addressing mode: Base N004 ( 6, 5) [000038] V---GO----- * IND long + 6 Removing unused node: N007 ( 1, 1) [000043] -c--------- * CNS_INT long 8 Removing unused node: N006 ( 8, 7) [000037] ----GO-N--- * ADD long Removing unused node: N005 ( 1, 1) [000042] -c--------- * CNS_INT long -2 New addressing mode node: N008 ( 9, 8) [000044] ----------- * LEA(b+6) long lowering store lcl var/field (before): N001 ( 3, 2) [000090] ----------- t90 = LCL_VAR long V05 tmp4 /--* t90 long N003 ( 4, 3) [000039] -c--------- t39 = * LEA(b+8) byref /--* t39 byref N004 ( 6, 5) [000038] V---GO----- t38 = * IND long /--* t38 long N008 ( 9, 8) [000044] -c--------- t44 = * LEA(b+6) long /--* t44 long N009 ( 9, 8) [000045] ---XGO----- t45 = * IND long /--* t45 long N010 ( 13, 11) [000097] DA-XGO----- * STORE_LCL_VAR long V06 tmp5 lowering store lcl var/field (after): N001 ( 3, 2) [000090] ----------- t90 = LCL_VAR long V05 tmp4 /--* t90 long N003 ( 4, 3) [000039] -c--------- t39 = * LEA(b+8) byref /--* t39 byref N004 ( 6, 5) [000038] V---GO----- t38 = * IND long /--* t38 long N008 ( 9, 8) [000044] -c--------- t44 = * LEA(b+6) long /--* t44 long N009 ( 9, 8) [000045] ---XGO----- t45 = * IND long /--* t45 long N010 ( 13, 11) [000097] DA-XGO----- * STORE_LCL_VAR long V06 tmp5 lowering store lcl var/field (before): N001 ( 1, 4) [000099] H---------- t99 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t99 long N002 ( 5, 7) [000100] DA--------- * STORE_LCL_VAR long V07 tmp6 lowering store lcl var/field (after): N001 ( 1, 4) [000099] H---------- t99 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t99 long N002 ( 5, 7) [000100] DA--------- * STORE_LCL_VAR long V07 tmp6 Addressing mode: Base N003 ( 3, 2) [000101] ----------- * LCL_VAR long V07 tmp6 + -8 Removing unused node: N005 ( 1, 1) [000104] -c--------- * CNS_INT int -8 New addressing mode node: N006 ( 9, 10) [000105] ----------- * LEA(b+-8) long Lowering JTRUE: N003 ( 3, 2) [000101] ----------- t101 = LCL_VAR long V07 tmp6 /--* t101 long N006 ( 9, 10) [000105] -c--------- t105 = * LEA(b+-8) long /--* t105 long N007 ( 11, 12) [000106] nA--G------ t106 = * IND long N008 ( 1, 1) [000107] -c--------- t107 = CNS_INT long 0 /--* t106 long +--* t107 long N009 ( 13, 14) [000108] JA--G------ t108 = * EQ int /--* t108 int N010 ( 15, 16) [000109] -A--G------ * JTRUE void Lowering condition: N003 ( 3, 2) [000101] ----------- t101 = LCL_VAR long V07 tmp6 /--* t101 long N006 ( 9, 10) [000105] -c--------- t105 = * LEA(b+-8) long /--* t105 long N007 ( 11, 12) [000106] nA--G------ t106 = * IND long N008 ( 1, 1) [000107] -c--------- t107 = CNS_INT long 0 /--* t106 long +--* t107 long N009 ( 13, 14) [000108] JA--G------ t108 = * EQ int Lowering JTRUE Result: N003 ( 3, 2) [000101] ----------- t101 = LCL_VAR long V07 tmp6 /--* t101 long N006 ( 9, 10) [000105] -c--------- t105 = * LEA(b+-8) long /--* t105 long N007 ( 11, 12) [000106] nA--G------ t106 = * IND long N008 ( 1, 1) [000107] -c--------- t107 = CNS_INT long 0 /--* t106 long +--* t107 long N009 ( 13, 14) [000108] -A--G------ * CMP void N010 ( 15, 16) [000109] -A--G------ JCC void cond=UEQ lowering call (before): N001 ( 14, 5) [000032] H-CXG------ u32 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE args: ====== late: ====== lowering call (after): N001 ( 14, 5) [000032] H-CXG------ u32 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE Addressing mode: Base N002 ( 3, 2) [000103] ----------- * LCL_VAR long V07 tmp6 + 8 Removing unused node: N003 ( 1, 1) [000033] -c--------- * CNS_INT long 8 Fseq[FtnHolder] New addressing mode node: N004 ( 4, 3) [000031] ----------- * LEA(b+8) byref Addressing mode: Base N005 ( 6, 5) [000030] V---GO----- * IND long + -2 Removing unused node: N006 ( 1, 1) [000034] -c--------- * CNS_INT long -2 New addressing mode node: N007 ( 7, 6) [000035] ----------- * LEA(b+-2) long lowering call (before): N001 ( 3, 2) [000098] ----------- t98 = LCL_VAR long V06 tmp5 N002 ( 3, 2) [000103] ----------- t103 = LCL_VAR long V07 tmp6 /--* t103 long N004 ( 4, 3) [000031] -c--------- t31 = * LEA(b+8) byref /--* t31 byref N005 ( 6, 5) [000030] V---GO----- t30 = * IND long /--* t30 long N007 ( 7, 6) [000035] -c--------- t35 = * LEA(b+-2) long /--* t35 long N008 ( 9, 8) [000036] ---XGO----- t36 = * IND long /--* t98 long gctx in rcx +--* t36 long calli tgt N009 ( 29, 13) [000046] --CXGO----- * CALL ind void args: ====== late: ====== lowering arg : N001 ( 3, 2) [000098] ----------- * LCL_VAR long V06 tmp5 new node is : [000128] ----------- * PUTARG_REG long REG rcx lowering call (after): N001 ( 3, 2) [000098] ----------- t98 = LCL_VAR long V06 tmp5 /--* t98 long [000128] ----------- t128 = * PUTARG_REG long REG rcx N002 ( 3, 2) [000103] ----------- t103 = LCL_VAR long V07 tmp6 /--* t103 long N004 ( 4, 3) [000031] -c--------- t31 = * LEA(b+8) byref /--* t31 byref N005 ( 6, 5) [000030] V---GO----- t30 = * IND long /--* t30 long N007 ( 7, 6) [000035] -c--------- t35 = * LEA(b+-2) long /--* t35 long N008 ( 9, 8) [000036] -c-XGO----- t36 = * IND long REG NA /--* t128 long gctx in rcx +--* t36 long calli tgt N009 ( 29, 13) [000046] --CXGO----- * CALL ind void lowering call (before): N001 ( 1, 4) [000051] H---------- t51 = CNS_INT(h) ref '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' N002 ( 1, 4) [000052] H---------- t52 = CNS_INT(h) ref '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' /--* t51 ref arg0 in rcx +--* t52 ref arg1 in rdx N003 ( 16, 15) [000014] --CXG------ * CALL void Statics:CheckForFailure(System.String,System.String) args: ====== late: ====== lowering arg : N001 ( 1, 4) [000051] H---------- * CNS_INT(h) ref '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' new node is : [000129] ----------- * PUTARG_REG ref REG rcx lowering arg : N002 ( 1, 4) [000052] H---------- * CNS_INT(h) ref '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' new node is : [000130] ----------- * PUTARG_REG ref REG rdx lowering call (after): N001 ( 1, 4) [000051] H---------- t51 = CNS_INT(h) ref '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' /--* t51 ref [000129] ----------- t129 = * PUTARG_REG ref REG rcx N002 ( 1, 4) [000052] H---------- t52 = CNS_INT(h) ref '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' /--* t52 ref [000130] ----------- t130 = * PUTARG_REG ref REG rdx /--* t129 ref arg0 in rcx +--* t130 ref arg1 in rdx N003 ( 16, 15) [000014] --CXG------ * CALL void Statics:CheckForFailure(System.String,System.String) lowering GT_RETURN N001 ( 0, 0) [000015] ----------- * RETURN void ============ Lower has completed modifying nodes. ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i LIR keep internal q BB02 [0001] 1 BB01 1 [???..???)-> BB07,BB09 ( cond ) i LIR hascall BB09 [0008] 1 BB02 0 [???..???)-> BB07 (always) LIR rare internal q BB07 [0006] 2 BB02,BB09 1 [000..01F)-> BB04 (always) i LIR hascall q BB04 [0003] 1 BB07 1 [???..???)-> BB10,BB12 ( cond ) i LIR internal hascall BB12 [0011] 1 BB04 0 [???..???)-> BB10 (always) LIR rare internal q BB10 [0009] 2 BB04,BB12 1 [???..???)-> BB06,BB05 ( cond ) i LIR internal hascall q BB05 [0004] 1 BB10 0.80 [???..???)-> BB13,BB15 ( cond ) i LIR internal hascall gcsafe BB15 [0014] 1 BB05 0 [???..???)-> BB13 (always) LIR rare internal q BB13 [0012] 2 BB05,BB15 0.80 [???..???)-> BB03 (always) i LIR internal hascall gcsafe BB06 [0005] 1 BB10 0.20 [???..???)-> BB16,BB18 ( cond ) i LIR internal hascall gcsafe BB18 [0017] 1 BB06 0 [???..???)-> BB16 (always) LIR rare internal q BB16 [0015] 2 BB06,BB18 0.20 [???..???)-> BB19,BB21 ( cond ) i LIR internal hascall gcsafe BB21 [0020] 1 BB16 0 [???..???)-> BB19 (always) LIR rare internal q BB19 [0018] 2 BB16,BB21 0.20 [013..???)-> BB03 (always) i LIR internal hascall gcsafe q BB03 [0002] 2 BB13,BB19 1 [01F..02F) (return) i LIR internal hascall gcsafe ---------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [???..???) -> BB02 (always), preds={} succs={BB02} N001 ( 0, 0) [000000] ----------- NOP void ------------ BB02 [0001] [???..???) -> BB07,BB09 (cond), preds={BB01} succs={BB09,BB07} [000110] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 1, 4) [000053] H---------- t53 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t53 long N002 ( 5, 7) [000054] DA--------- * STORE_LCL_VAR long V02 tmp1 N003 ( 3, 2) [000055] ----------- t55 = LCL_VAR long V02 tmp1 /--* t55 long N006 ( 9, 10) [000059] -c--------- t59 = * LEA(b+-8) long /--* t59 long N007 ( 11, 12) [000060] nA--G------ t60 = * IND long N008 ( 1, 1) [000061] -c--------- t61 = CNS_INT long 0 /--* t60 long +--* t61 long N009 ( 13, 14) [000062] -A--G------ * CMP void N010 ( 15, 16) [000063] -A--G------ JCC void cond=UEQ ------------ BB09 [0008] [???..???) -> BB07 (always), preds={BB02} succs={BB07} [000111] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 14, 5) [000003] H-CXG------ u3 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB07 [0006] [000..01F) -> BB04 (always), preds={BB02,BB09} succs={BB04} [000112] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 3, 2) [000057] ----------- t57 = LCL_VAR long V02 tmp1 /--* t57 long N003 ( 4, 3) [000005] -c--------- t5 = * LEA(b+8) byref N004 ( 3, 2) [000001] !---------- t1 = LCL_VAR ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_GenericOverTypeParameterGenericValuetype_GenericOverString_CuriouslyRecurringGeneric_GenericMethodOverString[System.__Canon]()' during 'Generate code' (IL size 47; hash 0x03b569bf; MinOpts) long V00 TypeCtx /--* t1 long [000127] ----------- t127 = * PUTARG_REG long REG rcx /--* t127 long arg0 in rcx N005 ( 17, 8) [000002] --C-G------ t2 = * CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE /--* t5 byref +--* t2 long N006 ( 24, 14) [000006] VAC-GO----- * STOREIND long ------------ BB04 [0003] [???..???) -> BB10,BB12 (cond), preds={BB07} succs={BB12,BB10} [000113] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 1, 4) [000064] H---------- t64 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t64 long N002 ( 5, 7) [000065] DA--------- * STORE_LCL_VAR long V03 tmp2 N003 ( 3, 2) [000066] ----------- t66 = LCL_VAR long V03 tmp2 /--* t66 long N006 ( 9, 10) [000070] -c--------- t70 = * LEA(b+-8) long /--* t70 long N007 ( 11, 12) [000071] nA--G------ t71 = * IND long N008 ( 1, 1) [000072] -c--------- t72 = CNS_INT long 0 /--* t71 long +--* t72 long N009 ( 13, 14) [000073] -A--G------ * CMP void N010 ( 15, 16) [000074] -A--G------ JCC void cond=UEQ ------------ BB12 [0011] [???..???) -> BB10 (always), preds={BB04} succs={BB10} [000114] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 14, 5) [000019] H-CXG------ u19 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB10 [0009] [???..???) -> BB06,BB05 (cond), preds={BB04,BB12} succs={BB05,BB06} [000115] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 3, 2) [000068] ----------- t68 = LCL_VAR long V03 tmp2 /--* t68 long N003 ( 4, 3) [000018] -c--------- t18 = * LEA(b+8) byref /--* t18 byref N004 ( 6, 5) [000017] V---GO----- t17 = * IND int N005 ( 1, 1) [000016] -c--------- t16 = CNS_INT int 2 /--* t17 int +--* t16 int N006 ( 8, 7) [000021] ----GO----- t21 = * AND int N007 ( 1, 1) [000022] -c--------- t22 = CNS_INT int 0 /--* t21 int +--* t22 int N008 ( 10, 9) [000023] ----GO-N--- * CMP void N009 ( 12, 11) [000024] ----GO----- JCC void cond=UNE ------------ BB05 [0004] [???..???) -> BB13,BB15 (cond), preds={BB10} succs={BB15,BB13} [000116] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 1, 4) [000075] H---------- t75 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t75 long N002 ( 5, 7) [000076] DA--------- * STORE_LCL_VAR long V04 tmp3 N003 ( 3, 2) [000077] ----------- t77 = LCL_VAR long V04 tmp3 /--* t77 long N006 ( 9, 10) [000081] -c--------- t81 = * LEA(b+-8) long /--* t81 long N007 ( 11, 12) [000082] nA--G------ t82 = * IND long N008 ( 1, 1) [000083] -c--------- t83 = CNS_INT long 0 /--* t82 long +--* t83 long N009 ( 13, 14) [000084] -A--G------ * CMP void N010 ( 15, 16) [000085] -A--G------ JCC void cond=UEQ ------------ BB15 [0014] [???..???) -> BB13 (always), preds={BB05} succs={BB13} [000117] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 14, 5) [000028] H-CXG------ u28 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB13 [0012] [???..???) -> BB03 (always), preds={BB05,BB15} succs={BB03} [000118] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 3, 2) [000079] ----------- t79 = LCL_VAR long V04 tmp3 /--* t79 long N003 ( 4, 3) [000027] -c-----ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 -ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_GenericOverTypeParameterGenericValuetype_GenericOverString_CuriouslyRecurringGeneric_GenericMethodOverTypeParameter[System.__Canon]()' during 'Generate code' (IL size 47---; hash 0x1f1113fb; MinOpts) t27 = * LEA(b+8) byref /--* t27 byref N004 ( 6, 5) [000026] Vc--GO----- t26 = * IND long REG NA /--* t26 long calli tgt N005 ( 23, 7) [000025] --CXGO----- * CALL ind void ------------ BB06 [0005] [???..???) -> BB16,BB18 (cond), preds={BB10} succs={BB18,BB16} [000119] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 1, 4) [000086] H---------- t86 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t86 long N002 ( 5, 7) [000087] DA--------- * STORE_LCL_VAR long V05 tmp4 N003 ( 3, 2) [000088] ----------- t88 = LCL_VAR long V05 tmp4 /--* t88 long N006 ( 9, 10) [000092] -c--------- t92 = * LEA(b+-8) long /--* t92 long N007 ( 11, 12) [000093] nA--G------ t93 = * IND long N008 ( 1, 1) [000094] -c--------- t94 = CNS_INT long 0 /--* t93 long +--* t94 long N009 ( 13, 14) [000095] -A--G------ * CMP void N010 ( 15, 16) [000096] -A--G------ JCC void cond=UEQ ------------ BB18 [0017] [???..???) -> BB16 (always), preds={BB06} succs={BB16} [000120] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 14, 5) [000040] H-CXG------ u40 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB16 [0015] [???..???) -> BB19,BB21 (cond), preds={BB06,BB18} succs={BB21,BB19} [000121] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 3, 2) [000090] ----------- t90 = LCL_VAR long V05 tmp4 /--* t90 long N003 ( 4, 3) [000039] -c--------- t39 = * LEA(b+8) byref /--* t39 byref N004 ( 6, 5) [000038] V---GO----- t38 = * IND long /--* t38 long N008 ( 9, 8) [000044] -c--------- t44 = * LEA(b+6) long /--* t44 long N009 ( 9, 8) [000045] ---XGO----- t45 = * IND long /--* t45 long N010 ( 13, 11) [000097] DA-XGO----- * STORE_LCL_VAR long V06 tmp5 [000122] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 1, 4) [000099] H---------- t99 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t99 long N002 ( 5, 7) [000100] DA--------- * STORE_LCL_VAR long V07 tmp6 N003 ( 3, 2) [000101] ----------- t101 = LCL_VAR long V07 tmp6 /--* t101 long N006 ( 9, 10) [000105] -c--------- t105 = * LEA(b+-8) long /--* t105 long N007 ( 11, 12) [000106] nA--G------ t106 = * IND long N008 ( 1, 1) [000107] -c--------- t107 = CNS_INT long 0 /--* t106 long +--* t107 long N009 ( 13, 14) [000108] -A--G------ * CMP void N010 ( 15, 16) [000109] -A--G------ JCC void cond=UEQ ------------ BB21 [0020] [???..???) -> BB19 (always), preds={BB16} succs={BB19} [000123] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 14, 5) [000032] H-CXG------ u32 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB19 [0018] [013..???) -> BB03 (always), preds={BB16,BB21} succs={BB03} [000124] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 3, 2) [000098] ----------- t98 = LCL_VAR long V06 tmp5 /--* t98 long [000128] ----------- t128 = * PUTARG_REG long REG rcx N002 ( 3, 2) [000103] ----------- t103 = LCL_VAR long V07 tmp6 /--* t103 long N004 ( 4, 3) [000031] -c--------- t31 = * LEA(b+8) byref /--* t31 byref N005 ( 6, 5) [000030] V---GO----- t30 = * IND long /--* t30 long N007 ( 7, 6) [000035] -c--------- t35 = * LEA(b+-2) long /--* t35 long N008 ( 9, 8) [000036] -c-XGO----- t36 = * IND long REG NA /--* t128 long gctx in rcx +--* t36 long calli tgt N009 ( 29, 13) [000046] --CXGO----- * CALL ind void ------------ BB03 [0002] [01F..02F) (return), preds={BB13,BB19} succs={} [000125] ----------- IL_OFFSET void INLRT @ 0x01F[E-] N001 ( 1, 4) [000051] H---------- t51 = CNS_INT(h) ref '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' /--* t51 ref [000129] ----------- t129 = * PUTARG_REG ref REG rcx N002 ( 1, 4) [000052] H---------- t52 = CNS_INT(h) ref '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' /--* t52 ref [000130] ----------- t130 = * PUTARG_REG ref REG rdx /--* t129 ref arg0 in rcx +--* t130 ref arg1 in rdx N003 ( 16, 15) [000014] --CXG------ * CALL void Statics:CheckForFailure(System.String,System.String) [000126] ----------- IL_OFFSET void INLRT @ 0x02E[E-] N001 ( 0, 0) [000015] ----------- RETURN void ------------------------------------------------------------------------------------------------------------------- *** lvaComputeRefCounts *** *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 TypeCtx long do-not-enreg[] ; V01 OutArgs struct <32> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ; V02 tmp1 long do-not-enreg[] "fgMakeTemp is creating a new local variable" ; V03 tmp2 long do-not-enreg[] "fgMakeTemp is creating a new local variable" ; V04 tmp3 long do-not-enreg[] "fgMakeTemp is creating a new local variable" ; V05 tmp4 long do-not-enreg[] "fgMakeTemp is creating a new local variable" ; V06 tmp5 long do-not-enreg[] "Spilling to split statement for tree" ; V07 tmp6 long do-not-enreg[] "fgMakeTemp is creating a new local variable" In fgLocalVarLivenessInit *************** In fgPerBlockLocalVarLiveness() *************** In fgInterBlockLocalVarLiveness() *************** In fgExtendDbgLifetimes() Marking vars alive over their entire scope : Local variable scopes = 1 VarNum LVNum Name Beg End Sorted by enter scope: 0: 00h 00h V00 TypeCtx 000h 02Fh <-- next enter scope Sorted by exit scope: 0: 00h 00h V00 TypeCtx 000h 02Fh <-- next exit scope Scope info: block BB01 marking in scope: {} Scope info: block BB02 marking in scope: {} Scope info: block BB09 marking in scope: {} Scope info: block BB07 marking in scope: {} Scope info: block BB04 marking in scope: {} Scope info: block BB12 marking in scope: {} Scope info: block BB10 marking in scope: {} Scope info: block BB05 marking in scope: {} Scope info: block BB15 marking in scope: {} Scope info: block BB13 marking in scope: {} Scope info: block BB06 marking in scope: {} Scope info: block BB18 marking in scope: {} Scope info: block BB16 marking in scope: {} Scope info: block BB21 marking in scope: {} Scope info: block BB19 marking in scope: {} Scope info: block BB03 marking in scope: {} Debug scopes: BB01: {} BB02: {} BB09: {} BB07: {} BB04: {} BB12: {} BB10: {} BB05: {} BB15: {} BB13: {} BB06: {} BB18: {} BB16: {} BB21: {} BB19: {} BB03: {} Scope info: block BB01 UNmarking in scope: {} BB liveness after fgExtendDbgLifetimes(): BB01 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap BB02 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap BB09 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap BB07 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap BB04 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap BB12 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap BB10 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap BB05 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap BB15 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap BB13 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap BB06 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap BB18 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap BB16 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap BB21 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap BB19 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap BB03 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap *************** In fgRemoveDeadBlocks() New BlockSet epoch 2, # of blocks (including unused BB00): 22, bitset array size: 1 (short) Removing unreachable blocks for fgRemoveDeadBlocks iteration #1 *************** In fgDebugCheckBBlist *** lvaComputeRefCounts *** *************** Finishing PHASE Lowering nodeinfo Trees after Lowering nodeinfo ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i LIR keep internal q BB02 [0001] 1 BB01 1 [???..???)-> BB07,BB09 ( cond ) i LIR hascall BB09 [0008] 1 BB02 0 [???..???)-> BB07 (always) LIR rare internal q BB07 [0006] 2 BB02,BB09 1 [000..01F)-> BB04 (always) i LIR hascall q BB04 [0003] 1 BB07 1 [???..???)-> BB10,BB12 ( cond ) i LIR internal hascall BB12 [0011] 1 BB04 0 [???..???)-> BB10 (always) LIR rare internal q BB10 [0009] 2 BB04,BB12 1 [???..???)-> BB06,BB05 ( cond ) i LIR internal hascall q BB05 [0004] 1 BB10 0.80 [???..???)-> BB13,BB15 ( cond ) i LIR internal hascall gcsafe BB15 [0014] 1 BB05 0 [???..???)-> BB13 (always) LIR rare internal q BB13 [0012] 2 BB05,BB15 0.80 [???..???)-> BB03 (always) i LIR internal hascall gcsafe BB06 [0005] 1 BB10 0.20 [???..???)-> BB16,BB18 ( cond ) i LIR internal hascall gcsafe BB18 [0017] 1 BB06 0 [???..???)-> BB16 (always) LIR rare internal q BB16 [0015] 2 BB06,BB18 0.20 [???..???)-> BB19,BB21 ( cond ) i LIR internal hascall gcsafe BB21 [0020] 1 BB16 0 [???..???)-> BB19 (always) LIR rare internal q BB19 [0018] 2 BB16,BB21 0.20 [013..???)-> BB03 (always) i LIR internal hascall gcsafe q BB03 [0002] 2 BB13,BB19 1 [01F..02F) (return) i LIR internal hascall gcsafe ---------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [???..???) -> BB02 (always), preds={} succs={BB02} N001 ( 0, 0) [000000] ----------- NOP void ------------ BB02 [0001] [???..???) -> BB07,BB09 (cond), preds={BB01} succs={BB09,BB07} [000110] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 1, 4) [000053] H---------- t53 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t53 long N002 ( 5, 7) [000054] DA--------- * STORE_LCL_VAR long V02 tmp1 N003 ( 3, 2) [000055] ----------- t55 = LCL_VAR long V02 tmp1 /--* t55 long N006 ( 9, 10) [000059] -c--------- t59 = * LEA(b+-8) long /--* t59 long N007 ( 11, 12) [000060] nA--G------ t60 = * IND long N008 ( 1, 1) [000061] -c--------- t61 = CNS_INT long 0 /--* t60 long +--* t61 long N009 ( 13, 14) [000062] -A--G------ * CMP void N010 ( 15, 16) [000063] -A--G------ JCC void cond=UEQ ------------ BB09 [0008] [???..???) -> BB07 (always), preds={BB02} succs={BB07} [000111] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 14, 5) [000003] H-CXG------ u3 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB07 [0006] [000..01F) -> BB04 (always), preds={BB02,BB09} succs={BB04} [000112] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 3, 2) [000057] ----------- t57 = LCL_VAR long V02 tmp1 /--* t57 long N003 ( 4, 3) [000005] -c--------- t5 = * LEA(b+8) byref N004 ( 3, 2) [000001] !---------- t1 = LCL_VAR long V00 TypeCtx /--* t1 long [000127] ----------- t127 = * PUTARG_REG long REG rcx /--* t127 long arg0 in rcx N005 ( 17, 8) [000002] --C-G------ t2 = * CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE /--* t5 byref +--* t2 long N006 ( 24, 14) [000006] VAC-GO----- * STOREIND long ------------ BB04 [0003] [???..???) -> BB10,BB12 (cond), preds={BB07} succs={BB12,BB10} [000113] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 1, 4) [000064] H---------- t64 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t64 long N002 ( 5, 7) [000065] DA--------- * STORE_LCL_VAR long V03 tmp2 N003 ( 3, 2) [000066] ----------- t66 = LCL_VAR long V03 tmp2 /--* t66 long N006 ( 9, 10) [000070] -c--------- t70 = * LEA(b+-8) long /--* t70 long N007 ( 11, 12) [000071] nA--G------ t71 = * IND long N008 ( 1, 1) [000072] -c--------- t72 = CNS_INT long 0 /--* t71 long +--* t72 long N009 ( 13, 14) [000073] -A--G------ * CMP void N010 ( 15, 16) [000074] -A--G------ JCC void cond=UEQ ------------ BB12 [0011] [???..???) -> BB10 (always), preds={BB04} succs={BB10} [000114] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 14, 5) [000019] H-CXG------ u19 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB10 [0009] [???..???) -> BB06,BB05 (cond), preds={BB04,BB12} succs={BB05,BB06} [000115] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 3, 2) [000068] ----------- t68 = LCL_VAR long V03 tmp2 /--* t68 long N003 ( 4, 3) [000018] -c--------- t18 = * LEA(b+8) byref /--* t18 byref N004 ( 6, 5) [000017] V---GO----- t17 = * IND int N005 ( 1, 1) [000016] -c--------- t16 = CNS_INT int 2 /--* t17 int +--* t16 int N006 ( 8, 7) [000021] ----GO----- t21 = * AND int N007 ( 1, 1) [000022] -c--------- t22 = CNS_INT int 0 /--* t21 int +--* t22 int N008 ( 10, 9) [000023] ----GO-N--- * CMP void N009 ( 12, 11) [000024] ----GO----- JCC void cond=UNE ------------ BB05 [0004] [???..???) -> BB13,BB15 (cond), preds={BB10} succs={BB15,BB13} [000116] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 1, 4) [000075] H---------- t75 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t75 long N002 ( 5, 7) [000076] DA--------- * STORE_LCL_VAR long V04 tmp3 N003 ( 3, 2) [000077] ----------- t77 = LCL_VAR long V04 tmp3 /--* t77 long N006 ( 9, 10) [000081] -c--------- t81 = * LEA(b+-8) long /--* t81 long N007 ( 11, 12) [000082] nA--G------ t82 = * IND long N008 ( 1, 1) [000083] -c--------- t83 = CNS_INT long 0 /--* t82 long +--* t83 long N009 ( 13, 14) [000084] -A--G------ * CMP void N010 ( 15, 16) [000085] -A--G------ JCC void cond=UEQ ------------ BB15 [0014] [???..???) -> BB13 (always), preds={BB05} succs={BB13} [000117] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 14, 5) [000028] H-CXG------ u28 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB13 [0012] [???..???) -> BB03 (always), preds={BB05,BB15} succs={BB03} [000118] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 3, 2) [000079] ----------- t79 = LCL_VAR long V04 tmp3 /--* t79 long N003 ( 4, 3) [000027] -c--------- t27 = * LEA(b+8) byref /--* t27 byref N004 ( 6, 5) [000026] Vc--GO----- t26 = * IND long REG NA /--* t26 long calli tgt N005 ( 23, 7) [000025] --CXGO----- * CALL ind void ------------ BB06 [0005] [???..???) -> BB16,BB18 (cond), preds={BB10} succs={BB18,BB16} [000119] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 1, 4) [000086] H---------- t86 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t86 long N002 ( 5, 7) [000087] DA--------- * STORE_LCL_VAR long V05 tmp4 N003 ( 3, 2) [000088] ----------- t88 = LCL_VAR long V05 tmp4 /--* t88 long N006 ( 9, 10) [000092] -c--------- t92 = * LEA(b+-8) long /--* t92 long N007 ( 11, 12) [000093] nA--G------ t93 = * IND long N008 ( 1, 1) [000094] -c--------- t94 = CNS_INT long 0 /--* t93 long +--* t94 long N009 ( 13, 14) [000095] -A--G------ * CMP void N010 ( 15, 16) [000096] -A--G------ JCC void cond=UEQ ------------ BB18 [0017] [???..???) -> BB16 (always), preds={BB06} succs={BB16} [000120] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 14, 5) [000040] H-CXG------ u40 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB16 [0015] [???..???) -> BB19,BB21 (cond), preds={BB06,BB18} succs={BB21,BB19} [000121] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 3, 2) [000090] ----------- t90 = LCL_VAR long V05 tmp4 /--* t90 long N003 ( 4, 3) [000039] -c--------- t39 = * LEA(b+8) byref /--* t39 byref N004 ( 6, 5) [000038] V---GO----- t38 = * IND long /--* t38 long N008 ( 9, 8) [000044] -c--------- t44 = * LEA(b+6) long /--* t44 long N009 ( 9, 8) [000045] ---XGO----- t45 = * IND long /--* t45 long N010 ( 13, 11) [000097] DA-XGO----- * STORE_LCL_VAR long V06 tmp5 [000122] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 1, 4) [000099] H---------- t99 = CNS_INT(h) long 0x4000000000420458 global ptr /--* t99 long N002 ( 5, 7) [000100] DA--------- * STORE_LCL_VAR long V07 tmp6 N003 ( 3, 2) [000101] ----------- t101 = LCL_VAR long V07 tmp6 /--* t101 long N006 ( 9, 10) [000105] -c--------- t105 = * LEA(b+-8) long /--* t105 long N007 ( 11, 12) [000106] nA--G------ t106 = * IND long N008 ( 1, 1) [000107] -c--------- t107 = CNS_INT long 0 /--* t106 long +--* t107 long N009 ( 13, 14) [000108] -A--G------ * CMP void N010 ( 15, 16) [000109] -A--G------ JCC void cond=UEQ ------------ BB21 [0020] [???..???) -> BB19 (always), preds={BB16} succs={BB19} [000123] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 14, 5) [000032] H-CXG------ u32 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE ------------ BB19 [0018] [013..???) -> BB03 (always), preds={BB16,BB21} succs={BB03} [000124] ----------- IL_OFFSET void INLRT @ 0x013[E-] N001 ( 3, 2) [000098] ----------- t98 = LCL_VAR long V06 tmp5 /--* t98 long [000128] ----------- t128 = * PUTARG_REG long REG rcx N002 ( 3, 2) [000103] ----------- t103 = LCL_VAR long V07 tmp6 /--* t103 long N004 ( 4, 3) [000031] -c--------- t31 = * LEA(b+8) byref /--* t31 byref N005 ( 6, 5) [000030] V---GO----- t30 = * IND long /--* t30 long N007 ( 7, 6) [000035] -c--------- t35 = * LEA(b+-2) long /--* t35 long N008 ( 9, 8) [000036] -c-XGO----- t36 = * IND long REG NA /--* t128 long gctx in rcx +--* t36 long calli tgt N009 ( 29, 13) [000046] --CXGO----- * CALL ind void ------------ BB03 [0002] [01F..02F) (return), preds={BB13,BB19} succs={} [000125] ----------- IL_OFFSET void INLRT @ 0x01F[E-] N001 ( 1, 4) [000051] H---------- t51 = CNS_INT(h) ref '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' /--* t51 ref [000129] ----------- t129 = * PUTARG_REG ref REG rcx N002 ( 1, 4) [000052] H---------- t52 = CNS_INT(h) ref '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' /--* t52 ref [000130] ----------- t130 = * PUTARG_REG ref REG rdx /--* t129 ref arg0 in rcx +--* t130 ref arg1 in rdx N003 ( 16, 15) [000014] --CXG------ * CALL void Statics:CheckForFailure(System.String,System.String) [000126] ----------- IL_OFFSET void INLRT @ 0x02E[E-] N001 ( 0, 0) [000015] ----------- RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Calculate stack level slots *************** Finishing PHASE Calculate stack level slots [no changes] *************** Starting PHASE Linear scan register alloc Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use: {} def: {} in: {} out: {} BB02 use: {} def: {} in: {} out: {} BB09 use: {} def: {} in: {} out: {} BB07 use: {} def: {} in: {} out: {} BB04 use: {} def: {} in: {} out: {} BB12 use: {} def: {} in: {} out: {} BB10 use: {} def: {} in: {} out: {} BB05 use: {} def: {} in: {} out: {} BB15 use: {} def: {} in: {} out: {} BB13 use: {} def: {} in: {} out: {} BB06 use: {} def: {} in: {} out: {} BB18 use: {} def: {} in: {} out: {} BB16 use: {} def: {} in: {} out: {} BB21 use: {} def: {} in: {} out: {} BB19 use: {} def: {} in: {} out: {} BB03 use: {} def: {} in: {} out: {} FP callee save candidate vars: None floatVarCount = 0; hasLoops = false, singleExit = true TUPLE STYLE DUMP BEFORE LSRA Start LSRA Block Sequence: Current block: BB01 Succ block: BB02, Criteria: weight, Worklist: [BB02 ] Current block: BB02 Succ block: BB09, Criteria: weight, Worklist: [BB09 ] Succ block: BB07, Criteria: weight, Worklist: [BB07 BB09 ] Current block: BB07 Succ block: BB04, Criteria: bbNum, Worklist: [BB04 BB09 ] Current block: BB04 Succ block: BB12, Criteria: weight, Worklist: [BB09 BB12 ] Succ block: BB10, Criteria: bbNum, Worklist: [BB10 BB09 BB12 ] Current block: BB10 Succ block: BB05, Criteria: bbNum, Worklist: [BB05 BB09 BB12 ] Succ block: BB06, Criteria: bbNum, Worklist: [BB05 BB06 BB09 BB12 ] Current block: BB05 Succ block: BB15, Criteria: weight, Worklist: [BB06 BB09 BB12 BB15 ] Succ block: BB13, Criteria: bbNum, Worklist: [BB06 BB13 BB09 BB12 BB15 ] Current block: BB06 Succ block: BB18, Criteria: weight, Worklist: [BB13 BB09 BB12 BB15 BB18 ] Succ block: BB16, Criteria: bbNum, Worklist: [BB13 BB16 BB09 BB12 BB15 BB18 ] Current block: BB13 Succ block: BB03, Criteria: bbNum, Worklist: [BB03 BB16 BB09 BB12 BB15 BB18 ] Current block: BB03 Current block: BB16 Succ block: BB21, Criteria: weight, Worklist: [BB09 BB12 BB15 BB18 BB21 ] Succ block: BB19, Criteria: bbNum, Worklist: [BB19 BB09 BB12 BB15 BB18 BB21 ] Current block: BB19 Current block: BB09 Current block: BB12 Current block: BB15 Current block: BB18 Current block: BB21 Final LSRA Block Sequence: BB01 ( 1 ) BB02 ( 1 ) critical-out BB07 ( 1 ) critical-in BB04 ( 1 ) critical-out BB10 ( 1 ) critical-in BB05 ( 0.80) critical-out BB06 ( 0.20) critical-out BB13 ( 0.80) critical-in BB03 ( 1 ) BB16 ( 0.20) critical-in critical-out BB19 ( 0.20) critical-in BB09 ( 0 ) BB12 ( 0 ) BB15 ( 0 ) BB18 ( 0 ) BB21 ( 0 ) BB01 [0000] [???..???) -> BB02 (always), preds={} succs={BB02} ===== N001. NOP BB02 [0001] [???..???) -> BB07,BB09 (cond), preds={BB01} succs={BB09,BB07} ===== N000. IL_OFFSET INLRT @ 0x000[E-] N001. t53 = CNS_INT(h) 0x4000000000420458 global ptr N002. V02 MEM; t53 N003. t55 = V02 MEM N006. t59 = LEA(b+-8); t55 N007. t60 = IND ; t59 N008. CNS_INT 0 N009. CMP ; t60 N010. JCC cond=UEQ BB07 [0006] [000..01F) -> BB04 (always), preds={BB02,BB09} succs={BB04} ===== N000. IL_OFFSET INLRT @ 0x000[E-] N001. t57 = V02 MEM N003. t5 = LEA(b+8) ; t57 N004. t1 = V00 MEM N000. t127 = PUTARG_REG; t1 N005. t2 = CALL help; t127 N006. STOREIND ; t5,t2 BB04 [0003] [???..???) -> BB10,BB12 (cond), preds={BB07} succs={BB12,BB10} ===== N000. IL_OFFSET INLRT @ 0x013[E-] N001. t64 = CNS_INT(h) 0x4000000000420458 global ptr N002. V03 MEM; t64 N003. t66 = V03 MEM N006. t70 = LEA(b+-8); t66 N007. t71 = IND ; t70 N008. CNS_INT 0 N009. CMP ; t71 N010. JCC cond=UEQ BB10 [0009] [???..???) -> BB06,BB05 (cond), preds={BB04,BB12} succs={BB05,BB06} ===== N000. IL_OFFSET INLRT @ 0x013[E-] N001. t68 = V03 MEM N003. t18 = LEA(b+8) ; t68 N004. t17 = IND ; t18 N005. CNS_INT 2 N006. t21 = AND ; t17 N007. CNS_INT 0 N008. CMP ; t21 N009. JCC cond=UNE BB05 [0004] [???..???) -> BB13,BB15 (cond), preds={BB10} succs={BB15,BB13} ===== N000. IL_OFFSET INLRT @ 0x013[E-] N001. t75 = CNS_INT(h) 0x4000000000420458 global ptr N002. V04 MEM; t75 N003. t77 = V04 MEM N006. t81 = LEA(b+-8); t77 N007. t82 = IND ; t81 N008. CNS_INT 0 N009. CMP ; t82 N010. JCC cond=UEQ BB06 [0005] [???..???) -> BB16,BB18 (cond), preds={BB10} succs={BB18,BB16} ===== N000. IL_OFFSET INLRT @ 0x013[E-] N001. t86 = CNS_INT(h) 0x4000000000420458 global ptr N002. V05 MEM; t86 N003. t88 = V05 MEM N006. t92 = LEA(b+-8); t88 N007. t93 = IND ; t92 N008. CNS_INT 0 N009. CMP ; t93 N010. JCC cond=UEQ BB13 [0012] [???..???) -> BB03 (always), preds={BB05,BB15} succs={BB03} ===== N000. IL_OFFSET INLRT @ 0x013[E-] N001. t79 = V04 MEM N003. t27 = LEA(b+8) ; t79 N004. t26 = IND ; t27 N005. CALL ind ; t26 BB03 [0002] [01F..02F) (return), preds={BB13,BB19} succs={} ===== N000. IL_OFFSET INLRT @ 0x01F[E-] N001. t51 = CNS_INT(h) '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' N000. t129 = PUTARG_REG; t51 N002. t52 = CNS_INT(h) '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' N000. t130 = PUTARG_REG; t52 N003. CALL ; t129,t130 N000. IL_OFFSET INLRT @ 0x02E[E-] N001. RETURN BB16 [0015] [???..???) -> BB19,BB21 (cond), preds={BB06,BB18} succs={BB21,BB19} ===== N000. IL_OFFSET INLRT @ 0x013[E-] N001. t90 = V05 MEM N003. t39 = LEA(b+8) ; t90 N004. t38 = IND ; t39 N008. t44 = LEA(b+6) ; t38 N009. t45 = IND ; t44 N010. V06 MEM; t45 N000. IL_OFFSET INLRT @ 0x013[E-] N001. t99 = CNS_INT(h) 0x4000000000420458 global ptr N002. V07 MEM; t99 N003. t101 = V07 MEM N006. t105 = LEA(b+-8); t101 N007. t106 = IND ; t105 N008. CNS_INT 0 N009. CMP ; t106 N010. JCC cond=UEQ BB19 [0018] [013..???) -> BB03 (always), preds={BB16,BB21} succs={BB03} ===== N000. IL_OFFSET INLRT @ 0x013[E-] N001. t98 = V06 MEM N000. t128 = PUTARG_REG; t98 N002. t103 = V07 MEM N004. t31 = LEA(b+8) ; t103 N005. t30 = IND ; t31 N007. t35 = LEA(b+-2); t30 N008. t36 = IND ; t35 N009. CALL ind ; t128,t36 BB09 [0008] [???..???) -> BB07 (always), preds={BB02} succs={BB07} ===== N000. IL_OFFSET INLRT @ 0x000[E-] N001. CALL help BB12 [0011] [???..???) -> BB10 (always), preds={BB04} succs={BB10} ===== N000. IL_OFFSET INLRT @ 0x013[E-] N001. CALL help BB15 [0014] [???..???) -> BB13 (always), preds={BB05} succs={BB13} ===== N000. IL_OFFSET INLRT @ 0x013[E-] N001. CALL help BB18 [0017] [???..???) -> BB16 (always), preds={BB06} succs={BB16} ===== N000. IL_OFFSET INLRT @ 0x013[E-] N001. CALL help BB21 [0020] [???..???) -> BB19 (always), preds={BB16} succs={BB19} ===== N000. IL_OFFSET INLRT @ 0x013[E-] N001. CALL help buildIntervals second part ======== Int arg V00 in reg rcx NEW BLOCK BB01 BB01 regmask=[rax] minReg=1 wt=100.00> BB01 regmask=[rcx] minReg=1 wt=100.00> BB01 regmask=[rdi] minReg=1 wt=100.00> DefList: { } N004 ( 0, 0) [000000] ----------- * NOP void REG NA NEW BLOCK BB02 Setting BB01 as the predecessor for determining incoming variable registers of BB02 DefList: { } N008 (???,???) [000110] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA DefList: { } N010 ( 1, 4) [000053] H---------- * CNS_INT(h) long 0x4000000000420458 global ptr REG NA Interval 0: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] CNS_INT BB02 regmask=[allIntButFP] minReg=1 wt=400.00> DefList: { N010.t53. CNS_INT } N012 ( 5, 7) [000054] DA--------- * STORE_LCL_VAR long V02 tmp1 NA REG NA BB02 regmask=[allIntButFP] minReg=1 last wt=100.00> DefList: { } N014 ( 3, 2) [000055] ----------- * LCL_VAR long V02 tmp1 NA REG NA Interval 1: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] LCL_VAR BB02 regmask=[allIntButFP] minReg=1 wt=400.00> DefList: { N014.t55. LCL_VAR } N016 ( 9, 10) [000059] -c--------- * LEA(b+-8) long REG NA Contained DefList: { N014.t55. LCL_VAR } N018 ( 11, 12) [000060] nA--G------ * IND long REG NA Contained DefList: { N014.t55. LCL_VAR } N020 ( 1, 1) [000061] -c--------- * CNS_INT long 0 REG NA Contained DefList: { N014.t55. LCL_VAR } N022 ( 13, 14) [000062] -A--G------ * CMP void REG NA BB02 regmask=[allIntButFP] minReg=1 last wt=100.00> DefList: { } N024 ( 15, 16) [000063] -A--G------ * JCC void cond=UEQ REG NA NEW BLOCK BB07 Setting BB02 as the predecessor for determining incoming variable registers of BB07 DefList: { } N028 (???,???) [000112] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA DefList: { } N030 ( 3, 2) [000057] ----------- * LCL_VAR long V02 tmp1 NA REG NA Interval 2: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] LCL_VAR BB07 regmask=[allIntButFP] minReg=1 wt=400.00> DefList: { N030.t57. LCL_VAR } N032 ( 4, 3) [000005] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N030.t57. LCL_VAR } N034 ( 3, 2) [000001] !---------- * LCL_VAR long V00 TypeCtx NA REG NA Interval 3: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] LCL_VAR BB07 regmask=[allIntButFP] minReg=1 wt=400.00> DefList: { N030.t57. LCL_VAR; N034.t1. LCL_VAR } N036 (???,???) [000127] ----------- * PUTARG_REG long REG rcx BB07 regmask=[rcx] minReg=1 wt=100.00> BB07 regmask=[rcx] minReg=1 last fixed wt=100.00> Interval 4: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] BB07 regmask=[rcx] minReg=1 wt=100.00> PUTARG_REG BB07 regmask=[rcx] minReg=1 fixed wt=400.00> DefList: { N030.t57. LCL_VAR; N036.t127. PUTARG_REG } N038 ( 17, 8) [000002] --C-G------ * CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE REG NA BB07 regmask=[rcx] minReg=1 wt=100.00> BB07 regmask=[rcx] minReg=1 last fixed wt=100.00> BB07 regmask=[rax] minReg=1 wt=100.00> BB07 regmask=[rcx] minReg=1 wt=100.00> BB07 regmask=[rdx] minReg=1 wt=100.00> BB07 regmask=[r8] minReg=1 wt=100.00> BB07 regmask=[r9] minReg=1 wt=100.00> BB07 regmask=[r10] minReg=1 wt=100.00> BB07 regmask=[r11] minReg=1 wt=100.00> Interval 5: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] BB07 regmask=[rax] minReg=1 wt=100.00> CALL BB07 regmask=[rax] minReg=1 fixed wt=400.00> DefList: { N030.t57. LCL_VAR; N038.t2. CALL } N040 ( 24, 14) [000006] VAC-GO----- * STOREIND long REG NA BB07 regmask=[allIntButFP] minReg=1 last wt=100.00> BB07 regmask=[allIntButFP] minReg=1 last wt=100.00> NEW BLOCK BB04 Setting BB07 as the predecessor for determining incoming variable registers of BB04 DefList: { } N044 (???,???) [000113] ----------- * IL_OFFSET void INLRT @ 0x013[E-] REG NA DefList: { } N046 ( 1, 4) [000064] H---------- * CNS_INT(h) long 0x4000000000420458 global ptr REG NA Interval 6: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] CNS_INT BB04 regmask=[allIntButFP] minReg=1 wt=400.00> DefList: { N046.t64. CNS_INT } N048 ( 5, 7) [000065] DA--------- * STORE_LCL_VAR long V03 tmp2 NA REG NA BB04 regmask=[allIntButFP] minReg=1 last wt=100.00> DefList: { } N050 ( 3, 2) [000066] ----------- * LCL_VAR long V03 tmp2 NA REG NA Interval 7: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] LCL_VAR BB04 regmask=[allIntButFP] minReg=1 wt=400.00> DefList: { N050.t66. LCL_VAR } N052 ( 9, 10) [000070] -c--------- * LEA(b+-8) long REG NA Contained DefList: { N050.t66. LCL_VAR } N054 ( 11, 12) [000071] nA--G------ * IND long REG NA Contained DefList: { N050.t66. LCL_VAR } N056 ( 1, 1) [000072] -c--------- * CNS_INT long 0 REG NA Contained DefList: { N050.t66. LCL_VAR } N058 ( 13, 14) [000073] -A--G------ * CMP void REG NA BB04 regmask=[allIntButFP] minReg=1 last wt=100.00> DefList: { } N060 ( 15, 16) [000074] -A--G------ * JCC void cond=UEQ REG NA NEW BLOCK BB10 Setting BB04 as the predecessor for determining incoming variable registers of BB10 DefList: { } N064 (???,???) [000115] ----------- * IL_OFFSET void INLRT @ 0x013[E-] REG NA DefList: { } N066 ( 3, 2) [000068] ----------- * LCL_VAR long V03 tmp2 NA REG NA Interval 8: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] LCL_VAR BB10 regmask=[allIntButFP] minReg=1 wt=400.00> DefList: { N066.t68. LCL_VAR } N068 ( 4, 3) [000018] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N066.t68. LCL_VAR } N070 ( 6, 5) [000017] V---GO----- * IND int REG NA BB10 regmask=[allIntButFP] minReg=1 last wt=100.00> Interval 9: int RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] IND BB10 regmask=[allIntButFP] minReg=1 wt=400.00> DefList: { N070.t17. IND } N072 ( 1, 1) [000016] -c--------- * CNS_INT int 2 REG NA Contained DefList: { N070.t17. IND } N074 ( 8, 7) [000021] ----GO----- * AND int REG NA BB10 regmask=[allIntButFP] minReg=1 last wt=100.00> Interval 10: int RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] AND BB10 regmask=[allIntButFP] minReg=1 wt=400.00> Assigning related to DefList: { N074.t21. AND } N076 ( 1, 1) [000022] -c--------- * CNS_INT int 0 REG NA Contained DefList: { N074.t21. AND } N078 ( 10, 9) [000023] ----GO-N--- * CMP void REG NA BB10 regmask=[allIntButFP] minReg=1 last wt=100.00> DefList: { } N080 ( 12, 11) [000024] ----GO----- * JCC void cond=UNE REG NA NEW BLOCK BB05 Setting BB10 as the predecessor for determining incoming variable registers of BB05 DefList: { } N084 (???,???) [000116] ----------- * IL_OFFSET void INLRT @ 0x013[E-] REG NA DefList: { } N086 ( 1, 4) [000075] H---------- * CNS_INT(h) long 0x4000000000420458 global ptr REG NA Interval 11: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] CNS_INT BB05 regmask=[allIntButFP] minReg=1 wt=320.00> DefList: { N086.t75. CNS_INT } N088 ( 5, 7) [000076] DA--------- * STORE_LCL_VAR long V04 tmp3 NA REG NA BB05 regmask=[allIntButFP] minReg=1 last wt=80.00> DefList: { } N090 ( 3, 2) [000077] ----------- * LCL_VAR long V04 tmp3 NA REG NA Interval 12: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] LCL_VAR BB05 regmask=[allIntButFP] minReg=1 wt=320.00> DefList: { N090.t77. LCL_VAR } N092 ( 9, 10) [000081] -c--------- * LEA(b+-8) long REG NA Contained DefList: { N090.t77. LCL_VAR } N094 ( 11, 12) [000082] nA--G------ * IND long REG NA Contained DefList: { N090.t77. LCL_VAR } N096 ( 1, 1) [000083] -c--------- * CNS_INT long 0 REG NA Contained DefList: { N090.t77. LCL_VAR } N098 ( 13, 14) [000084] -A--G------ * CMP void REG NA BB05 regmask=[allIntButFP] minReg=1 last wt=80.00> DefList: { } N100 ( 15, 16) [000085] -A--G------ * JCC void cond=UEQ REG NA NEW BLOCK BB06 Setting BB10 as the predecessor for determining incoming variable registers of BB06 DefList: { } N104 (???,???) [000119] ----------- * IL_OFFSET void INLRT @ 0x013[E-] REG NA DefList: { } N106 ( 1, 4) [000086] H---------- * CNS_INT(h) long 0x4000000000420458 global ptr REG NA Interval 13: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] CNS_INT BB06 regmask=[allIntButFP] minReg=1 wt=80.00> DefList: { N106.t86. CNS_INT } N108 ( 5, 7) [000087] DA--------- * STORE_LCL_VAR long V05 tmp4 NA REG NA BB06 regmask=[allIntButFP] minReg=1 last wt=20.00> DefList: { } N110 ( 3, 2) [000088] ----------- * LCL_VAR long V05 tmp4 NA REG NA Interval 14: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] LCL_VAR BB06 regmask=[allIntButFP] minReg=1 wt=80.00> DefList: { N110.t88. LCL_VAR } N112 ( 9, 10) [000092] -c--------- * LEA(b+-8) long REG NA Contained DefList: { N110.t88. LCL_VAR } N114 ( 11, 12) [000093] nA--G------ * IND long REG NA Contained DefList: { N110.t88. LCL_VAR } N116 ( 1, 1) [000094] -c--------- * CNS_INT long 0 REG NA Contained DefList: { N110.t88. LCL_VAR } N118 ( 13, 14) [000095] -A--G------ * CMP void REG NA BB06 regmask=[allIntButFP] minReg=1 last wt=20.00> DefList: { } N120 ( 15, 16) [000096] -A--G------ * JCC void cond=UEQ REG NA NEW BLOCK BB13 Setting BB05 as the predecessor for determining incoming variable registers of BB13 DefList: { } N124 (???,???) [000118] ----------- * IL_OFFSET void INLRT @ 0x013[E-] REG NA DefList: { } N126 ( 3, 2) [000079] ----------- * LCL_VAR long V04 tmp3 NA REG NA Interval 15: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] LCL_VAR BB13 regmask=[allIntButFP] minReg=1 wt=320.00> DefList: { N126.t79. LCL_VAR } N128 ( 4, 3) [000027] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N126.t79. LCL_VAR } N130 ( 6, 5) [000026] Vc--GO----- * IND long REG NA Contained DefList: { N126.t79. LCL_VAR } N132 ( 23, 7) [000025] --CXGO----- * CALL ind void REG NA BB13 regmask=[allIntButFP] minReg=1 last wt=80.00> BB13 regmask=[rax] minReg=1 wt=80.00> BB13 regmask=[rcx] minReg=1 wt=80.00> BB13 regmask=[rdx] minReg=1 wt=80.00> BB13 regmask=[r8] minReg=1 wt=80.00> BB13 regmask=[r9] minReg=1 wt=80.00> BB13 regmask=[r10] minReg=1 wt=80.00> BB13 regmask=[r11] minReg=1 wt=80.00> NEW BLOCK BB03 Setting BB13 as the predecessor for determining incoming variable registers of BB03 DefList: { } N136 (???,???) [000125] ----------- * IL_OFFSET void INLRT @ 0x01F[E-] REG NA DefList: { } N138 ( 1, 4) [000051] H---------- * CNS_INT(h) ref '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' REG NA Interval 16: ref RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] CNS_INT BB03 regmask=[allIntButFP] minReg=1 wt=400.00> DefList: { N138.t51. CNS_INT } N140 (???,???) [000129] ----------- * PUTARG_REG ref REG rcx BB03 regmask=[rcx] minReg=1 wt=100.00> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00> Interval 17: ref RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] BB03 regmask=[rcx] minReg=1 wt=100.00> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=400.00> DefList: { N140.t129. PUTARG_REG } N142 ( 1, 4) [000052] H---------- * CNS_INT(h) ref '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' REG NA Interval 18: ref RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] CNS_INT BB03 regmask=[allIntButFP] minReg=1 wt=400.00> DefList: { N140.t129. PUTARG_REG; N142.t52. CNS_INT } N144 (???,???) [000130] ----------- * PUTARG_REG ref REG rdx BB03 regmask=[rdx] minReg=1 wt=100.00> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00> Interval 19: ref RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] BB03 regmask=[rdx] minReg=1 wt=100.00> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=400.00> DefList: { N140.t129. PUTARG_REG; N144.t130. PUTARG_REG } N146 ( 16, 15) [000014] --CXG------ * CALL void Statics:CheckForFailure(System.String,System.String) REG NA BB03 regmask=[rcx] minReg=1 wt=100.00> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00> BB03 regmask=[rdx] minReg=1 wt=100.00> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00> BB03 regmask=[rax] minReg=1 wt=100.00> BB03 regmask=[rcx] minReg=1 wt=100.00> BB03 regmask=[rdx] minReg=1 wt=100.00> BB03 regmask=[r8] minReg=1 wt=100.00> BB03 regmask=[r9] minReg=1 wt=100.00> BB03 regmask=[r10] minReg=1 wt=100.00> BB03 regmask=[r11] minReg=1 wt=100.00> DefList: { } N148 (???,???) [000126] ----------- * IL_OFFSET void INLRT @ 0x02E[E-] REG NA DefList: { } N150 ( 0, 0) [000015] ----------- * RETURN void REG NA NEW BLOCK BB16 Setting BB06 as the predecessor for determining incoming variable registers of BB16 DefList: { } N154 (???,???) [000121] ----------- * IL_OFFSET void INLRT @ 0x013[E-] REG NA DefList: { } N156 ( 3, 2) [000090] ----------- * LCL_VAR long V05 tmp4 NA REG NA Interval 20: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] LCL_VAR BB16 regmask=[allIntButFP] minReg=1 wt=80.00> DefList: { N156.t90. LCL_VAR } N158 ( 4, 3) [000039] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N156.t90. LCL_VAR } N160 ( 6, 5) [000038] V---GO----- * IND long REG NA BB16 regmask=[allIntButFP] minReg=1 last wt=20.00> Interval 21: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] IND BB16 regmask=[allIntButFP] minReg=1 wt=80.00> DefList: { N160.t38. IND } N162 ( 9, 8) [000044] -c--------- * LEA(b+6) long REG NA Contained DefList: { N160.t38. IND } N164 ( 9, 8) [000045] ---XGO----- * IND long REG NA BB16 regmask=[allIntButFP] minReg=1 last wt=20.00> Interval 22: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] IND BB16 regmask=[allIntButFP] minReg=1 wt=80.00> DefList: { N164.t45. IND } N166 ( 13, 11) [000097] DA-XGO----- * STORE_LCL_VAR long V06 tmp5 NA REG NA BB16 regmask=[allIntButFP] minReg=1 last wt=20.00> DefList: { } N168 (???,???) [000122] ----------- * IL_OFFSET void INLRT @ 0x013[E-] REG NA DefList: { } N170 ( 1, 4) [000099] H---------- * CNS_INT(h) long 0x4000000000420458 global ptr REG NA Interval 23: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] CNS_INT BB16 regmask=[allIntButFP] minReg=1 wt=80.00> DefList: { N170.t99. CNS_INT } N172 ( 5, 7) [000100] DA--------- * STORE_LCL_VAR long V07 tmp6 NA REG NA BB16 regmask=[allIntButFP] minReg=1 last wt=20.00> DefList: { } N174 ( 3, 2) [000101] ----------- * LCL_VAR long V07 tmp6 NA REG NA Interval 24: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] LCL_VAR BB16 regmask=[allIntButFP] minReg=1 wt=80.00> DefList: { N174.t101. LCL_VAR } N176 ( 9, 10) [000105] -c--------- * LEA(b+-8) long REG NA Contained DefList: { N174.t101. LCL_VAR } N178 ( 11, 12) [000106] nA--G------ * IND long REG NA Contained DefList: { N174.t101. LCL_VAR } N180 ( 1, 1) [000107] -c--------- * CNS_INT long 0 REG NA Contained DefList: { N174.t101. LCL_VAR } N182 ( 13, 14) [000108] -A--G------ * CMP void REG NA BB16 regmask=[allIntButFP] minReg=1 last wt=20.00> DefList: { } N184 ( 15, 16) [000109] -A--G------ * JCC void cond=UEQ REG NA NEW BLOCK BB19 Setting BB16 as the predecessor for determining incoming variable registers of BB19 DefList: { } N188 (???,???) [000124] ----------- * IL_OFFSET void INLRT @ 0x013[E-] REG NA DefList: { } N190 ( 3, 2) [000098] ----------- * LCL_VAR long V06 tmp5 NA REG NA Interval 25: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] LCL_VAR BB19 regmask=[allIntButFP] minReg=1 wt=80.00> DefList: { N190.t98. LCL_VAR } N192 (???,???) [000128] ----------- * PUTARG_REG long REG rcx BB19 regmask=[rcx] minReg=1 wt=20.00> BB19 regmask=[rcx] minReg=1 last fixed wt=20.00> Interval 26: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] BB19 regmask=[rcx] minReg=1 wt=20.00> PUTARG_REG BB19 regmask=[rcx] minReg=1 fixed wt=80.00> DefList: { N192.t128. PUTARG_REG } N194 ( 3, 2) [000103] ----------- * LCL_VAR long V07 tmp6 NA REG NA Interval 27: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] LCL_VAR BB19 regmask=[allIntButFP] minReg=1 wt=80.00> DefList: { N192.t128. PUTARG_REG; N194.t103. LCL_VAR } N196 ( 4, 3) [000031] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N192.t128. PUTARG_REG; N194.t103. LCL_VAR } N198 ( 6, 5) [000030] V---GO----- * IND long REG NA BB19 regmask=[allIntButFP] minReg=1 last wt=20.00> Interval 28: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] IND BB19 regmask=[allIntButFP] minReg=1 wt=80.00> DefList: { N192.t128. PUTARG_REG; N198.t30. IND } N200 ( 7, 6) [000035] -c--------- * LEA(b+-2) long REG NA Contained DefList: { N192.t128. PUTARG_REG; N198.t30. IND } N202 ( 9, 8) [000036] -c-XGO----- * IND long REG NA Contained DefList: { N192.t128. PUTARG_REG; N198.t30. IND } N204 ( 29, 13) [000046] --CXGO----- * CALL ind void REG NA BB19 regmask=[rcx] minReg=1 wt=20.00> BB19 regmask=[rcx] minReg=1 last fixed wt=20.00> BB19 regmask=[allIntButFP] minReg=1 last wt=20.00> BB19 regmask=[rax] minReg=1 wt=20.00> BB19 regmask=[rcx] minReg=1 wt=20.00> BB19 regmask=[rdx] minReg=1 wt=20.00> BB19 regmask=[r8] minReg=1 wt=20.00> BB19 regmask=[r9] minReg=1 wt=20.00> BB19 regmask=[r10] minReg=1 wt=20.00> BB19 regmask=[r11] minReg=1 wt=20.00> NEW BLOCK BB09 Setting BB02 as the predecessor for determining incoming variable registers of BB09 firstColdLoc = 208 DefList: { } N208 (???,???) [000111] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA DefList: { } N210 ( 14, 5) [000003] H-CXG------ * CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG NA BB09 regmask=[rax] minReg=1 wt=0.00> BB09 regmask=[rcx] minReg=1 wt=0.00> BB09 regmask=[rdx] minReg=1 wt=0.00> BB09 regmask=[r8] minReg=1 wt=0.00> BB09 regmask=[r9] minReg=1 wt=0.00> BB09 regmask=[r10] minReg=1 wt=0.00> BB09 regmask=[r11] minReg=1 wt=0.00> Interval 29: byref RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] BB09 regmask=[rax] minReg=1 wt=0.00> CALL BB09 regmask=[rax] minReg=1 fixed wt=0.00> NEW BLOCK BB12 Setting BB04 as the predecessor for determining incoming variable registers of BB12 DefList: { } N214 (???,???) [000114] ----------- * IL_OFFSET void INLRT @ 0x013[E-] REG NA DefList: { } N216 ( 14, 5) [000019] H-CXG------ * CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG NA BB12 regmask=[rax] minReg=1 wt=0.00> BB12 regmask=[rcx] minReg=1 wt=0.00> BB12 regmask=[rdx] minReg=1 wt=0.00> BB12 regmask=[r8] minReg=1 wt=0.00> BB12 regmask=[r9] minReg=1 wt=0.00> BB12 regmask=[r10] minReg=1 wt=0.00> BB12 regmask=[r11] minReg=1 wt=0.00> Interval 30: byref RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] BB12 regmask=[rax] minReg=1 wt=0.00> CALL BB12 regmask=[rax] minReg=1 fixed wt=0.00> NEW BLOCK BB15 Setting BB05 as the predecessor for determining incoming variable registers of BB15 DefList: { } N220 (???,???) [000117] ----------- * IL_OFFSET void INLRT @ 0x013[E-] REG NA DefList: { } N222 ( 14, 5) [000028] H-CXG------ * CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG NA BB15 regmask=[rax] minReg=1 wt=0.00> BB15 regmask=[rcx] minReg=1 wt=0.00> BB15 regmask=[rdx] minReg=1 wt=0.00> BB15 regmask=[r8] minReg=1 wt=0.00> BB15 regmask=[r9] minReg=1 wt=0.00> BB15 regmask=[r10] minReg=1 wt=0.00> BB15 regmask=[r11] minReg=1 wt=0.00> Interval 31: byref RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] BB15 regmask=[rax] minReg=1 wt=0.00> CALL BB15 regmask=[rax] minReg=1 fixed wt=0.00> NEW BLOCK BB18 Setting BB06 as the predecessor for determining incoming variable registers of BB18 DefList: { } N226 (???,???) [000120] ----------- * IL_OFFSET void INLRT @ 0x013[E-] REG NA DefList: { } N228 ( 14, 5) [000040] H-CXG------ * CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG NA BB18 regmask=[rax] minReg=1 wt=0.00> BB18 regmask=[rcx] minReg=1 wt=0.00> BB18 regmask=[rdx] minReg=1 wt=0.00> BB18 regmask=[r8] minReg=1 wt=0.00> BB18 regmask=[r9] minReg=1 wt=0.00> BB18 regmask=[r10] minReg=1 wt=0.00> BB18 regmask=[r11] minReg=1 wt=0.00> Interval 32: byref RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] BB18 regmask=[rax] minReg=1 wt=0.00> CALL BB18 regmask=[rax] minReg=1 fixed wt=0.00> NEW BLOCK BB21 Setting BB16 as the predecessor for determining incoming variable registers of BB21 DefList: { } N232 (???,???) [000123] ----------- * IL_OFFSET void INLRT @ 0x013[E-] REG NA DefList: { } N234 ( 14, 5) [000032] H-CXG------ * CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG NA BB21 regmask=[rax] minReg=1 wt=0.00> BB21 regmask=[rcx] minReg=1 wt=0.00> BB21 regmask=[rdx] minReg=1 wt=0.00> BB21 regmask=[r8] minReg=1 wt=0.00> BB21 regmask=[r9] minReg=1 wt=0.00> BB21 regmask=[r10] minReg=1 wt=0.00> BB21 regmask=[r11] minReg=1 wt=0.00> Interval 33: byref RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] BB21 regmask=[rax] minReg=1 wt=0.00> CALL BB21 regmask=[rax] minReg=1 fixed wt=0.00> Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: long (constant) RefPositions {#5@11 #6@12} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 1: long RefPositions {#7@15 #8@22} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 2: long RefPositions {#10@31 #27@40} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 3: long RefPositions {#11@35 #13@36} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 4: long RefPositions {#15@37 #17@38} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 5: long RefPositions {#26@39 #28@40} physReg:NA Preferences=[rax] Aversions=[allMask] Interval 6: long (constant) RefPositions {#30@47 #31@48} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 7: long RefPositions {#32@51 #33@58} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 8: long RefPositions {#35@67 #36@70} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 9: int RefPositions {#37@71 #38@74} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] RelatedInterval Interval 10: int RefPositions {#39@75 #40@78} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 11: long (constant) RefPositions {#42@87 #43@88} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 12: long RefPositions {#44@91 #45@98} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 13: long (constant) RefPositions {#47@107 #48@108} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 14: long RefPositions {#49@111 #50@118} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 15: long RefPositions {#52@127 #53@132} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 16: ref (constant) RefPositions {#62@139 #64@140} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 17: ref RefPositions {#66@141 #73@146} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 18: ref (constant) RefPositions {#67@143 #69@144} physReg:NA Preferences=[rdx] Aversions=[allMask] Interval 19: ref RefPositions {#71@145 #75@146} physReg:NA Preferences=[rdx] Aversions=[allMask] Interval 20: long RefPositions {#84@157 #85@160} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 21: long RefPositions {#86@161 #87@164} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 22: long RefPositions {#88@165 #89@166} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 23: long (constant) RefPositions {#90@171 #91@172} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 24: long RefPositions {#92@175 #93@182} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 25: long RefPositions {#95@191 #97@192} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 26: long RefPositions {#99@193 #104@204} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 27: long RefPositions {#100@195 #101@198} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 28: long RefPositions {#102@199 #105@204} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 29: byref RefPositions {#122@211} physReg:NA Preferences=[rax] Aversions=[allMask] Interval 30: byref RefPositions {#132@217} physReg:NA Preferences=[rax] Aversions=[allMask] Interval 31: byref RefPositions {#142@223} physReg:NA Preferences=[rax] Aversions=[allMask] Interval 32: byref RefPositions {#152@229} physReg:NA Preferences=[rax] Aversions=[allMask] Interval 33: byref RefPositions {#162@235} physReg:NA Preferences=[rax] Aversions=[allMask] ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ BB01 regmask=[rax] minReg=1 last wt=100.00> BB01 regmask=[rcx] minReg=1 last wt=100.00> BB01 regmask=[rdi] minReg=1 last wt=100.00> CNS_INT BB02 regmask=[allIntButFP] minReg=1 wt=400.00> BB02 regmask=[allIntButFP] minReg=1 last wt=100.00> LCL_VAR BB02 regmask=[allIntButFP] minReg=1 wt=400.00> BB02 regmask=[allIntButFP] minReg=1 last wt=100.00> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 wt=400.00> LCL_VAR BB07 regmask=[rcx] minReg=1 wt=400.00> BB07 regmask=[rcx] minReg=1 wt=100.00> BB07 regmask=[rcx] minReg=1 last fixed wt=100.00> BB07 regmask=[rcx] minReg=1 wt=100.00> PUTARG_REG BB07 regmask=[rcx] minReg=1 fixed wt=400.00> BB07 regmask=[rcx] minReg=1 wt=100.00> BB07 regmask=[rcx] minReg=1 last fixed wt=100.00> BB07 regmask=[rax] minReg=1 last wt=100.00> BB07 regmask=[rcx] minReg=1 last wt=100.00> BB07 regmask=[rdx] minReg=1 last wt=100.00> BB07 regmask=[r8] minReg=1 last wt=100.00> BB07 regmask=[r9] minReg=1 last wt=100.00> BB07 regmask=[r10] minReg=1 last wt=100.00> BB07 regmask=[r11] minReg=1 last wt=100.00> BB07 regmask=[rax] minReg=1 wt=100.00> CALL BB07 regmask=[rax] minReg=1 fixed wt=400.00> BB07 regmask=[allIntButFP] minReg=1 last wt=100.00> BB07 regmask=[allIntButFP] minReg=1 last wt=100.00> CNS_INT BB04 regmask=[allIntButFP] minReg=1 wt=400.00> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00> LCL_VAR BB04 regmask=[allIntButFP] minReg=1 wt=400.00> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00> LCL_VAR BB10 regmask=[allIntButFP] minReg=1 wt=400.00> BB10 regmask=[allIntButFP] minReg=1 last wt=100.00> IND BB10 regmask=[allIntButFP] minReg=1 wt=400.00> BB10 regmask=[allIntButFP] minReg=1 last wt=100.00> AND BB10 regmask=[allIntButFP] minReg=1 wt=400.00> BB10 regmask=[allIntButFP] minReg=1 last regOptional wt=100.00> CNS_INT BB05 regmask=[allIntButFP] minReg=1 wt=320.00> BB05 regmask=[allIntButFP] minReg=1 last wt=80.00> LCL_VAR BB05 regmask=[allIntButFP] minReg=1 wt=320.00> BB05 regmask=[allIntButFP] minReg=1 last wt=80.00> CNS_INT BB06 regmask=[allIntButFP] minReg=1 wt=80.00> BB06 regmask=[allIntButFP] minReg=1 last wt=20.00> LCL_VAR BB06 regmask=[allIntButFP] minReg=1 wt=80.00> BB06 regmask=[allIntButFP] minReg=1 last wt=20.00> LCL_VAR BB13 regmask=[allIntButFP] minReg=1 wt=320.00> BB13 regmask=[allIntButFP] minReg=1 last wt=80.00> BB13 regmask=[rax] minReg=1 last wt=80.00> BB13 regmask=[rcx] minReg=1 last wt=80.00> BB13 regmask=[rdx] minReg=1 last wt=80.00> BB13 regmask=[r8] minReg=1 last wt=80.00> BB13 regmask=[r9] minReg=1 last wt=80.00> BB13 regmask=[r10] minReg=1 last wt=80.00> BB13 regmask=[r11] minReg=1 last wt=80.00> CNS_INT BB03 regmask=[rcx] minReg=1 wt=400.00> BB03 regmask=[rcx] minReg=1 wt=100.00> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00> BB03 regmask=[rcx] minReg=1 wt=100.00> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=400.00> CNS_INT BB03 regmask=[rdx] minReg=1 wt=400.00> BB03 regmask=[rdx] minReg=1 wt=100.00> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00> BB03 regmask=[rdx] minReg=1 wt=100.00> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=400.00> BB03 regmask=[rcx] minReg=1 wt=100.00> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00> BB03 regmask=[rdx] minReg=1 wt=100.00> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00> BB03 regmask=[rax] minReg=1 last wt=100.00> BB03 regmask=[rcx] minReg=1 last wt=100.00> BB03 regmask=[rdx] minReg=1 last wt=100.00> BB03 regmask=[r8] minReg=1 last wt=100.00> BB03 regmask=[r9] minReg=1 last wt=100.00> BB03 regmask=[r10] minReg=1 last wt=100.00> BB03 regmask=[r11] minReg=1 last wt=100.00> LCL_VAR BB16 regmask=[allIntButFP] minReg=1 wt=80.00> BB16 regmask=[allIntButFP] minReg=1 last wt=20.00> IND BB16 regmask=[allIntButFP] minReg=1 wt=80.00> BB16 regmask=[allIntButFP] minReg=1 last wt=20.00> IND BB16 regmask=[allIntButFP] minReg=1 wt=80.00> BB16 regmask=[allIntButFP] minReg=1 last wt=20.00> CNS_INT BB16 regmask=[allIntButFP] minReg=1 wt=80.00> BB16 regmask=[allIntButFP] minReg=1 last wt=20.00> LCL_VAR BB16 regmask=[allIntButFP] minReg=1 wt=80.00> BB16 regmask=[allIntButFP] minReg=1 last wt=20.00> LCL_VAR BB19 regmask=[rcx] minReg=1 wt=80.00> BB19 regmask=[rcx] minReg=1 wt=20.00> BB19 regmask=[rcx] minReg=1 last fixed wt=20.00> BB19 regmask=[rcx] minReg=1 wt=20.00> PUTARG_REG BB19 regmask=[rcx] minReg=1 fixed wt=80.00> LCL_VAR BB19 regmask=[allIntButFP] minReg=1 wt=80.00> BB19 regmask=[allIntButFP] minReg=1 last wt=20.00> IND BB19 regmask=[allIntButFP] minReg=1 wt=80.00> BB19 regmask=[rcx] minReg=1 wt=20.00> BB19 regmask=[rcx] minReg=1 last fixed wt=20.00> BB19 regmask=[allIntButFP] minReg=1 last wt=20.00> BB19 regmask=[rax] minReg=1 last wt=20.00> BB19 regmask=[rcx] minReg=1 last wt=20.00> BB19 regmask=[rdx] minReg=1 last wt=20.00> BB19 regmask=[r8] minReg=1 last wt=20.00> BB19 regmask=[r9] minReg=1 last wt=20.00> BB19 regmask=[r10] minReg=1 last wt=20.00> BB19 regmask=[r11] minReg=1 last wt=20.00> BB09 regmask=[rax] minReg=1 last wt=0.00> BB09 regmask=[rcx] minReg=1 last wt=0.00> BB09 regmask=[rdx] minReg=1 last wt=0.00> BB09 regmask=[r8] minReg=1 last wt=0.00> BB09 regmask=[r9] minReg=1 last wt=0.00> BB09 regmask=[r10] minReg=1 last wt=0.00> BB09 regmask=[r11] minReg=1 last wt=0.00> BB09 regmask=[rax] minReg=1 wt=0.00> CALL BB09 regmask=[rax] minReg=1 last fixed local wt=0.00> BB12 regmask=[rax] minReg=1 last wt=0.00> BB12 regmask=[rcx] minReg=1 last wt=0.00> BB12 regmask=[rdx] minReg=1 last wt=0.00> BB12 regmask=[r8] minReg=1 last wt=0.00> BB12 regmask=[r9] minReg=1 last wt=0.00> BB12 regmask=[r10] minReg=1 last wt=0.00> BB12 regmask=[r11] minReg=1 last wt=0.00> BB12 regmask=[rax] minReg=1 wt=0.00> CALL BB12 regmask=[rax] minReg=1 last fixed local wt=0.00> BB15 regmask=[rax] minReg=1 last wt=0.00> BB15 regmask=[rcx] minReg=1 last wt=0.00> BB15 regmask=[rdx] minReg=1 last wt=0.00> BB15 regmask=[r8] minReg=1 last wt=0.00> BB15 regmask=[r9] minReg=1 last wt=0.00> BB15 regmask=[r10] minReg=1 last wt=0.00> BB15 regmask=[r11] minReg=1 last wt=0.00> BB15 regmask=[rax] minReg=1 wt=0.00> CALL BB15 regmask=[rax] minReg=1 last fixed local wt=0.00> BB18 regmask=[rax] minReg=1 last wt=0.00> BB18 regmask=[rcx] minReg=1 last wt=0.00> BB18 regmask=[rdx] minReg=1 last wt=0.00> BB18 regmask=[r8] minReg=1 last wt=0.00> BB18 regmask=[r9] minReg=1 last wt=0.00> BB18 regmask=[r10] minReg=1 last wt=0.00> BB18 regmask=[r11] minReg=1 last wt=0.00> BB18 regmask=[rax] minReg=1 wt=0.00> CALL BB18 regmask=[rax] minReg=1 last fixed local wt=0.00> BB21 regmask=[rax] minReg=1 last wt=0.00> BB21 regmask=[rcx] minReg=1 last wt=0.00> BB21 regmask=[rdx] minReg=1 last wt=0.00> BB21 regmask=[r8] minReg=1 last wt=0.00> BB21 regmask=[r9] minReg=1 last wt=0.00> BB21 regmask=[r10] minReg=1 last wt=0.00> BB21 regmask=[r11] minReg=1 last wt=0.00> BB21 regmask=[rax] minReg=1 wt=0.00> CALL BB21 regmask=[rax] minReg=1 last fixed local wt=0.00> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: BB01 [0000] [???..???) -> BB02 (always), preds={} succs={BB02} ===== N004. NOP N008. IL_OFFSET INLRT @ 0x000[E-] N010. CNS_INT(h) 0x4000000000420458 global ptr N012. V02 MEM N014. V02 MEM N016. LEA(b+-8) N018. IND N020. CNS_INT 0 N022. CMP N024. JCC cond=UEQ N028. IL_OFFSET INLRT @ 0x000[E-] N030. V02 MEM N032. LEA(b+8) N034. V00 MEM N036. PUTARG_REG N038. CALL help N040. STOREIND N044. IL_OFFSET INLRT @ 0x013[E-] N046. CNS_INT(h) 0x4000000000420458 global ptr N048. V03 MEM N050. V03 MEM N052. LEA(b+-8) N054. IND N056. CNS_INT 0 N058. CMP N060. JCC cond=UEQ N064. IL_OFFSET INLRT @ 0x013[E-] N066. V03 MEM N068. LEA(b+8) N070. IND N072. CNS_INT 2 N074. AND N076. CNS_INT 0 N078. CMP N080. JCC cond=UNE N084. IL_OFFSET INLRT @ 0x013[E-] N086. CNS_INT(h) 0x4000000000420458 global ptr N088. V04 MEM N090. V04 MEM N092. LEA(b+-8) N094. IND N096. CNS_INT 0 N098. CMP N100. JCC cond=UEQ N104. IL_OFFSET INLRT @ 0x013[E-] N106. CNS_INT(h) 0x4000000000420458 global ptr N108. V05 MEM N110. V05 MEM N112. LEA(b+-8) N114. IND N116. CNS_INT 0 N118. CMP N120. JCC cond=UEQ N124. IL_OFFSET INLRT @ 0x013[E-] N126. V04 MEM N128. LEA(b+8) N130. IND N132. CALL ind N136. IL_OFFSET INLRT @ 0x01F[E-] N138. CNS_INT(h) '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' N140. PUTARG_REG N142. CNS_INT(h) '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' N144. PUTARG_REG N146. CALL N148. IL_OFFSET INLRT @ 0x02E[E-] N150. RETURN N154. IL_OFFSET INLRT @ 0x013[E-] N156. V05 MEM N158. LEA(b+8) N160. IND N162. LEA(b+6) N164. IND N166. V06 MEM N168. IL_OFFSET INLRT @ 0x013[E-] N170. CNS_INT(h) 0x4000000000420458 global ptr N172. V07 MEM N174. V07 MEM N176. LEA(b+-8) N178. IND N180. CNS_INT 0 N182. CMP N184. JCC cond=UEQ N188. IL_OFFSET INLRT @ 0x013[E-] N190. V06 MEM N192. PUTARG_REG N194. V07 MEM N196. LEA(b+8) N198. IND N200. LEA(b+-2) N202. IND N204. CALL ind N208. IL_OFFSET INLRT @ 0x000[E-] N210. CALL help N214. IL_OFFSET INLRT @ 0x013[E-] N216. CALL help N220. IL_OFFSET INLRT @ 0x013[E-] N222. CALL help N226. IL_OFFSET INLRT @ 0x013[E-] N228. CALL help N232. IL_OFFSET INLRT @ 0x013[E-] N234. CALL help Linear scan intervals after buildIntervals: Interval 0: long (constant) RefPositions {#5@11 #6@12} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 1: long RefPositions {#7@15 #8@22} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 2: long RefPositions {#10@31 #27@40} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 3: long RefPositions {#11@35 #13@36} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 4: long RefPositions {#15@37 #17@38} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 5: long RefPositions {#26@39 #28@40} physReg:NA Preferences=[rax] Aversions=[allMask] Interval 6: long (constant) RefPositions {#30@47 #31@48} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 7: long RefPositions {#32@51 #33@58} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 8: long RefPositions {#35@67 #36@70} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 9: int RefPositions {#37@71 #38@74} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] RelatedInterval Interval 10: int RefPositions {#39@75 #40@78} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 11: long (constant) RefPositions {#42@87 #43@88} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 12: long RefPositions {#44@91 #45@98} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 13: long (constant) RefPositions {#47@107 #48@108} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 14: long RefPositions {#49@111 #50@118} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 15: long RefPositions {#52@127 #53@132} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 16: ref (constant) RefPositions {#62@139 #64@140} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 17: ref RefPositions {#66@141 #73@146} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 18: ref (constant) RefPositions {#67@143 #69@144} physReg:NA Preferences=[rdx] Aversions=[allMask] Interval 19: ref RefPositions {#71@145 #75@146} physReg:NA Preferences=[rdx] Aversions=[allMask] Interval 20: long RefPositions {#84@157 #85@160} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 21: long RefPositions {#86@161 #87@164} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 22: long RefPositions {#88@165 #89@166} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 23: long (constant) RefPositions {#90@171 #91@172} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 24: long RefPositions {#92@175 #93@182} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 25: long RefPositions {#95@191 #97@192} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 26: long RefPositions {#99@193 #104@204} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 27: long RefPositions {#100@195 #101@198} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 28: long RefPositions {#102@199 #105@204} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 29: byref RefPositions {#122@211} physReg:NA Preferences=[rax] Aversions=[allMask] Interval 30: byref RefPositions {#132@217} physReg:NA Preferences=[rax] Aversions=[allMask] Interval 31: byref RefPositions {#142@223} physReg:NA Preferences=[rax] Aversions=[allMask] Interval 32: byref RefPositions {#152@229} physReg:NA Preferences=[rax] Aversions=[allMask] Interval 33: byref RefPositions {#162@235} physReg:NA Preferences=[rax] Aversions=[allMask] *************** In LinearScan::allocateRegistersMinimal() Linear scan intervals before allocateRegistersMinimal: Interval 0: long (constant) RefPositions {#5@11 #6@12} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 1: long RefPositions {#7@15 #8@22} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 2: long RefPositions {#10@31 #27@40} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 3: long RefPositions {#11@35 #13@36} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 4: long RefPositions {#15@37 #17@38} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 5: long RefPositions {#26@39 #28@40} physReg:NA Preferences=[rax] Aversions=[allMask] Interval 6: long (constant) RefPositions {#30@47 #31@48} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 7: long RefPositions {#32@51 #33@58} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 8: long RefPositions {#35@67 #36@70} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 9: int RefPositions {#37@71 #38@74} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] RelatedInterval Interval 10: int RefPositions {#39@75 #40@78} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 11: long (constant) RefPositions {#42@87 #43@88} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 12: long RefPositions {#44@91 #45@98} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 13: long (constant) RefPositions {#47@107 #48@108} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 14: long RefPositions {#49@111 #50@118} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 15: long RefPositions {#52@127 #53@132} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 16: ref (constant) RefPositions {#62@139 #64@140} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 17: ref RefPositions {#66@141 #73@146} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 18: ref (constant) RefPositions {#67@143 #69@144} physReg:NA Preferences=[rdx] Aversions=[allMask] Interval 19: ref RefPositions {#71@145 #75@146} physReg:NA Preferences=[rdx] Aversions=[allMask] Interval 20: long RefPositions {#84@157 #85@160} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 21: long RefPositions {#86@161 #87@164} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 22: long RefPositions {#88@165 #89@166} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 23: long (constant) RefPositions {#90@171 #91@172} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 24: long RefPositions {#92@175 #93@182} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 25: long RefPositions {#95@191 #97@192} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 26: long RefPositions {#99@193 #104@204} physReg:NA Preferences=[rcx] Aversions=[allMask] Interval 27: long RefPositions {#100@195 #101@198} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 28: long RefPositions {#102@199 #105@204} physReg:NA Preferences=[allIntButFP] Aversions=[allMask] Interval 29: byref RefPositions {#122@211} physReg:NA Preferences=[rax] Aversions=[allMask] Interval 30: byref RefPositions {#132@217} physReg:NA Preferences=[rax] Aversions=[allMask] Interval 31: byref RefPositions {#142@223} physReg:NA Preferences=[rax] Aversions=[allMask] Interval 32: byref RefPositions {#152@229} physReg:NA Preferences=[rax] Aversions=[allMask] Interval 33: byref RefPositions {#162@235} physReg:NA Preferences=[rax] Aversions=[allMask] ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ BB01 regmask=[rax] minReg=1 last wt=100.00> BB01 regmask=[rcx] minReg=1 last wt=100.00> BB01 regmask=[rdi] minReg=1 last wt=100.00> CNS_INT BB02 regmask=[allIntButFP] minReg=1 wt=400.00> BB02 regmask=[allIntButFP] minReg=1 last wt=100.00> LCL_VAR BB02 regmask=[allIntButFP] minReg=1 wt=400.00> BB02 regmask=[allIntButFP] minReg=1 last wt=100.00> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 wt=400.00> LCL_VAR BB07 regmask=[rcx] minReg=1 wt=400.00> BB07 regmask=[rcx] minReg=1 wt=100.00> BB07 regmask=[rcx] minReg=1 last fixed wt=100.00> BB07 regmask=[rcx] minReg=1 wt=100.00> PUTARG_REG BB07 regmask=[rcx] minReg=1 fixed wt=400.00> BB07 regmask=[rcx] minReg=1 wt=100.00> BB07 regmask=[rcx] minReg=1 last fixed wt=100.00> BB07 regmask=[rax] minReg=1 last wt=100.00> BB07 regmask=[rcx] minReg=1 last wt=100.00> BB07 regmask=[rdx] minReg=1 last wt=100.00> BB07 regmask=[r8] minReg=1 last wt=100.00> BB07 regmask=[r9] minReg=1 last wt=100.00> BB07 regmask=[r10] minReg=1 last wt=100.00> BB07 regmask=[r11] minReg=1 last wt=100.00> BB07 regmask=[rax] minReg=1 wt=100.00> CALL BB07 regmask=[rax] minReg=1 fixed wt=400.00> BB07 regmask=[allIntButFP] minReg=1 last wt=100.00> BB07 regmask=[allIntButFP] minReg=1 last wt=100.00> CNS_INT BB04 regmask=[allIntButFP] minReg=1 wt=400.00> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00> LCL_VAR BB04 regmask=[allIntButFP] minReg=1 wt=400.00> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00> LCL_VAR BB10 regmask=[allIntButFP] minReg=1 wt=400.00> BB10 regmask=[allIntButFP] minReg=1 last wt=100.00> IND BB10 regmask=[allIntButFP] minReg=1 wt=400.00> BB10 regmask=[allIntButFP] minReg=1 last wt=100.00> AND BB10 regmask=[allIntButFP] minReg=1 wt=400.00> BB10 regmask=[allIntButFP] minReg=1 last regOptional wt=100.00> CNS_INT BB05 regmask=[allIntButFP] minReg=1 wt=320.00> BB05 regmask=[allIntButFP] minReg=1 last wt=80.00> LCL_VAR BB05 regmask=[allIntButFP] minReg=1 wt=320.00> BB05 regmask=[allIntButFP] minReg=1 last wt=80.00> CNS_INT BB06 regmask=[allIntButFP] minReg=1 wt=80.00> BB06 regmask=[allIntButFP] minReg=1 last wt=20.00> LCL_VAR BB06 regmask=[allIntButFP] minReg=1 wt=80.00> BB06 regmask=[allIntButFP] minReg=1 last wt=20.00> LCL_VAR BB13 regmask=[allIntButFP] minReg=1 wt=320.00> BB13 regmask=[allIntButFP] minReg=1 last wt=80.00> BB13 regmask=[rax] minReg=1 last wt=80.00> BB13 regmask=[rcx] minReg=1 last wt=80.00> BB13 regmask=[rdx] minReg=1 last wt=80.00> BB13 regmask=[r8] minReg=1 last wt=80.00> BB13 regmask=[r9] minReg=1 last wt=80.00> BB13 regmask=[r10] minReg=1 last wt=80.00> BB13 regmask=[r11] minReg=1 last wt=80.00> CNS_INT BB03 regmask=[rcx] minReg=1 wt=400.00> BB03 regmask=[rcx] minReg=1 wt=100.00> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00> BB03 regmask=[rcx] minReg=1 wt=100.00> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=400.00> CNS_INT BB03 regmask=[rdx] minReg=1 wt=400.00> BB03 regmask=[rdx] minReg=1 wt=100.00> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00> BB03 regmask=[rdx] minReg=1 wt=100.00> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=400.00> BB03 regmask=[rcx] minReg=1 wt=100.00> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00> BB03 regmask=[rdx] minReg=1 wt=100.00> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00> BB03 regmask=[rax] minReg=1 last wt=100.00> BB03 regmask=[rcx] minReg=1 last wt=100.00> BB03 regmask=[rdx] minReg=1 last wt=100.00> BB03 regmask=[r8] minReg=1 last wt=100.00> BB03 regmask=[r9] minReg=1 last wt=100.00> BB03 regmask=[r10] minReg=1 last wt=100.00> BB03 regmask=[r11] minReg=1 last wt=100.00> LCL_VAR BB16 regmask=[allIntButFP] minReg=1 wt=80.00> BB16 regmask=[allIntButFP] minReg=1 last wt=20.00> IND BB16 regmask=[allIntButFP] minReg=1 wt=80.00> BB16 regmask=[allIntButFP] minReg=1 last wt=20.00> IND BB16 regmask=[allIntButFP] minReg=1 wt=80.00> BB16 regmask=[allIntButFP] minReg=1 last wt=20.00> CNS_INT BB16 regmask=[allIntButFP] minReg=1 wt=80.00> BB16 regmask=[allIntButFP] minReg=1 last wt=20.00> LCL_VAR BB16 regmask=[allIntButFP] minReg=1 wt=80.00> BB16 regmask=[allIntButFP] minReg=1 last wt=20.00> LCL_VAR BB19 regmask=[rcx] minReg=1 wt=80.00> BB19 regmask=[rcx] minReg=1 wt=20.00> BB19 regmask=[rcx] minReg=1 last fixed wt=20.00> BB19 regmask=[rcx] minReg=1 wt=20.00> PUTARG_REG BB19 regmask=[rcx] minReg=1 fixed wt=80.00> LCL_VAR BB19 regmask=[allIntButFP] minReg=1 wt=80.00> BB19 regmask=[allIntButFP] minReg=1 last wt=20.00> IND BB19 regmask=[allIntButFP] minReg=1 wt=80.00> BB19 regmask=[rcx] minReg=1 wt=20.00> BB19 regmask=[rcx] minReg=1 last fixed wt=20.00> BB19 regmask=[allIntButFP] minReg=1 last wt=20.00> BB19 regmask=[rax] minReg=1 last wt=20.00> BB19 regmask=[rcx] minReg=1 last wt=20.00> BB19 regmask=[rdx] minReg=1 last wt=20.00> BB19 regmask=[r8] minReg=1 last wt=20.00> BB19 regmask=[r9] minReg=1 last wt=20.00> BB19 regmask=[r10] minReg=1 last wt=20.00> BB19 regmask=[r11] minReg=1 last wt=20.00> BB09 regmask=[rax] minReg=1 last wt=0.00> BB09 regmask=[rcx] minReg=1 last wt=0.00> BB09 regmask=[rdx] minReg=1 last wt=0.00> BB09 regmask=[r8] minReg=1 last wt=0.00> BB09 regmask=[r9] minReg=1 last wt=0.00> BB09 regmask=[r10] minReg=1 last wt=0.00> BB09 regmask=[r11] minReg=1 last wt=0.00> BB09 regmask=[rax] minReg=1 wt=0.00> CALL BB09 regmask=[rax] minReg=1 last fixed local wt=0.00> BB12 regmask=[rax] minReg=1 last wt=0.00> BB12 regmask=[rcx] minReg=1 last wt=0.00> BB12 regmask=[rdx] minReg=1 last wt=0.00> BB12 regmask=[r8] minReg=1 last wt=0.00> BB12 regmask=[r9] minReg=1 last wt=0.00> BB12 regmask=[r10] minReg=1 last wt=0.00> BB12 regmask=[r11] minReg=1 last wt=0.00> BB12 regmask=[rax] minReg=1 wt=0.00> CALL BB12 regmask=[rax] minReg=1 last fixed local wt=0.00> BB15 regmask=[rax] minReg=1 last wt=0.00> BB15 regmask=[rcx] minReg=1 last wt=0.00> BB15 regmask=[rdx] minReg=1 last wt=0.00> BB15 regmask=[r8] minReg=1 last wt=0.00> BB15 regmask=[r9] minReg=1 last wt=0.00> BB15 regmask=[r10] minReg=1 last wt=0.00> BB15 regmask=[r11] minReg=1 last wt=0.00> BB15 regmask=[rax] minReg=1 wt=0.00> CALL BB15 regmask=[rax] minReg=1 last fixed local wt=0.00> BB18 regmask=[rax] minReg=1 last wt=0.00> BB18 regmask=[rcx] minReg=1 last wt=0.00> BB18 regmask=[rdx] minReg=1 last wt=0.00> BB18 regmask=[r8] minReg=1 last wt=0.00> BB18 regmask=[r9] minReg=1 last wt=0.00> BB18 regmask=[r10] minReg=1 last wt=0.00> BB18 regmask=[r11] minReg=1 last wt=0.00> BB18 regmask=[rax] minReg=1 wt=0.00> CALL BB18 regmask=[rax] minReg=1 last fixed local wt=0.00> BB21 regmask=[rax] minReg=1 last wt=0.00> BB21 regmask=[rcx] minReg=1 last wt=0.00> BB21 regmask=[rdx] minReg=1 last wt=0.00> BB21 regmask=[r8] minReg=1 last wt=0.00> BB21 regmask=[r9] minReg=1 last wt=0.00> BB21 regmask=[r10] minReg=1 last wt=0.00> BB21 regmask=[r11] minReg=1 last wt=0.00> BB21 regmask=[rax] minReg=1 wt=0.00> CALL BB21 regmask=[rax] minReg=1 last fixed local wt=0.00> Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use, Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register, (b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc, '(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details. The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive. Columns are only printed up to the last modified register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ | | | | | | | | | | 0.#0 BB1 PredBB0 | | | | | | | | | | 3.#1 rax Kill Keep rax | | | | | | | | | | 3.#2 rcx Kill Keep rcx | | | | | | | | | | 3.#3 rdi Kill Keep rdi | | | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 6.#4 BB2 PredBB1 | | | | | | | | | | [000053] 11.#5 C0 Def ORDER(A) rax |C0 a| | | | | | | | | [000054] 12.#6 C0 Use * Keep rax |C0 a| | | | | | | | | [000055] 15.#7 I1 Def ORDER(A) rax |I1 a| | | | | | | | | [000062] 22.#8 I1 Use * Keep rax |I1 a| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 26.#9 BB7 PredBB2 | | | | | | | | | | [000057] 31.#10 I2 Def ORDER(A) rax |I2 a| | | | | | | | | [000001] 35.#11 I3 Def Alloc rcx |I2 a|I3 a| | | | | | | | [000127] 36.#12 rcx Fixd Keep rcx |I2 a|I3 a| | | | | | | | 36.#13 I3 Use * Keep rcx |I2 a|I3 a| | | | | | | | 37.#14 rcx Fixd Keep rcx |I2 a| | | | | | | | | 37.#15 I4 Def Alloc rcx |I2 a|I4 a| | | | | | | | [000002] 38.#16 rcx Fixd Keep rcx |I2 a|I4 a| | | | | | | | 38.#17 I4 Use * Keep rcx |I2 a|I4 a| | | | | | | | 39.#18 rax Kill Spill rax | | | | | | | | | | Keep rax | | | | | | | | | | 39.#19 rcx Kill Keep rcx | | | | | | | | | | 39.#20 rdx Kill Keep rdx | | | | | | | | | | 39.#21 r8 Kill Keep r8 | | | | | | | | | | 39.#22 r9 Kill Keep r9 | | | | | | | | | | 39.#23 r10 Kill Keep r10 | | | | | | | | | | 39.#24 r11 Kill Keep r11 | | | | | | | | | | 39.#25 rax Fixd Keep rax | | | | | | | | | | 39.#26 I5 Def Alloc rax |I5 a| | | | | | | | | [000006] 40.#27 I2 Use * ReLod NA |I5 a| | | | | | | | | ORDER(A) rcx |I5 a|I2 a| | | | | | | | 40.#28 I5 Use * Keep rax |I5 a|I2 a| | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 42.#29 BB4 PredBB7 | | | | | | | | | | [000064] 47.#30 C6 Def ORDER(A) rax |C6 a| | | | | | | | | [000065] 48.#31 C6 Use * Keep rax |C6 a| | | | | | | | | [000066] 51.#32 I7 Def ORDER(A) rax |I7 a| | | | | | | | | [000073] 58.#33 I7 Use * Keep rax |I7 a| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 62.#34 BB10 PredBB4 | | | | | | | | | | [000068] 67.#35 I8 Def ORDER(A) rax |I8 a| | | | | | | | | [000017] 70.#36 I8 Use * Keep rax |I8 a| | | | | | | | | 71.#37 I9 Def ORDER(A) rax |I9 a| | | | | | | | | [000021] 74.#38 I9 Use * Keep rax |I9 a| | | | | | | | | 75.#39 I10 Def ORDER(A) rax |I10a| | | | | | | | | [000023] 78.#40 I10 Use * Keep rax |I10a| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 82.#41 BB5 PredBB10 | | | | | | | | | | [000075] 87.#42 C11 Def ORDER(A) rax |C11a| | | | | | | | | [000076] 88.#43 C11 Use * Keep rax |C11a| | | | | | | | | [000077] 91.#44 I12 Def ORDER(A) rax |I12a| | | | | | | | | [000084] 98.#45 I12 Use * Keep rax |I12a| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 102.#46 BB6 PredBB10 | | | | | | | | | | [000086] 107.#47 C13 Def ORDER(A) rax |C13a| | | | | | | | | [000087] 108.#48 C13 Use * Keep rax |C13a| | | | | | | | | [000088] 111.#49 I14 Def ORDER(A) rax |I14a| | | | | | | | | [000095] 118.#50 I14 Use * Keep rax |I14a| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 122.#51 BB13 PredBB5 | | | | | | | | | | [000079] 127.#52 I15 Def ORDER(A) rax |I15a| | | | | | | | | [000025] 132.#53 I15 Use * Keep rax |I15a| | | | | | | | | 133.#54 rax Kill Keep rax | | | | | | | | | | 133.#55 rcx Kill Keep rcx | | | | | | | | | | 133.#56 rdx Kill Keep rdx | | | | | | | | | | 133.#57 r8 Kill Keep r8 | | | | | | | | | | 133.#58 r9 Kill Keep r9 | | | | | | | | | | 133.#59 r10 Kill Keep r10 | | | | | | | | | | 133.#60 r11 Kill Keep r11 | | | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 134.#61 BB3 PredBB13 | | | | | | | | | | [000051] 139.#62 C16 Def Alloc rcx | |C16a| | | | | | | | [000129] 140.#63 rcx Fixd Keep rcx | |C16a| | | | | | | | 140.#64 C16 Use * Keep rcx | |C16a| | | | | | | | 141.#65 rcx Fixd Keep rcx | | | | | | | | | | 141.#66 I17 Def Alloc rcx | |I17a| | | | | | | | [000052] 143.#67 C18 Def Alloc rdx | |I17a|C18a| | | | | | | [000130] 144.#68 rdx Fixd Keep rdx | |I17a|C18a| | | | | | | 144.#69 C18 Use * Keep rdx | |I17a|C18a| | | | | | | 145.#70 rdx Fixd Keep rdx | |I17a| | | | | | | | 145.#71 I19 Def Alloc rdx | |I17a|I19a| | | | | | | [000014] 146.#72 rcx Fixd Keep rcx | |I17a|I19a| | | | | | | 146.#73 I17 Use * Keep rcx | |I17a|I19a| | | | | | | 146.#74 rdx Fixd Keep rdx | |I17a|I19a| | | | | | | 146.#75 I19 Use * Keep rdx | |I17a|I19a| | | | | | | 147.#76 rax Kill Keep rax | | | | | | | | | | 147.#77 rcx Kill Keep rcx | | | | | | | | | | 147.#78 rdx Kill Keep rdx | | | | | | | | | | 147.#79 r8 Kill Keep r8 | | | | | | | | | | 147.#80 r9 Kill Keep r9 | | | | | | | | | | 147.#81 r10 Kill Keep r10 | | | | | | | | | | 147.#82 r11 Kill Keep r11 | | | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 152.#83 BB16 PredBB6 | | | | | | | | | | [000090] 157.#84 I20 Def ORDER(A) rax |I20a| | | | | | | | | [000038] 160.#85 I20 Use * Keep rax |I20a| | | | | | | | | 161.#86 I21 Def ORDER(A) rax |I21a| | | | | | | | | [000045] 164.#87 I21 Use * Keep rax |I21a| | | | | | | | | 165.#88 I22 Def ORDER(A) rax |I22a| | | | | | | | | [000097] 166.#89 I22 Use * Keep rax |I22a| | | | | | | | | [000099] 171.#90 C23 Def ORDER(A) rax |C23a| | | | | | | | | [000100] 172.#91 C23 Use * Keep rax |C23a| | | | | | | | | [000101] 175.#92 I24 Def ORDER(A) rax |I24a| | | | | | | | | [000108] 182.#93 I24 Use * Keep rax |I24a| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 186.#94 BB19 PredBB16 | | | | | | | | | | [000098] 191.#95 I25 Def Alloc rcx | |I25a| | | | | | | | [000128] 192.#96 rcx Fixd Keep rcx | |I25a| | | | | | | | 192.#97 I25 Use * Keep rcx | |I25a| | | | | | | | 193.#98 rcx Fixd Keep rcx | | | | | | | | | | 193.#99 I26 Def Alloc rcx | |I26a| | | | | | | | [000103] 195.#100 I27 Def ORDER(A) rax |I27a|I26a| | | | | | | | [000030] 198.#101 I27 Use * Keep rax |I27a|I26a| | | | | | | | 199.#102 I28 Def ORDER(A) rax |I28a|I26a| | | | | | | | [000046] 204.#103 rcx Fixd Keep rcx |I28a|I26a| | | | | | | | 204.#104 I26 Use * Keep rcx |I28a|I26a| | | | | | | | 204.#105 I28 Use * Keep rax |I28a|I26a| | | | | | | | 205.#106 rax Kill Keep rax | | | | | | | | | | 205.#107 rcx Kill Keep rcx | | | | | | | | | | 205.#108 rdx Kill Keep rdx | | | | | | | | | | 205.#109 r8 Kill Keep r8 | | | | | | | | | | 205.#110 r9 Kill Keep r9 | | | | | | | | | | 205.#111 r10 Kill Keep r10 | | | | | | | | | | 205.#112 r11 Kill Keep r11 | | | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 206.#113 BB9 PredBB2 | | | | | | | | | | [000003] 211.#114 rax Kill Keep rax | | | | | | | | | | 211.#115 rcx Kill Keep rcx | | | | | | | | | | 211.#116 rdx Kill Keep rdx | | | | | | | | | | 211.#117 r8 Kill Keep r8 | | | | | | | | | | 211.#118 r9 Kill Keep r9 | | | | | | | | | | 211.#119 r10 Kill Keep r10 | | | | | | | | | | 211.#120 r11 Kill Keep r11 | | | | | | | | | | 211.#121 rax Fixd Keep rax | | | | | | | | | | 211.#122 I29 Def * Alloc rax |I29a| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 212.#123 BB12 PredBB4 | | | | | | | | | | [000019] 217.#124 rax Kill Keep rax | | | | | | | | | | 217.#125 rcx Kill Keep rcx | | | | | | | | | | 217.#126 rdx Kill Keep rdx | | | | | | | | | | 217.#127 r8 Kill Keep r8 | | | | | | | | | | 217.#128 r9 Kill Keep r9 | | | | | | | | | | 217.#129 r10 Kill Keep r10 | | | | | | | | | | 217.#130 r11 Kill Keep r11 | | | | | | | | | | 217.#131 rax Fixd Keep rax | | | | | | | | | | 217.#132 I30 Def * Alloc rax |I30a| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 218.#133 BB15 PredBB5 | | | | | | | | | | [000028] 223.#134 rax Kill Keep rax | | | | | | | | | | 223.#135 rcx Kill Keep rcx | | | | | | | | | | 223.#136 rdx Kill Keep rdx | | | | | | | | | | 223.#137 r8 Kill Keep r8 | | | | | | | | | | 223.#138 r9 Kill Keep r9 | | | | | | | | | | 223.#139 r10 Kill Keep r10 | | | | | | | | | | 223.#140 r11 Kill Keep r11 | | | | | | | | | | 223.#141 rax Fixd Keep rax | | | | | | | | | | 223.#142 I31 Def * Alloc rax |I31a| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 224.#143 BB18 PredBB6 | | | | | | | | | | [000040] 229.#144 rax Kill Keep rax | | | | | | | | | | 229.#145 rcx Kill Keep rcx | | | | | | | | | | 229.#146 rdx Kill Keep rdx | | | | | | | | | | 229.#147 r8 Kill Keep r8 | | | | | | | | | | 229.#148 r9 Kill Keep r9 | | | | | | | | | | 229.#149 r10 Kill Keep r10 | | | | | | | | | | 229.#150 r11 Kill Keep r11 | | | | | | | | | | 229.#151 rax Fixd Keep rax | | | | | | | | | | 229.#152 I32 Def * Alloc rax |I32a| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 230.#153 BB21 PredBB16 | | | | | | | | | | [000032] 235.#154 rax Kill Keep rax | | | | | | | | | | 235.#155 rcx Kill Keep rcx | | | | | | | | | | 235.#156 rdx Kill Keep rdx | | | | | | | | | | 235.#157 r8 Kill Keep r8 | | | | | | | | | | 235.#158 r9 Kill Keep r9 | | | | | | | | | | 235.#159 r10 Kill Keep r10 | | | | | | | | | | 235.#160 r11 Kill Keep r11 | | | | | | | | | | 235.#161 rax Fixd Keep rax | | | | | | | | | | 235.#162 I33 Def * Alloc rax |I33a| | | | | | | | | 236.#163 END | | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ BB01 regmask=[rax] minReg=1 last wt=100.00> BB01 regmask=[rcx] minReg=1 last wt=100.00> BB01 regmask=[rdi] minReg=1 last wt=100.00> CNS_INT BB02 regmask=[rax] minReg=1 wt=400.00> BB02 regmask=[rax] minReg=1 last wt=100.00> LCL_VAR BB02 regmask=[rax] minReg=1 wt=400.00> BB02 regmask=[rax] minReg=1 last wt=100.00> LCL_VAR BB07 regmask=[rax] minReg=1 spillAfter singleDefSpill wt=400.00> LCL_VAR BB07 regmask=[rcx] minReg=1 wt=400.00> BB07 regmask=[rcx] minReg=1 wt=100.00> BB07 regmask=[rcx] minReg=1 last fixed wt=100.00> BB07 regmask=[rcx] minReg=1 wt=100.00> PUTARG_REG BB07 regmask=[rcx] minReg=1 fixed wt=400.00> BB07 regmask=[rcx] minReg=1 wt=100.00> BB07 regmask=[rcx] minReg=1 last fixed wt=100.00> BB07 regmask=[rax] minReg=1 last wt=100.00> BB07 regmask=[rcx] minReg=1 last wt=100.00> BB07 regmask=[rdx] minReg=1 last wt=100.00> BB07 regmask=[r8] minReg=1 last wt=100.00> BB07 regmask=[r9] minReg=1 last wt=100.00> BB07 regmask=[r10] minReg=1 last wt=100.00> BB07 regmask=[r11] minReg=1 last wt=100.00> BB07 regmask=[rax] minReg=1 wt=100.00> CALL BB07 regmask=[rax] minReg=1 fixed wt=400.00> BB07 regmask=[rcx] minReg=1 last reload wt=100.00> BB07 regmask=[rax] minReg=1 last wt=100.00> CNS_INT BB04 regmask=[rax] minReg=1 wt=400.00> BB04 regmask=[rax] minReg=1 last wt=100.00> LCL_VAR BB04 regmask=[rax] minReg=1 wt=400.00> BB04 regmask=[rax] minReg=1 last wt=100.00> LCL_VAR BB10 regmask=[rax] minReg=1 wt=400.00> BB10 regmask=[rax] minReg=1 last wt=100.00> IND BB10 regmask=[rax] minReg=1 wt=400.00> BB10 regmask=[rax] minReg=1 last wt=100.00> AND BB10 regmask=[rax] minReg=1 wt=400.00> BB10 regmask=[rax] minReg=1 last regOptional wt=100.00> CNS_INT BB05 regmask=[rax] minReg=1 wt=320.00> BB05 regmask=[rax] minReg=1 last wt=80.00> LCL_VAR BB05 regmask=[rax] minReg=1 wt=320.00> BB05 regmask=[rax] minReg=1 last wt=80.00> CNS_INT BB06 regmask=[rax] minReg=1 wt=80.00> BB06 regmask=[rax] minReg=1 last wt=20.00> LCL_VAR BB06 regmask=[rax] minReg=1 wt=80.00> BB06 regmask=[rax] minReg=1 last wt=20.00> LCL_VAR BB13 regmask=[rax] minReg=1 wt=320.00> BB13 regmask=[rax] minReg=1 last wt=80.00> BB13 regmask=[rax] minReg=1 last wt=80.00> BB13 regmask=[rcx] minReg=1 last wt=80.00> BB13 regmask=[rdx] minReg=1 last wt=80.00> BB13 regmask=[r8] minReg=1 last wt=80.00> BB13 regmask=[r9] minReg=1 last wt=80.00> BB13 regmask=[r10] minReg=1 last wt=80.00> BB13 regmask=[r11] minReg=1 last wt=80.00> CNS_INT BB03 regmask=[rcx] minReg=1 wt=400.00> BB03 regmask=[rcx] minReg=1 wt=100.00> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00> BB03 regmask=[rcx] minReg=1 wt=100.00> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=400.00> CNS_INT BB03 regmask=[rdx] minReg=1 wt=400.00> BB03 regmask=[rdx] minReg=1 wt=100.00> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00> BB03 regmask=[rdx] minReg=1 wt=100.00> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=400.00> BB03 regmask=[rcx] minReg=1 wt=100.00> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00> BB03 regmask=[rdx] minReg=1 wt=100.00> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00> BB03 regmask=[rax] minReg=1 last wt=100.00> BB03 regmask=[rcx] minReg=1 last wt=100.00> BB03 regmask=[rdx] minReg=1 last wt=100.00> BB03 regmask=[r8] minReg=1 last wt=100.00> BB03 regmask=[r9] minReg=1 last wt=100.00> BB03 regmask=[r10] minReg=1 last wt=100.00> BB03 regmask=[r11] minReg=1 last wt=100.00> LCL_VAR BB16 regmask=[rax] minReg=1 wt=80.00> BB16 regmask=[rax] minReg=1 last wt=20.00> IND BB16 regmask=[rax] minReg=1 wt=80.00> BB16 regmask=[rax] minReg=1 last wt=20.00> IND BB16 regmask=[rax] minReg=1 wt=80.00> BB16 regmask=[rax] minReg=1 last wt=20.00> CNS_INT BB16 regmask=[rax] minReg=1 wt=80.00> BB16 regmask=[rax] minReg=1 last wt=20.00> LCL_VAR BB16 regmask=[rax] minReg=1 wt=80.00> BB16 regmask=[rax] minReg=1 last wt=20.00> LCL_VAR BB19 regmask=[rcx] minReg=1 wt=80.00> BB19 regmask=[rcx] minReg=1 wt=20.00> BB19 regmask=[rcx] minReg=1 last fixed wt=20.00> BB19 regmask=[rcx] minReg=1 wt=20.00> PUTARG_REG BB19 regmask=[rcx] minReg=1 fixed wt=80.00> LCL_VAR BB19 regmask=[rax] minReg=1 wt=80.00> BB19 regmask=[rax] minReg=1 last wt=20.00> IND BB19 regmask=[rax] minReg=1 wt=80.00> BB19 regmask=[rcx] minReg=1 wt=20.00> BB19 regmask=[rcx] minReg=1 last fixed wt=20.00> BB19 regmask=[rax] minReg=1 last wt=20.00> BB19 regmask=[rax] minReg=1 last wt=20.00> BB19 regmask=[rcx] minReg=1 last wt=20.00> BB19 regmask=[rdx] minReg=1 last wt=20.00> BB19 regmask=[r8] minReg=1 last wt=20.00> BB19 regmask=[r9] minReg=1 last wt=20.00> BB19 regmask=[r10] minReg=1 last wt=20.00> BB19 regmask=[r11] minReg=1 last wt=20.00> BB09 regmask=[rax] minReg=1 last wt=0.00> BB09 regmask=[rcx] minReg=1 last wt=0.00> BB09 regmask=[rdx] minReg=1 last wt=0.00> BB09 regmask=[r8] minReg=1 last wt=0.00> BB09 regmask=[r9] minReg=1 last wt=0.00> BB09 regmask=[r10] minReg=1 last wt=0.00> BB09 regmask=[r11] minReg=1 last wt=0.00> BB09 regmask=[rax] minReg=1 wt=0.00> CALL BB09 regmask=[rax] minReg=1 last fixed local wt=0.00> BB12 regmask=[rax] minReg=1 last wt=0.00> BB12 regmask=[rcx] minReg=1 last wt=0.00> BB12 regmask=[rdx] minReg=1 last wt=0.00> BB12 regmask=[r8] minReg=1 last wt=0.00> BB12 regmask=[r9] minReg=1 last wt=0.00> BB12 regmask=[r10] minReg=1 last wt=0.00> BB12 regmask=[r11] minReg=1 last wt=0.00> BB12 regmask=[rax] minReg=1 wt=0.00> CALL BB12 regmask=[rax] minReg=1 last fixed local wt=0.00> BB15 regmask=[rax] minReg=1 last wt=0.00> BB15 regmask=[rcx] minReg=1 last wt=0.00> BB15 regmask=[rdx] minReg=1 last wt=0.00> BB15 regmask=[r8] minReg=1 last wt=0.00> BB15 regmask=[r9] minReg=1 last wt=0.00> BB15 regmask=[r10] minReg=1 last wt=0.00> BB15 regmask=[r11] minReg=1 last wt=0.00> BB15 regmask=[rax] minReg=1 wt=0.00> CALL BB15 regmask=[rax] minReg=1 last fixed local wt=0.00> BB18 regmask=[rax] minReg=1 last wt=0.00> BB18 regmask=[rcx] minReg=1 last wt=0.00> BB18 regmask=[rdx] minReg=1 last wt=0.00> BB18 regmask=[r8] minReg=1 last wt=0.00> BB18 regmask=[r9] minReg=1 last wt=0.00> BB18 regmask=[r10] minReg=1 last wt=0.00> BB18 regmask=[r11] minReg=1 last wt=0.00> BB18 regmask=[rax] minReg=1 wt=0.00> CALL BB18 regmask=[rax] minReg=1 last fixed local wt=0.00> BB21 regmask=[rax] minReg=1 last wt=0.00> BB21 regmask=[rcx] minReg=1 last wt=0.00> BB21 regmask=[rdx] minReg=1 last wt=0.00> BB21 regmask=[r8] minReg=1 last wt=0.00> BB21 regmask=[r9] minReg=1 last wt=0.00> BB21 regmask=[r10] minReg=1 last wt=0.00> BB21 regmask=[r11] minReg=1 last wt=0.00> BB21 regmask=[rax] minReg=1 wt=0.00> CALL BB21 regmask=[rax] minReg=1 last fixed local wt=0.00> Active intervals at end of allocation: Max spill for long is 1 Max spill for long is 1 Trees after linear scan register allocator (LSRA) ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i LIR keep internal q BB02 [0001] 1 BB01 1 [???..???)-> BB07,BB09 ( cond ) i LIR hascall BB09 [0008] 1 BB02 0 [???..???)-> BB07 (always) LIR rare internal q BB07 [0006] 2 BB02,BB09 1 [000..01F)-> BB04 (always) i LIR hascall q BB04 [0003] 1 BB07 1 [???..???)-> BB10,BB12 ( cond ) i LIR internal hascall BB12 [0011] 1 BB04 0 [???..???)-> BB10 (always) LIR rare internal q BB10 [0009] 2 BB04,BB12 1 [???..???)-> BB06,BB05 ( cond ) i LIR internal hascall q BB05 [0004] 1 BB10 0.80 [???..???)-> BB13,BB15 ( cond ) i LIR internal hascall gcsafe BB15 [0014] 1 BB05 0 [???..???)-> BB13 (always) LIR rare internal q BB13 [0012] 2 BB05,BB15 0.80 [???..???)-> BB03 (always) i LIR internal hascall gcsafe BB06 [0005] 1 BB10 0.20 [???..???)-> BB16,BB18 ( cond ) i LIR internal hascall gcsafe BB18 [0017] 1 BB06 0 [???..???)-> BB16 (always) LIR rare internal q BB16 [0015] 2 BB06,BB18 0.20 [???..???)-> BB19,BB21 ( cond ) i LIR internal hascall gcsafe BB21 [0020] 1 BB16 0 [???..???)-> BB19 (always) LIR rare internal q BB19 [0018] 2 BB16,BB21 0.20 [013..???)-> BB03 (always) i LIR internal hascall gcsafe q BB03 [0002] 2 BB13,BB19 1 [01F..02F) (return) i LIR internal hascall gcsafe ---------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [???..???) -> BB02 (always), preds={} succs={BB02} N004 ( 0, 0) [000000] ----------- NOP void REG NA ------------ BB02 [0001] [???..???) -> BB07,BB09 (cond), preds={BB01} succs={BB09,BB07} N008 (???,???) [000110] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA N010 ( 1, 4) [000053] H---------- t53 = CNS_INT(h) long 0x4000000000420458 global ptr REG rax /--* t53 long N012 ( 5, 7) [000054] DA--------- * STORE_LCL_VAR long V02 tmp1 NA REG NA N014 ( 3, 2) [000055] ----------- t55 = LCL_VAR long V02 tmp1 rax REG rax /--* t55 long N016 ( 9, 10) [000059] -c--------- t59 = * LEA(b+-8) long REG NA /--* t59 long N018 ( 11, 12) [000060] nA--G------ t60 = * IND long REG NA N020 ( 1, 1) [000061] -c--------- t61 = CNS_INT long 0 REG NA /--* t60 long +--* t61 long N022 ( 13, 14) [000062] -A--G------ * CMP void REG NA N024 ( 15, 16) [000063] -A--G------ JCC void cond=UEQ REG NA ------------ BB09 [0008] [???..???) -> BB07 (always), preds={BB02} succs={BB07} N208 (???,???) [000111] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA N210 ( 14, 5) [000003] H-CXG------ u3 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG rax ------------ BB07 [0006] [000..01F) -> BB04 (always), preds={BB02,BB09} succs={BB04} N028 (???,???) [000112] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA N030 ( 3, 2) [000057] ----------Z t57 = LCL_VAR long V02 tmp1 rax REG rax /--* t57 long [000131] ----------- t131 = * RELOAD long REG rcx /--* t131 long N032 ( 4, 3) [000005] -c--------- t5 = * LEA(b+8) byref REG NA N034 ( 3, 2) [000001] !---------- t1 = LCL_VAR long V00 TypeCtx rcx REG rcx /--* t1 long N036 (???,???) [000127] ----------- t127 = * PUTARG_REG long REG rcx /--* t127 long arg0 in rcx N038 ( 17, 8) [000002] --C-G------ t2 = * CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE REG rax /--* t5 byref +--* t2 long N040 ( 24, 14) [000006] VAC-GO----- * STOREIND long REG NA ------------ BB04 [0003] [???..???) -> BB10,BB12 (cond), preds={BB07} succs={BB12,BB10} N044 (???,???) [000113] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N046 ( 1, 4) [000064] H---------- t64 = CNS_INT(h) long 0x4000000000420458 global ptr REG rax /--* t64 long N048 ( 5, 7) [000065] DA--------- * STORE_LCL_VAR long V03 tmp2 NA REG NA N050 ( 3, 2) [000066] ----------- t66 = LCL_VAR long V03 tmp2 rax REG rax /--* t66 long N052 ( 9, 10) [000070] -c--------- t70 = * LEA(b+-8) long REG NA /--* t70 long N054 ( 11, 12) [000071] nA--G------ t71 = * IND long REG NA N056 ( 1, 1) [000072] -c--------- t72 = CNS_INT long 0 REG NA /--* t71 long +--* t72 long N058 ( 13, 14) [000073] -A--G------ * CMP void REG NA N060 ( 15, 16) [000074] -A--G------ JCC void cond=UEQ REG NA ------------ BB12 [0011] [???..???) -> BB10 (always), preds={BB04} succs={BB10} N214 (???,???) [000114] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N216 ( 14, 5) [000019] H-CXG------ u19 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG rax ------------ BB10 [0009] [???..???) -> BB06,BB05 (cond), preds={BB04,BB12} succs={BB05,BB06} N064 (???,???) [000115] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N066 ( 3, 2) [000068] ----------- t68 = LCL_VAR long V03 tmp2 rax REG rax /--* t68 long N068 ( 4, 3) [000018] -c--------- t18 = * LEA(b+8) byref REG NA /--* t18 byref N070 ( 6, 5) [000017] V---GO----- t17 = * IND int REG rax N072 ( 1, 1) [000016] -c--------- t16 = CNS_INT int 2 REG NA /--* t17 int +--* t16 int N074 ( 8, 7) [000021] ----GO----- t21 = * AND int REG rax N076 ( 1, 1) [000022] -c--------- t22 = CNS_INT int 0 REG NA /--* t21 int +--* t22 int N078 ( 10, 9) [000023] ----GO-N--- * CMP void REG NA N080 ( 12, 11) [000024] ----GO----- JCC void cond=UNE REG NA ------------ BB05 [0004] [???..???) -> BB13,BB15 (cond), preds={BB10} succs={BB15,BB13} N084 (???,???) [000116] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N086 ( 1, 4) [000075] H---------- t75 = CNS_INT(h) long 0x4000000000420458 global ptr REG rax /--* t75 long N088 ( 5, 7) [000076] DA--------- * STORE_LCL_VAR long V04 tmp3 NA REG NA N090 ( 3, 2) [000077] ----------- t77 = LCL_VAR long V04 tmp3 rax REG rax /--* t77 long N092 ( 9, 10) [000081] -c--------- t81 = * LEA(b+-8) long REG NA /--* t81 long N094 ( 11, 12) [000082] nA--G------ t82 = * IND long REG NA N096 ( 1, 1) [000083] -c--------- t83 = CNS_INT long 0 REG NA /--* t82 long +--* t83 long N098 ( 13, 14) [000084] -A--G------ * CMP void REG NA N100 ( 15, 16) [000085] -A--G------ JCC void cond=UEQ REG NA ------------ BB15 [0014] [???..???) -> BB13 (always), preds={BB05} succs={BB13} N220 (???,???) [000117] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N222 ( 14, 5) [000028] H-CXG------ u28 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG rax ------------ BB13 [0012] [???..???) -> BB03 (always), preds={BB05,BB15} succs={BB03} N124 (???,???) [000118] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N126 ( 3, 2) [000079] ----------- t79 = LCL_VAR long V04 tmp3 rax REG rax /--* t79 long N128 ( 4, 3) [000027] -c--------- t27 = * LEA(b+8) byref REG NA /--* t27 byref N130 ( 6, 5) [000026] Vc--GO----- t26 = * IND long REG NA /--* t26 long calli tgt N132 ( 23, 7) [000025] --CXGO----- * CALL ind void REG NA ------------ BB06 [0005] [???..???) -> BB16,BB18 (cond), preds={BB10} succs={BB18,BB16} N104 (???,???) [000119] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N106 ( 1, 4) [000086] H---------- t86 = CNS_INT(h) long 0x4000000000420458 global ptr REG rax /--* t86 long N108 ( 5, 7) [000087] DA--------- * STORE_LCL_VAR long V05 tmp4 NA REG NA N110 ( 3, 2) [000088] ----------- t88 = LCL_VAR long V05 tmp4 rax REG rax /--* t88 long N112 ( 9, 10) [000092] -c--------- t92 = * LEA(b+-8) long REG NA /--* t92 long N114 ( 11, 12) [000093] nA--G------ t93 = * IND long REG NA N116 ( 1, 1) [000094] -c--------- t94 = CNS_INT long 0 REG NA /--* t93 long +--* t94 long N118 ( 13, 14) [000095] -A--G------ * CMP void REG NA N120 ( 15, 16) [000096] -A--G------ JCC void cond=UEQ REG NA ------------ BB18 [0017] [???..???) -> BB16 (always), preds={BB06} succs={BB16} N226 (???,???) [000120] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N228 ( 14, 5) [000040] H-CXG------ u40 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG rax ------------ BB16 [0015] [???..???) -> BB19,BB21 (cond), preds={BB06,BB18} succs={BB21,BB19} N154 (???,???) [000121] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N156 ( 3, 2) [000090] ----------- t90 = LCL_VAR long V05 tmp4 rax REG rax /--* t90 long N158 ( 4, 3) [000039] -c--------- t39 = * LEA(b+8) byref REG NA /--* t39 byref N160 ( 6, 5) [000038] V---GO----- t38 = * IND long REG rax /--* t38 long N162 ( 9, 8) [000044] -c--------- t44 = * LEA(b+6) long REG NA /--* t44 long N164 ( 9, 8) [000045] ---XGO----- t45 = * IND long REG rax /--* t45 long N166 ( 13, 11) [000097] DA-XGO----- * STORE_LCL_VAR long V06 tmp5 NA REG NA N168 (???,???) [000122] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N170 ( 1, 4) [000099] H---------- t99 = CNS_INT(h) long 0x4000000000420458 global ptr REG rax /--* t99 long N172 ( 5, 7) [000100] DA--------- * STORE_LCL_VAR long V07 tmp6 NA REG NA N174 ( 3, 2) [000101] ----------- t101 = LCL_VAR long V07 tmp6 rax REG rax /--* t101 long N176 ( 9, 10) [000105] -c--------- t105 = * LEA(b+-8) long REG NA /--* t105 long N178 ( 11, 12) [000106] nA--G------ t106 = * IND long REG NA N180 ( 1, 1) [000107] -c--------- t107 = CNS_INT long 0 REG NA /--* t106 long +--* t107 long N182 ( 13, 14) [000108] -A--G------ * CMP void REG NA N184 ( 15, 16) [000109] -A--G------ JCC void cond=UEQ REG NA ------------ BB21 [0020] [???..???) -> BB19 (always), preds={BB16} succs={BB19} N232 (???,???) [000123] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N234 ( 14, 5) [000032] H-CXG------ u32 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG rax ------------ BB19 [0018] [013..???) -> BB03 (always), preds={BB16,BB21} succs={BB03} N188 (???,???) [000124] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N190 ( 3, 2) [000098] ----------- t98 = LCL_VAR long V06 tmp5 rcx REG rcx /--* t98 long N192 (???,???) [000128] ----------- t128 = * PUTARG_REG long REG rcx N194 ( 3, 2) [000103] ----------- t103 = LCL_VAR long V07 tmp6 rax REG rax /--* t103 long N196 ( 4, 3) [000031] -c--------- t31 = * LEA(b+8) byref REG NA /--* t31 byref N198 ( 6, 5) [000030] V---GO----- t30 = * IND long REG rax /--* t30 long N200 ( 7, 6) [000035] -c--------- t35 = * LEA(b+-2) long REG NA /--* t35 long N202 ( 9, 8) [000036] -c-XGO----- t36 = * IND long REG NA /--* t128 long gctx in rcx +--* t36 long calli tgt N204 ( 29, 13) [000046] --CXGO----- * CALL ind void REG NA ------------ BB03 [0002] [01F..02F) (return), preds={BB13,BB19} succs={} N136 (???,???) [000125] ----------- IL_OFFSET void INLRT @ 0x01F[E-] REG NA N138 ( 1, 4) [000051] H---------- t51 = CNS_INT(h) ref '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' REG rcx /--* t51 ref N140 (???,???) [000129] ----------- t129 = * PUTARG_REG ref REG rcx N142 ( 1, 4) [000052] H---------- t52 = CNS_INT(h) ref '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' REG rdx /--* t52 ref N144 (???,???) [000130] ----------- t130 = * PUTARG_REG ref REG rdx /--* t129 ref arg0 in rcx +--* t130 ref arg1 in rdx N146 ( 16, 15) [000014] --CXG------ * CALL void Statics:CheckForFailure(System.String,System.String) REG NA N148 (???,???) [000126] ----------- IL_OFFSET void INLRT @ 0x02E[E-] REG NA N150 ( 0, 0) [000015] ----------- RETURN void REG NA ------------------------------------------------------------------------------------------------------------------- Final allocation --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 0.#0 BB1 PredBB0 | | | | | | | | | | 3.#1 rax Kill Keep rax | | | | | | | | | | 3.#2 rcx Kill Keep rcx | | | | | | | | | | 3.#3 rdi Kill Keep rdi | | | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 6.#4 BB2 PredBB1 | | | | | | | | | | [000053] 11.#5 C0 Def Alloc rax |C0 a| | | | | | | | | [000054] 12.#6 C0 Use * Keep rax |C0 i| | | | | | | | | [000055] 15.#7 I1 Def Alloc rax |I1 a| | | | | | | | | [000062] 22.#8 I1 Use * Keep rax |I1 i| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 26.#9 BB7 PredBB2 | | | | | | | | | | [000057] 31.#10 I2 Def Alloc rax | | | | | | | | | | Spill rax | | | | | | | | | | [000001] 35.#11 I3 Def Alloc rcx | |I3 a| | | | | | | | [000127] 36.#12 rcx Fixd Keep rcx | |I3 a| | | | | | | | 36.#13 I3 Use * Keep rcx | |I3 i| | | | | | | | 37.#14 rcx Fixd Keep rcx | | | | | | | | | | 37.#15 I4 Def Alloc rcx | |I4 a| | | | | | | | [000002] 38.#16 rcx Fixd Keep rcx | |I4 a| | | | | | | | 38.#17 I4 Use * Keep rcx | |I4 i| | | | | | | | 39.#18 rax Kill Keep rax | | | | | | | | | | 39.#19 rcx Kill Keep rcx | | | | | | | | | | 39.#20 rdx Kill Keep rdx | | | | | | | | | | 39.#21 r8 Kill Keep r8 | | | | | | | | | | 39.#22 r9 Kill Keep r9 | | | | | | | | | | 39.#23 r10 Kill Keep r10 | | | | | | | | | | 39.#24 r11 Kill Keep r11 | | | | | | | | | | 39.#25 rax Fixd Keep rax | | | | | | | | | | 39.#26 I5 Def Alloc rax |I5 a| | | | | | | | | [000006] 40.#27 I2 Use * ReLod rcx |I5 a|I2 a| | | | | | | | Keep rcx |I5 a|I2 i| | | | | | | | 40.#28 I5 Use * Keep rax |I5 i| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 42.#29 BB4 PredBB7 | | | | | | | | | | [000064] 47.#30 C6 Def Alloc rax |C6 a| | | | | | | | | [000065] 48.#31 C6 Use * Keep rax |C6 i| | | | | | | | | [000066] 51.#32 I7 Def Alloc rax |I7 a| | | | | | | | | [000073] 58.#33 I7 Use * Keep rax |I7 i| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 62.#34 BB10 PredBB4 | | | | | | | | | | [000068] 67.#35 I8 Def Alloc rax |I8 a| | | | | | | | | [000017] 70.#36 I8 Use * Keep rax |I8 i| | | | | | | | | 71.#37 I9 Def Alloc rax |I9 a| | | | | | | | | [000021] 74.#38 I9 Use * Keep rax |I9 i| | | | | | | | | 75.#39 I10 Def Alloc rax |I10a| | | | | | | | | [000023] 78.#40 I10 Use * Keep rax |I10i| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 82.#41 BB5 PredBB10 | | | | | | | | | | [000075] 87.#42 C11 Def Alloc rax |C11a| | | | | | | | | [000076] 88.#43 C11 Use * Keep rax |C11i| | | | | | | | | [000077] 91.#44 I12 Def Alloc rax |I12a| | | | | | | | | [000084] 98.#45 I12 Use * Keep rax |I12i| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 102.#46 BB6 PredBB10 | | | | | | | | | | [000086] 107.#47 C13 Def Alloc rax |C13a| | | | | | | | | [000087] 108.#48 C13 Use * Keep rax |C13i| | | | | | | | | [000088] 111.#49 I14 Def Alloc rax |I14a| | | | | | | | | [000095] 118.#50 I14 Use * Keep rax |I14i| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 122.#51 BB13 PredBB5 | | | | | | | | | | [000079] 127.#52 I15 Def Alloc rax |I15a| | | | | | | | | [000025] 132.#53 I15 Use * Keep rax |I15i| | | | | | | | | 133.#54 rax Kill Keep rax | | | | | | | | | | 133.#55 rcx Kill Keep rcx | | | | | | | | | | 133.#56 rdx Kill Keep rdx | | | | | | | | | | 133.#57 r8 Kill Keep r8 | | | | | | | | | | 133.#58 r9 Kill Keep r9 | | | | | | | | | | 133.#59 r10 Kill Keep r10 | | | | | | | | | | 133.#60 r11 Kill Keep r11 | | | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 134.#61 BB3 PredBB13 | | | | | | | | | | [000051] 139.#62 C16 Def Alloc rcx | |C16a| | | | | | | | [000129] 140.#63 rcx Fixd Keep rcx | |C16a| | | | | | | | 140.#64 C16 Use * Keep rcx | |C16i| | | | | | | | 141.#65 rcx Fixd Keep rcx | | | | | | | | | | 141.#66 I17 Def Alloc rcx | |I17a| | | | | | | | [000052] 143.#67 C18 Def Alloc rdx | |I17a|C18a| | | | | | | [000130] 144.#68 rdx Fixd Keep rdx | |I17a|C18a| | | | | | | 144.#69 C18 Use * Keep rdx | |I17a|C18i| | | | | | | 145.#70 rdx Fixd Keep rdx | |I17a| | | | | | | | 145.#71 I19 Def Alloc rdx | |I17a|I19a| | | | | | | [000014] 146.#72 rcx Fixd Keep rcx | |I17a|I19a| | | | | | | 146.#73 I17 Use * Keep rcx | |I17i|I19a| | | | | | | 146.#74 rdx Fixd Keep rdx | | |I19a| | | | | | | 146.#75 I19 Use * Keep rdx | | |I19i| | | | | | | 147.#76 rax Kill Keep rax | | | | | | | | | | 147.#77 rcx Kill Keep rcx | | | | | | | | | | 147.#78 rdx Kill Keep rdx | | | | | | | | | | 147.#79 r8 Kill Keep r8 | | | | | | | | | | 147.#80 r9 Kill Keep r9 | | | | | | | | | | 147.#81 r10 Kill Keep r10 | | | | | | | | | | 147.#82 r11 Kill Keep r11 | | | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 152.#83 BB16 PredBB6 | | | | | | | | | | [000090] 157.#84 I20 Def Alloc rax |I20a| | | | | | | | | [000038] 160.#85 I20 Use * Keep rax |I20i| | | | | | | | | 161.#86 I21 Def Alloc rax |I21a| | | | | | | | | [000045] 164.#87 I21 Use * Keep rax |I21i| | | | | | | | | 165.#88 I22 Def Alloc rax |I22a| | | | | | | | | [000097] 166.#89 I22 Use * Keep rax |I22i| | | | | | | | | [000099] 171.#90 C23 Def Alloc rax |C23a| | | | | | | | | [000100] 172.#91 C23 Use * Keep rax |C23i| | | | | | | | | [000101] 175.#92 I24 Def Alloc rax |I24a| | | | | | | | | [000108] 182.#93 I24 Use * Keep rax |I24i| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 186.#94 BB19 PredBB16 | | | | | | | | | | [000098] 191.#95 I25 Def Alloc rcx | |I25a| | | | | | | | [000128] 192.#96 rcx Fixd Keep rcx | |I25a| | | | | | | | 192.#97 I25 Use * Keep rcx | |I25i| | | | | | | | 193.#98 rcx Fixd Keep rcx | | | | | | | | | | 193.#99 I26 Def Alloc rcx | |I26a| | | | | | | | [000103] 195.#100 I27 Def Alloc rax |I27a|I26a| | | | | | | | [000030] 198.#101 I27 Use * Keep rax |I27i|I26a| | | | | | | | 199.#102 I28 Def Alloc rax |I28a|I26a| | | | | | | | [000046] 204.#103 rcx Fixd Keep rcx |I28a|I26a| | | | | | | | 204.#104 I26 Use * Keep rcx |I28a|I26i| | | | | | | | 204.#105 I28 Use * Keep rax |I28i| | | | | | | | | 205.#106 rax Kill Keep rax | | | | | | | | | | 205.#107 rcx Kill Keep rcx | | | | | | | | | | 205.#108 rdx Kill Keep rdx | | | | | | | | | | 205.#109 r8 Kill Keep r8 | | | | | | | | | | 205.#110 r9 Kill Keep r9 | | | | | | | | | | 205.#111 r10 Kill Keep r10 | | | | | | | | | | 205.#112 r11 Kill Keep r11 | | | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 206.#113 BB9 PredBB2 | | | | | | | | | | [000003] 211.#114 rax Kill Keep rax | | | | | | | | | | 211.#115 rcx Kill Keep rcx | | | | | | | | | | 211.#116 rdx Kill Keep rdx | | | | | | | | | | 211.#117 r8 Kill Keep r8 | | | | | | | | | | 211.#118 r9 Kill Keep r9 | | | | | | | | | | 211.#119 r10 Kill Keep r10 | | | | | | | | | | 211.#120 r11 Kill Keep r11 | | | | | | | | | | 211.#121 rax Fixd Keep rax | | | | | | | | | | 211.#122 I29 Def * Alloc rax |I29i| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 212.#123 BB12 PredBB4 | | | | | | | | | | [000019] 217.#124 rax Kill Keep rax | | | | | | | | | | 217.#125 rcx Kill Keep rcx | | | | | | | | | | 217.#126 rdx Kill Keep rdx | | | | | | | | | | 217.#127 r8 Kill Keep r8 | | | | | | | | | | 217.#128 r9 Kill Keep r9 | | | | | | | | | | 217.#129 r10 Kill Keep r10 | | | | | | | | | | 217.#130 r11 Kill Keep r11 | | | | | | | | | | 217.#131 rax Fixd Keep rax | | | | | | | | | | 217.#132 I30 Def * Alloc rax |I30i| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 218.#133 BB15 PredBB5 | | | | | | | | | | [000028] 223.#134 rax Kill Keep rax | | | | | | | | | | 223.#135 rcx Kill Keep rcx | | | | | | | | | | 223.#136 rdx Kill Keep rdx | | | | | | | | | | 223.#137 r8 Kill Keep r8 | | | | | | | | | | 223.#138 r9 Kill Keep r9 | | | | | | | | | | 223.#139 r10 Kill Keep r10 | | | | | | | | | | 223.#140 r11 Kill Keep r11 | | | | | | | | | | 223.#141 rax Fixd Keep rax | | | | | | | | | | 223.#142 I31 Def * Alloc rax |I31i| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 224.#143 BB18 PredBB6 | | | | | | | | | | [000040] 229.#144 rax Kill Keep rax | | | | | | | | | | 229.#145 rcx Kill Keep rcx | | | | | | | | | | 229.#146 rdx Kill Keep rdx | | | | | | | | | | 229.#147 r8 Kill Keep r8 | | | | | | | | | | 229.#148 r9 Kill Keep r9 | | | | | | | | | | 229.#149 r10 Kill Keep r10 | | | | | | | | | | 229.#150 r11 Kill Keep r11 | | | | | | | | | | 229.#151 rax Fixd Keep rax | | | | | | | | | | 229.#152 I32 Def * Alloc rax |I32i| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------------+----+----+----+----+----+----+----+----+----+ 230.#153 BB21 PredBB16 | | | | | | | | | | [000032] 235.#154 rax Kill Keep rax | | | | | | | | | | 235.#155 rcx Kill Keep rcx | | | | | | | | | | 235.#156 rdx Kill Keep rdx | | | | | | | | | | 235.#157 r8 Kill Keep r8 | | | | | | | | | | 235.#158 r9 Kill Keep r9 | | | | | | | | | | 235.#159 r10 Kill Keep r10 | | | | | | | | | | 235.#160 r11 Kill Keep r11 | | | | | | | | | | 235.#161 rax Fixd Keep rax | | | | | | | | | | 235.#162 I33 Def * Alloc rax |I33i| | | | | | | | | Recording the maximum number of concurrent spills: long: 1 pre-allocated temp #1, slot 1, size = 8 ---------- LSRA Stats ---------- Register selection order: ABCDEFGHIJKLMNOPQ Total Tracked Vars: 0 Total Reg Cand Vars: 0 Total number of Intervals: 33 Total number of RefPositions: 163 Total Number of spill temps created: 1 .......... BB02 [ 100.00]: REG_ORDER = 2 BB07 [ 100.00]: SpillCount = 1, REG_ORDER = 2 BB04 [ 100.00]: REG_ORDER = 2 BB10 [ 100.00]: REG_ORDER = 3 BB05 [ 80.00]: REG_ORDER = 2 BB13 [ 80.00]: REG_ORDER = 1 BB06 [ 20.00]: REG_ORDER = 2 BB16 [ 20.00]: REG_ORDER = 5 BB19 [ 20.00]: REG_ORDER = 2 .......... Total SpillCount : 1 Weighted: 100.000000 Total CopyReg : 0 Weighted: 0.000000 Total ResolutionMovs : 0 Weighted: 0.000000 Total SplitEdges : 0 Weighted: 0.000000 .......... Total REG_ORDER [#13] : 21 Weighted: 1320.000000 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: BB01 [0000] [???..???) -> BB02 (always), preds={} succs={BB02} ===== N004. NOP BB02 [0001] [???..???) -> BB07,BB09 (cond), preds={BB01} succs={BB09,BB07} ===== N008. IL_OFFSET INLRT @ 0x000[E-] N010. rax = CNS_INT(h) 0x4000000000420458 global ptr N012. V02 MEM; rax N014. rax = V02 MEM N016. STK = LEA(b+-8); rax N018. STK = IND ; STK N020. CNS_INT 0 N022. CMP ; STK N024. JCC cond=UEQ BB07 [0006] [000..01F) -> BB04 (always), preds={BB02,BB09} succs={BB04} ===== N028. IL_OFFSET INLRT @ 0x000[E-] S N030. rax = V02 MEM N000. rcx = RELOAD ; rax N032. STK = LEA(b+8) ; rcx N034. rcx = V00 MEM N036. rcx = PUTARG_REG; rcx N038. rax = CALL help; rcx N040. STOREIND ; STK,rax BB04 [0003] [???..???) -> BB10,BB12 (cond), preds={BB07} succs={BB12,BB10} ===== N044. IL_OFFSET INLRT @ 0x013[E-] N046. rax = CNS_INT(h) 0x4000000000420458 global ptr N048. V03 MEM; rax N050. rax = V03 MEM N052. STK = LEA(b+-8); rax N054. STK = IND ; STK N056. CNS_INT 0 N058. CMP ; STK N060. JCC cond=UEQ BB10 [0009] [???..???) -> BB06,BB05 (cond), preds={BB04,BB12} succs={BB05,BB06} ===== N064. IL_OFFSET INLRT @ 0x013[E-] N066. rax = V03 MEM N068. STK = LEA(b+8) ; rax N070. rax = IND ; STK N072. CNS_INT 2 N074. rax = AND ; rax N076. CNS_INT 0 N078. CMP ; rax N080. JCC cond=UNE BB05 [0004] [???..???) -> BB13,BB15 (cond), preds={BB10} succs={BB15,BB13} ===== N084. IL_OFFSET INLRT @ 0x013[E-] N086. rax = CNS_INT(h) 0x4000000000420458 global ptr N088. V04 MEM; rax N090. rax = V04 MEM N092. STK = LEA(b+-8); rax N094. STK = IND ; STK N096. CNS_INT 0 N098. CMP ; STK N100. JCC cond=UEQ BB06 [0005] [???..???) -> BB16,BB18 (cond), preds={BB10} succs={BB18,BB16} ===== N104. IL_OFFSET INLRT @ 0x013[E-] N106. rax = CNS_INT(h) 0x4000000000420458 global ptr N108. V05 MEM; rax N110. rax = V05 MEM N112. STK = LEA(b+-8); rax N114. STK = IND ; STK N116. CNS_INT 0 N118. CMP ; STK N120. JCC cond=UEQ BB13 [0012] [???..???) -> BB03 (always), preds={BB05,BB15} succs={BB03} ===== N124. IL_OFFSET INLRT @ 0x013[E-] N126. rax = V04 MEM N128. STK = LEA(b+8) ; rax N130. STK = IND ; STK N132. CALL ind ; STK BB03 [0002] [01F..02F) (return), preds={BB13,BB19} succs={} ===== N136. IL_OFFSET INLRT @ 0x01F[E-] N138. rcx = CNS_INT(h) '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' N140. rcx = PUTARG_REG; rcx N142. rdx = CNS_INT(h) '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' N144. rdx = PUTARG_REG; rdx N146. CALL ; rcx,rdx N148. IL_OFFSET INLRT @ 0x02E[E-] N150. RETURN BB16 [0015] [???..???) -> BB19,BB21 (cond), preds={BB06,BB18} succs={BB21,BB19} ===== N154. IL_OFFSET INLRT @ 0x013[E-] N156. rax = V05 MEM N158. STK = LEA(b+8) ; rax N160. rax = IND ; STK N162. STK = LEA(b+6) ; rax N164. rax = IND ; STK N166. V06 MEM; rax N168. IL_OFFSET INLRT @ 0x013[E-] N170. rax = CNS_INT(h) 0x4000000000420458 global ptr N172. V07 MEM; rax N174. rax = V07 MEM N176. STK = LEA(b+-8); rax N178. STK = IND ; STK N180. CNS_INT 0 N182. CMP ; STK N184. JCC cond=UEQ BB19 [0018] [013..???) -> BB03 (always), preds={BB16,BB21} succs={BB03} ===== N188. IL_OFFSET INLRT @ 0x013[E-] N190. rcx = V06 MEM N192. rcx = PUTARG_REG; rcx N194. rax = V07 MEM N196. STK = LEA(b+8) ; rax N198. rax = IND ; STK N200. STK = LEA(b+-2); rax N202. STK = IND ; STK N204. CALL ind ; rcx,STK BB09 [0008] [???..???) -> BB07 (always), preds={BB02} succs={BB07} ===== N208. IL_OFFSET INLRT @ 0x000[E-] * N210. rax = CALL help BB12 [0011] [???..???) -> BB10 (always), preds={BB04} succs={BB10} ===== N214. IL_OFFSET INLRT @ 0x013[E-] * N216. rax = CALL help BB15 [0014] [???..???) -> BB13 (always), preds={BB05} succs={BB13} ===== N220. IL_OFFSET INLRT @ 0x013[E-] * N222. rax = CALL help BB18 [0017] [???..???) -> BB16 (always), preds={BB06} succs={BB16} ===== N226. IL_OFFSET INLRT @ 0x013[E-] * N228. rax = CALL help BB21 [0020] [???..???) -> BB19 (always), preds={BB16} succs={BB19} ===== N232. IL_OFFSET INLRT @ 0x013[E-] * N234. rax = CALL help *************** Finishing PHASE Linear scan register alloc Trees after Linear scan register alloc ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i LIR keep internal q BB02 [0001] 1 BB01 1 [???..???)-> BB07,BB09 ( cond ) i LIR hascall BB09 [0008] 1 BB02 0 [???..???)-> BB07 (always) LIR rare internal q BB07 [0006] 2 BB02,BB09 1 [000..01F)-> BB04 (always) i LIR hascall q BB04 [0003] 1 BB07 1 [???..???)-> BB10,BB12 ( cond ) i LIR internal hascall BB12 [0011] 1 BB04 0 [???..???)-> BB10 (always) LIR rare internal q BB10 [0009] 2 BB04,BB12 1 [???..???)-> BB06,BB05 ( cond ) i LIR internal hascall q BB05 [0004] 1 BB10 0.80 [???..???)-> BB13,BB15 ( cond ) i LIR internal hascall gcsafe BB15 [0014] 1 BB05 0 [???..???)-> BB13 (always) LIR rare internal q BB13 [0012] 2 BB05,BB15 0.80 [???..???)-> BB03 (always) i LIR internal hascall gcsafe BB06 [0005] 1 BB10 0.20 [???..???)-> BB16,BB18 ( cond ) i LIR internal hascall gcsafe BB18 [0017] 1 BB06 0 [???..???)-> BB16 (always) LIR rare internal q BB16 [0015] 2 BB06,BB18 0.20 [???..???)-> BB19,BB21 ( cond ) i LIR internal hascall gcsafe BB21 [0020] 1 BB16 0 [???..???)-> BB19 (always) LIR rare internal q BB19 [0018] 2 BB16,BB21 0.20 [013..???)-> BB03 (always) i LIR internal hascall gcsafe q BB03 [0002] 2 BB13,BB19 1 [01F..02F) (return) i LIR internal hascall gcsafe ---------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [???..???) -> BB02 (always), preds={} succs={BB02} N004 ( 0, 0) [000000] ----------- NOP void REG NA ------------ BB02 [0001] [???..???) -> BB07,BB09 (cond), preds={BB01} succs={BB09,BB07} N008 (???,???) [000110] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA N010 ( 1, 4) [000053] H---------- t53 = CNS_INT(h) long 0x4000000000420458 global ptr REG rax /--* t53 long N012 ( 5, 7) [000054] DA--------- * STORE_LCL_VAR long V02 tmp1 NA REG NA N014 ( 3, 2) [000055] ----------- t55 = LCL_VAR long V02 tmp1 rax REG rax /--* t55 long N016 ( 9, 10) [000059] -c--------- t59 = * LEA(b+-8) long REG NA /--* t59 long N018 ( 11, 12) [000060] nA--G------ t60 = * IND long REG NA N020 ( 1, 1) [000061] -c--------- t61 = CNS_INT long 0 REG NA /--* t60 long +--* t61 long N022 ( 13, 14) [000062] -A--G------ * CMP void REG NA N024 ( 15, 16) [000063] -A--G------ JCC void cond=UEQ REG NA ------------ BB09 [0008] [???..???) -> BB07 (always), preds={BB02} succs={BB07} N208 (???,???) [000111] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA N210 ( 14, 5) [000003] H-CXG------ u3 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG rax ------------ BB07 [0006] [000..01F) -> BB04 (always), preds={BB02,BB09} succs={BB04} N028 (???,???) [000112] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA N030 ( 3, 2) [000057] ----------Z t57 = LCL_VAR long V02 tmp1 rax REG rax /--* t57 long [000131] ----------- t131 = * RELOAD long REG rcx /--* t131 long N032 ( 4, 3) [000005] -c--------- t5 = * LEA(b+8) byref REG NA N034 ( 3, 2) [000001] !---------- t1 = LCL_VAR long V00 TypeCtx rcx REG rcx /--* t1 long N036 (???,???) [000127] ----------- t127 = * PUTARG_REG long REG rcx /--* t127 long arg0 in rcx N038 ( 17, 8) [000002] --C-G------ t2 = * CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE REG rax /--* t5 byref +--* t2 long N040 ( 24, 14) [000006] VAC-GO----- * STOREIND long REG NA ------------ BB04 [0003] [???..???) -> BB10,BB12 (cond), preds={BB07} succs={BB12,BB10} N044 (???,???) [000113] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N046 ( 1, 4) [000064] H---------- t64 = CNS_INT(h) long 0x4000000000420458 global ptr REG rax /--* t64 long N048 ( 5, 7) [000065] DA--------- * STORE_LCL_VAR long V03 tmp2 NA REG NA N050 ( 3, 2) [000066] ----------- t66 = LCL_VAR long V03 tmp2 rax REG rax /--* t66 long N052 ( 9, 10) [000070] -c--------- t70 = * LEA(b+-8) long REG NA /--* t70 long N054 ( 11, 12) [000071] nA--G------ t71 = * IND long REG NA N056 ( 1, 1) [000072] -c--------- t72 = CNS_INT long 0 REG NA /--* t71 long +--* t72 long N058 ( 13, 14) [000073] -A--G------ * CMP void REG NA N060 ( 15, 16) [000074] -A--G------ JCC void cond=UEQ REG NA ------------ BB12 [0011] [???..???) -> BB10 (always), preds={BB04} succs={BB10} N214 (???,???) [000114] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N216 ( 14, 5) [000019] H-CXG------ u19 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG rax ------------ BB10 [0009] [???..???) -> BB06,BB05 (cond), preds={BB04,BB12} succs={BB05,BB06} N064 (???,???) [000115] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N066 ( 3, 2) [000068] ----------- t68 = LCL_VAR long V03 tmp2 rax REG rax /--* t68 long N068 ( 4, 3) [000018] -c--------- t18 = * LEA(b+8) byref REG NA /--* t18 byref N070 ( 6, 5) [000017] V---GO----- t17 = * IND int REG rax N072 ( 1, 1) [000016] -c--------- t16 = CNS_INT int 2 REG NA /--* t17 int +--* t16 int N074 ( 8, 7) [000021] ----GO----- t21 = * AND int REG rax N076 ( 1, 1) [000022] -c--------- t22 = CNS_INT int 0 REG NA /--* t21 int +--* t22 int N078 ( 10, 9) [000023] ----GO-N--- * CMP void REG NA N080 ( 12, 11) [000024] ----GO----- JCC void cond=UNE REG NA ------------ BB05 [0004] [???..???) -> BB13,BB15 (cond), preds={BB10} succs={BB15,BB13} N084 (???,???) [000116] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N086 ( 1, 4) [000075] H---------- t75 = CNS_INT(h) long 0x4000000000420458 global ptr REG rax /--* t75 long N088 ( 5, 7) [000076] DA--------- * STORE_LCL_VAR long V04 tmp3 NA REG NA N090 ( 3, 2) [000077] ----------- t77 = LCL_VAR long V04 tmp3 rax REG rax /--* t77 long N092 ( 9, 10) [000081] -c--------- t81 = * LEA(b+-8) long REG NA /--* t81 long N094 ( 11, 12) [000082] nA--G------ t82 = * IND long REG NA N096 ( 1, 1) [000083] -c--------- t83 = CNS_INT long 0 REG NA /--* t82 long +--* t83 long N098 ( 13, 14) [000084] -A--G------ * CMP void REG NA N100 ( 15, 16) [000085] -A--G------ JCC void cond=UEQ REG NA ------------ BB15 [0014] [???..???) -> BB13 (always), preds={BB05} succs={BB13} N220 (???,???) [000117] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N222 ( 14, 5) [000028] H-CXG------ u28 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG rax ------------ BB13 [0012] [???..???) -> BB03 (always), preds={BB05,BB15} succs={BB03} N124 (???,???) [000118] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N126 ( 3, 2) [000079] ----------- t79 = LCL_VAR long V04 tmp3 rax REG rax /--* t79 long N128 ( 4, 3) [000027] -c--------- t27 = * LEA(b+8) byref REG NA /--* t27 byref N130 ( 6, 5) [000026] Vc--GO----- t26 = * IND long REG NA /--* t26 long calli tgt N132 ( 23, 7) [000025] --CXGO----- * CALL ind void REG NA ------------ BB06 [0005] [???..???) -> BB16,BB18 (cond), preds={BB10} succs={BB18,BB16} N104 (???,???) [000119] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N106 ( 1, 4) [000086] H---------- t86 = CNS_INT(h) long 0x4000000000420458 global ptr REG rax /--* t86 long N108 ( 5, 7) [000087] DA--------- * STORE_LCL_VAR long V05 tmp4 NA REG NA N110 ( 3, 2) [000088] ----------- t88 = LCL_VAR long V05 tmp4 rax REG rax /--* t88 long N112 ( 9, 10) [000092] -c--------- t92 = * LEA(b+-8) long REG NA /--* t92 long N114 ( 11, 12) [000093] nA--G------ t93 = * IND long REG NA N116 ( 1, 1) [000094] -c--------- t94 = CNS_INT long 0 REG NA /--* t93 long +--* t94 long N118 ( 13, 14) [000095] -A--G------ * CMP void REG NA N120 ( 15, 16) [000096] -A--G------ JCC void cond=UEQ REG NA ------------ BB18 [0017] [???..???) -> BB16 (always), preds={BB06} succs={BB16} N226 (???,???) [000120] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N228 ( 14, 5) [000040] H-CXG------ u40 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG rax ------------ BB16 [0015] [???..???) -> BB19,BB21 (cond), preds={BB06,BB18} succs={BB21,BB19} N154 (???,???) [000121] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N156 ( 3, 2) [000090] ----------- t90 = LCL_VAR long V05 tmp4 rax REG rax /--* t90 long N158 ( 4, 3) [000039] -c--------- t39 = * LEA(b+8) byref REG NA /--* t39 byref N160 ( 6, 5) [000038] V---GO----- t38 = * IND long REG rax /--* t38 long N162 ( 9, 8) [000044] -c--------- t44 = * LEA(b+6) long REG NA /--* t44 long N164 ( 9, 8) [000045] ---XGO----- t45 = * IND long REG rax /--* t45 long N166 ( 13, 11) [000097] DA-XGO----- * STORE_LCL_VAR long V06 tmp5 NA REG NA N168 (???,???) [000122] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N170 ( 1, 4) [000099] H---------- t99 = CNS_INT(h) long 0x4000000000420458 global ptr REG rax /--* t99 long N172 ( 5, 7) [000100] DA--------- * STORE_LCL_VAR long V07 tmp6 NA REG NA N174 ( 3, 2) [000101] ----------- t101 = LCL_VAR long V07 tmp6 rax REG rax /--* t101 long N176 ( 9, 10) [000105] -c--------- t105 = * LEA(b+-8) long REG NA /--* t105 long N178 ( 11, 12) [000106] nA--G------ t106 = * IND long REG NA N180 ( 1, 1) [000107] -c--------- t107 = CNS_INT long 0 REG NA /--* t106 long +--* t107 long N182 ( 13, 14) [000108] -A--G------ * CMP void REG NA N184 ( 15, 16) [000109] -A--G------ JCC void cond=UEQ REG NA ------------ BB21 [0020] [???..???) -> BB19 (always), preds={BB16} succs={BB19} N232 (???,???) [000123] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N234 ( 14, 5) [000032] H-CXG------ u32 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG rax ------------ BB19 [0018] [013..???) -> BB03 (always), preds={BB16,BB21} succs={BB03} N188 (???,???) [000124] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA N190 ( 3, 2) [000098] ----------- t98 = LCL_VAR long V06 tmp5 rcx REG rcx /--* t98 long N192 (???,???) [000128] ----------- t128 = * PUTARG_REG long REG rcx N194 ( 3, 2) [000103] ----------- t103 = LCL_VAR long V07 tmp6 rax REG rax /--* t103 long N196 ( 4, 3) [000031] -c--------- t31 = * LEA(b+8) byref REG NA /--* t31 byref N198 ( 6, 5) [000030] V---GO----- t30 = * IND long REG rax /--* t30 long N200 ( 7, 6) [000035] -c--------- t35 = * LEA(b+-2) long REG NA /--* t35 long N202 ( 9, 8) [000036] -c-XGO----- t36 = * IND long REG NA /--* t128 long gctx in rcx +--* t36 long calli tgt N204 ( 29, 13) [000046] --CXGO----- * CALL ind void REG NA ------------ BB03 [0002] [01F..02F) (return), preds={BB13,BB19} succs={} N136 (???,???) [000125] ----------- IL_OFFSET void INLRT @ 0x01F[E-] REG NA N138 ( 1, 4) [000051] H---------- t51 = CNS_INT(h) ref '"Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericO' REG rcx /--* t51 ref N140 (???,???) [000129] ----------- t129 = * PUTARG_REG ref REG rcx N142 ( 1, 4) [000052] H---------- t52 = CNS_INT(h) ref '"valuetype GenericValuetype`1'IFaceNonGeneric.NormalMet' REG rdx /--* t52 ref N144 (???,???) [000130] ----------- t130 = * PUTARG_REG ref REG rdx /--* t129 ref arg0 in rcx +--* t130 ref arg1 in rdx N146 ( 16, 15) [000014] --CXG------ * CALL void Statics:CheckForFailure(System.String,System.String) REG NA N148 (???,???) [000126] ----------- IL_OFFSET void INLRT @ 0x02E[E-] REG NA N150 ( 0, 0) [000015] ----------- RETURN void REG NA ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Place 'align' instructions *************** In placeLoopAlignInstructions() Not aligning loops; ShouldAlignLoops is false *************** Finishing PHASE Place 'align' instructions [no changes] *************** In genGenerateCode() ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i LIR keep internal q BB02 [0001] 1 BB01 1 [???..???)-> BB07,BB09 ( cond ) i LIR hascall BB09 [0008] 1 BB02 0 [???..???)-> BB07 (always) LIR rare internal q BB07 [0006] 2 BB02,BB09 1 [000..01F)-> BB04 (always) i LIR hascall q BB04 [0003] 1 BB07 1 [???..???)-> BB10,BB12 ( cond ) i LIR internal hascall BB12 [0011] 1 BB04 0 [???..???)-> BB10 (always) LIR rare internal q BB10 [0009] 2 BB04,BB12 1 [???..???)-> BB06,BB05 ( cond ) i LIR internal hascall q BB05 [0004] 1 BB10 0.80 [???..???)-> BB13,BB15 ( cond ) i LIR internal hascall gcsafe BB15 [0014] 1 BB05 0 [???..???)-> BB13 (always) LIR rare internal q BB13 [0012] 2 BB05,BB15 0.80 [???..???)-> BB03 (always) i LIR internal hascall gcsafe BB06 [0005] 1 BB10 0.20 [???..???)-> BB16,BB18 ( cond ) i LIR internal hascall gcsafe BB18 [0017] 1 BB06 0 [???..???)-> BB16 (always) LIR rare internal q BB16 [0015] 2 BB06,BB18 0.20 [???..???)-> BB19,BB21 ( cond ) i LIR internal hascall gcsafe BB21 [0020] 1 BB16 0 [???..???)-> BB19 (always) LIR rare internal q BB19 [0018] 2 BB16,BB21 0.20 [013..???)-> BB03 (always) i LIR internal hascall gcsafe q BB03 [0002] 2 BB13,BB19 1 [01F..02F) (return) i LIR internal hascall gcsafe ---------------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Generate code *************** In fgDebugCheckBBlist Finalizing stack frame Modified regs: [rax rcx rdx rdi r8-r11] Callee-saved registers pushed: 1 [rdi] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Assign V02 tmp1, size=8, stkOffs=-0x28 Assign V03 tmp2, size=8, stkOffs=-0x30 Assign V04 tmp3, size=8, stkOffs=-0x38 Assign V05 tmp4, size=8, stkOffs=-0x40 Assign V06 tmp5, size=8, stkOffs=-0x48 Assign V07 tmp6, size=8, stkOffs=-0x50 Assign V01 OutArgs, size=32, stkOffs=-0x78 --- delta bump 8 for RA --- delta bump 8 for FP --- delta bump 0 for FP frame --- virtual stack offset to actual stack offset delta is 16 -- V00 was 0, now 16 -- V01 was -120, now -104 -- V02 was -40, now -24 -- V03 was -48, now -32 -- V04 was -56, now -40 -- V05 was -64, now -48 -- V06 was -72, now -56 -- V07 was -80, now -64 ; Final local variable assignments ; ; V00 TypeCtx [V00 ] ( 1, 1 ) long -> [rbp+0x10] do-not-enreg[] ; V01 OutArgs [V01 ] ( 1, 1 ) struct (32) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ; V02 tmp1 [V02 ] ( 1, 1 ) long -> [rbp-0x18] do-not-enreg[] "fgMakeTemp is creating a new local variable" ; V03 tmp2 [V03 ] ( 1, 1 ) long -> [rbp-0x20] do-not-enreg[] "fgMakeTemp is creating a new local variable" ; V04 tmp3 [V04 ] ( 1, 1 ) long -> [rbp-0x28] do-not-enreg[] "fgMakeTemp is creating a new local variable" ; V05 tmp4 [V05 ] ( 1, 1 ) long -> [rbp-0x30] do-not-enreg[] "fgMakeTemp is creating a new local variable" ; V06 tmp5 [V06 ] ( 1, 1 ) long -> [rbp-0x38] do-not-enreg[] "Spilling to split statement for tree" ; V07 tmp6 [V07 ] ( 1, 1 ) long -> [rbp-0x40] do-not-enreg[] "fgMakeTemp is creating a new local variable" ; TEMP_01 long -> [rbp-0x48] ; ; Lcl frame size = 104 Created: G_M11011_IG02: ; offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} Mark labels for codegen BB01 : first block BB07 : branch target BB10 : branch target BB06 : branch target BB13 : branch target BB03 : branch target BB16 : branch target BB19 : branch target *************** After genMarkLabelsForCodegen() ---------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] ---------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???)-> BB02 (always) i LIR keep internal label q BB02 [0001] 1 BB01 1 [???..???)-> BB07,BB09 ( cond ) i LIR hascall BB09 [0008] 1 BB02 0 [???..???)-> BB07 (always) LIR rare internal q BB07 [0006] 2 BB02,BB09 1 [000..01F)-> BB04 (always) i LIR label hascall q BB04 [0003] 1 BB07 1 [???..???)-> BB10,BB12 ( cond ) i LIR internal hascall BB12 [0011] 1 BB04 0 [???..???)-> BB10 (always) LIR rare internal q BB10 [0009] 2 BB04,BB12 1 [???..???)-> BB06,BB05 ( cond ) i LIR internal label hascall q BB05 [0004] 1 BB10 0.80 [???..???)-> BB13,BB15 ( cond ) i LIR internal hascall gcsafe BB15 [0014] 1 BB05 0 [???..???)-> BB13 (always) LIR rare internal q BB13 [0012] 2 BB05,BB15 0.80 [???..???)-> BB03 (always) i LIR internal label hascall gcsafe BB06 [0005] 1 BB10 0.20 [???..???)-> BB16,BB18 ( cond ) i LIR internal label hascall gcsafe BB18 [0017] 1 BB06 0 [???..???)-> BB16 (always) LIR rare internal q BB16 [0015] 2 BB06,BB18 0.20 [???..???)-> BB19,BB21 ( cond ) i LIR internal label hascall gcsafe BB21 [0020] 1 BB16 0 [???..???)-> BB19 (always) LIR rare internal q BB19 [0018] 2 BB16,BB21 0.20 [013..???)-> BB03 (always) i LIR internal label hascall gcsafe q BB03 [0002] 2 BB13,BB19 1 [01F..02F) (return) i LIR internal label hascall gcsafe ---------------------------------------------------------------------------------------------------------------------------------------------- Setting stack level from -572662307 to 0 =============== Generating BB01 [0000] [???..???) -> BB02 (always), preds={} succs={BB02} flags=0x00000100.00008039: i LIR keep internal label q BB01 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M11011_BB01: Label: G_M11011_IG02, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB01, IL range [???..???) Scope info: ignoring block beginning Generating: N004 ( 0, 0) [000000] ----------- NOP void REG NA Scope info: ignoring block end Variable Live Range History Dump for BB01 ..None.. =============== Generating BB02 [0001] [???..???) -> BB07,BB09 (cond), preds={BB01} succs={BB09,BB07} flags=0x00000000.10000011: i LIR hascall BB02 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M11011_BB02: Scope info: begin block BB02, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: 0x0000 STACK_EMPTY (G_M11011_IG02,ins#0,ofs#0) label Generating: N008 (???,???) [000110] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA Generating: N010 ( 1, 4) [000053] H---------- t53 = CNS_INT(h) long 0x4000000000420458 global ptr REG rax Mapped BB02 to G_M11011_IG02 IN0001: lea rax, [(reloc 0x4000000000420458)] /--* t53 long Generating: N012 ( 5, 7) [000054] DA--------- * STORE_LCL_VAR long V02 tmp1 NA REG NA IN0002: mov qword ptr [V02 rbp-0x18], rax Generating: N014 ( 3, 2) [000055] ----------- t55 = LCL_VAR long V02 tmp1 rax REG rax IN0003: mov rax, qword ptr [V02 rbp-0x18] /--* t55 long Generating: N016 ( 9, 10) [000059] -c--------- t59 = * LEA(b+-8) long REG NA /--* t59 long Generating: N018 ( 11, 12) [000060] nA--G------ t60 = * IND long REG NA Generating: N020 ( 1, 1) [000061] -c--------- t61 = CNS_INT long 0 REG NA /--* t60 long +--* t61 long Generating: N022 ( 13, 14) [000062] -A--G------ * CMP void REG NA IN0004: cmp qword ptr [rax-0x08], 0 Generating: N024 ( 15, 16) [000063] -A--G------ JCC void cond=UEQ REG NA IN0005: je L_M11011_BB07 Scope info: ignoring block end Variable Live Range History Dump for BB02 ..None.. =============== Generating BB09 [0008] [???..???) -> BB07 (always), preds={BB02} succs={BB07} flags=0x00000100.00002021: LIR rare internal q BB09 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M11011_BB09: Adding label due to BB weight difference: BBJ_COND BB02 with weight 100 different from BB09 with weight 0 Saved: G_M11011_IG02: ; offs=0x000000, size=0x001A, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byref Created: G_M11011_IG03: ; offs=0x00001A, size=0x0000, bbWeight=0, gcrefRegs=0000 {} Label: G_M11011_IG03, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB09, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP (G_M11011_IG03,ins#0,ofs#0) label Added IP mapping: 0x0000 STACK_EMPTY (G_M11011_IG03,ins#0,ofs#0) label Generating: N208 (???,???) [000111] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA Generating: N210 ( 14, 5) [000003] H-CXG------ u3 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG rax Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Mapped BB09 to G_M11011_IG03 IN0006: call CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE Byref regs: 0000 {} => 0001 {rax} Byref regs: 0001 {rax} => 0000 {} Scope info: ignoring block end Variable Live Range History Dump for BB09 ..None.. =============== Generating BB07 [0006] [000..01F) -> BB04 (always), preds={BB02,BB09} succs={BB04} flags=0x00000100.10008011: i LIR label hascall q BB07 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M11011_BB07: Saved: G_M11011_IG03: ; offs=0x00001A, size=0x0005, bbWeight=0, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB09 [0008], byref Created: G_M11011_IG04: ; offs=0x00001F, size=0x0000, bbWeight=1, gcrefRegs=0000 {} Label: G_M11011_IG04, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB07, IL range [000..01F) Scope info: opening scope, LVnum=0 [000..02F) Debug: New V00 debug range: first genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N028 (???,???) [000112] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA Generating: N030 ( 3, 2) [000057] ----------Z t57 = LCL_VAR long V02 tmp1 rax REG rax Mapped BB07 to G_M11011_IG04 IN0007: mov rax, qword ptr [V02 rbp-0x18] reused temp #1, slot 1, size = 8 The register rax spilled with [000057] IN0008: mov qword ptr [TEMP_01 rbp-0x48], rax /--* t57 long Generating: [000131] ----------- t131 = * RELOAD long REG rcx /--* t131 long Generating: N032 ( 4, 3) [000005] -c--------- t5 = * LEA(b+8) byref REG NA Generating: N034 ( 3, 2) [000001] !---------- t1 = LCL_VAR long V00 TypeCtx rcx REG rcx IN0009: mov rcx, qword ptr [V00 rbp+0x10] /--* t1 long Generating: N036 (???,???) [000127] ----------- t127 = * PUTARG_REG long REG rcx /--* t127 long arg0 in rcx Generating: N038 ( 17, 8) [000002] --C-G------ t2 = * CALL help long CORINFO_HELP_READYTORUN_GENERIC_HANDLE REG rax Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} IN000a: call CORINFO_HELP_READYTORUN_GENERIC_HANDLE /--* t5 byref +--* t2 long Generating: N040 ( 24, 14) [000006] VAC-GO----- * STOREIND long REG NA Tree-Node marked unspilled from [000057] IN000b: mov rcx, qword ptr [TEMP_01 rbp-0x48] release temp #1, slot 1, size = 8 IN000c: mov qword ptr [rcx+0x08], rax Variable Live Range History Dump for BB07 V00 TypeCtx: rbp[16] (1 slot) [(G_M11011_IG04,ins#0,ofs#0), ...] =============== Generating BB04 [0003] [???..???) -> BB10,BB12 (cond), preds={BB07} succs={BB12,BB10} flags=0x00000000.10000031: i LIR internal hascall BB04 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M11011_BB04: Scope info: begin block BB04, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP (G_M11011_IG04,ins#6,ofs#25) label Added IP mapping: 0x0013 STACK_EMPTY (G_M11011_IG04,ins#6,ofs#25) label Generating: N044 (???,???) [000113] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA Generating: N046 ( 1, 4) [000064] H---------- t64 = CNS_INT(h) long 0x4000000000420458 global ptr REG rax Mapped BB04 to G_M11011_IG04 IN000d: lea rax, [(reloc 0x4000000000420458)] /--* t64 long Generating: N048 ( 5, 7) [000065] DA--------- * STORE_LCL_VAR long V03 tmp2 NA REG NA IN000e: mov qword ptr [V03 rbp-0x20], rax Generating: N050 ( 3, 2) [000066] ----------- t66 = LCL_VAR long V03 tmp2 rax REG rax IN000f: mov rax, qword ptr [V03 rbp-0x20] /--* t66 long Generating: N052 ( 9, 10) [000070] -c--------- t70 = * LEA(b+-8) long REG NA /--* t70 long Generating: N054 ( 11, 12) [000071] nA--G------ t71 = * IND long REG NA Generating: N056 ( 1, 1) [000072] -c--------- t72 = CNS_INT long 0 REG NA /--* t71 long +--* t72 long Generating: N058 ( 13, 14) [000073] -A--G------ * CMP void REG NA IN0010: cmp qword ptr [rax-0x08], 0 Generating: N060 ( 15, 16) [000074] -A--G------ JCC void cond=UEQ REG NA IN0011: je L_M11011_BB10 Scope info: ignoring block end Variable Live Range History Dump for BB04 V00 TypeCtx: rbp[16] (1 slot) [(G_M11011_IG04,ins#0,ofs#0), ...] =============== Generating BB12 [0011] [???..???) -> BB10 (always), preds={BB04} succs={BB10} flags=0x00000100.00002021: LIR rare internal q BB12 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M11011_BB12: Adding label due to BB weight difference: BBJ_COND BB04 with weight 100 different from BB12 with weight 0 Saved: G_M11011_IG04: ; offs=0x00001F, size=0x0033, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB07 [0006], BB04 [0003], byref Created: G_M11011_IG05: ; offs=0x000052, size=0x0000, bbWeight=0, gcrefRegs=0000 {} Label: G_M11011_IG05, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB12, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP (G_M11011_IG05,ins#0,ofs#0) label Added IP mapping: 0x0013 STACK_EMPTY (G_M11011_IG05,ins#0,ofs#0) label Generating: N214 (???,???) [000114] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA Generating: N216 ( 14, 5) [000019] H-CXG------ u19 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG rax Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Mapped BB12 to G_M11011_IG05 IN0012: call CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE Byref regs: 0000 {} => 0001 {rax} Byref regs: 0001 {rax} => 0000 {} Scope info: ignoring block end Variable Live Range History Dump for BB12 V00 TypeCtx: rbp[16] (1 slot) [(G_M11011_IG04,ins#0,ofs#0), ...] =============== Generating BB10 [0009] [???..???) -> BB06,BB05 (cond), preds={BB04,BB12} succs={BB05,BB06} flags=0x00000100.10008031: i LIR internal label hascall q BB10 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M11011_BB10: Saved: G_M11011_IG05: ; offs=0x000052, size=0x0005, bbWeight=0, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB12 [0011], byref Created: G_M11011_IG06: ; offs=0x000057, size=0x0000, bbWeight=1, gcrefRegs=0000 {} Label: G_M11011_IG06, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB10, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP (G_M11011_IG06,ins#0,ofs#0) label Added IP mapping: 0x0013 STACK_EMPTY (G_M11011_IG06,ins#0,ofs#0) label Generating: N064 (???,???) [000115] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA Generating: N066 ( 3, 2) [000068] ----------- t68 = LCL_VAR long V03 tmp2 rax REG rax Mapped BB10 to G_M11011_IG06 IN0013: mov rax, qword ptr [V03 rbp-0x20] /--* t68 long Generating: N068 ( 4, 3) [000018] -c--------- t18 = * LEA(b+8) byref REG NA /--* t18 byref Generating: N070 ( 6, 5) [000017] V---GO----- t17 = * IND int REG rax IN0014: mov eax, dword ptr [rax+0x08] Generating: N072 ( 1, 1) [000016] -c--------- t16 = CNS_INT int 2 REG NA /--* t17 int +--* t16 int Generating: N074 ( 8, 7) [000021] ----GO----- t21 = * AND int REG rax IN0015: and eax, 2 Generating: N076 ( 1, 1) [000022] -c--------- t22 = CNS_INT int 0 REG NA /--* t21 int +--* t22 int Generating: N078 ( 10, 9) [000023] ----GO-N--- * CMP void REG NA IN0016: test eax, eax Generating: N080 ( 12, 11) [000024] ----GO----- JCC void cond=UNE REG NA IN0017: jne L_M11011_BB06 Scope info: ignoring block end Variable Live Range History Dump for BB10 V00 TypeCtx: rbp[16] (1 slot) [(G_M11011_IG04,ins#0,ofs#0), ...] =============== Generating BB05 [0004] [???..???) -> BB13,BB15 (cond), preds={BB10} succs={BB15,BB13} flags=0x00000000.10080031: i LIR internal hascall gcsafe BB05 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M11011_BB05: Adding label due to BB weight difference: BBJ_COND BB10 with weight 100 different from BB05 with weight 80 Saved: G_M11011_IG06: ; offs=0x000057, size=0x0012, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB10 [0009], byref Created: G_M11011_IG07: ; offs=0x000069, size=0x0000, bbWeight=0.80, gcrefRegs=0000 {} Label: G_M11011_IG07, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB05, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP (G_M11011_IG07,ins#0,ofs#0) label Added IP mapping: 0x0013 STACK_EMPTY (G_M11011_IG07,ins#0,ofs#0) label Generating: N084 (???,???) [000116] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA Generating: N086 ( 1, 4) [000075] H---------- t75 = CNS_INT(h) long 0x4000000000420458 global ptr REG rax Mapped BB05 to G_M11011_IG07 IN0018: lea rax, [(reloc 0x4000000000420458)] /--* t75 long Generating: N088 ( 5, 7) [000076] DA--------- * STORE_LCL_VAR long V04 tmp3 NA REG NA IN0019: mov qword ptr [V04 rbp-0x28], rax Generating: N090 ( 3, 2) [000077] ----------- t77 = LCL_VAR long V04 tmp3 rax REG rax IN001a: mov rax, qword ptr [V04 rbp-0x28] /--* t77 long Generating: N092 ( 9, 10) [000081] -c--------- t81 = * LEA(b+-8) long REG NA /--* t81 long Generating: N094 ( 11, 12) [000082] nA--G------ t82 = * IND long REG NA Generating: N096 ( 1, 1) [000083] -c--------- t83 = CNS_INT long 0 REG NA /--* t82 long +--* t83 long Generating: N098 ( 13, 14) [000084] -A--G------ * CMP void REG NA IN001b: cmp qword ptr [rax-0x08], 0 Generating: N100 ( 15, 16) [000085] -A--G------ JCC void cond=UEQ REG NA IN001c: je L_M11011_BB13 Scope info: ignoring block end Variable Live Range History Dump for BB05 V00 TypeCtx: rbp[16] (1 slot) [(G_M11011_IG04,ins#0,ofs#0), ...] =============== Generating BB15 [0014] [???..???) -> BB13 (always), preds={BB05} succs={BB13} flags=0x00000100.00002021: LIR rare internal q BB15 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M11011_BB15: Adding label due to BB weight difference: BBJ_COND BB05 with weight 80 different from BB15 with weight 0 Saved: G_M11011_IG07: ; offs=0x000069, size=0x001A, bbWeight=0.80, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB05 [0004], byref Created: G_M11011_IG08: ; offs=0x000083, size=0x0000, bbWeight=0, gcrefRegs=0000 {} Label: G_M11011_IG08, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB15, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP (G_M11011_IG08,ins#0,ofs#0) label Added IP mapping: 0x0013 STACK_EMPTY (G_M11011_IG08,ins#0,ofs#0) label Generating: N220 (???,???) [000117] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA Generating: N222 ( 14, 5) [000028] H-CXG------ u28 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG rax Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Mapped BB15 to G_M11011_IG08 IN001d: call CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE Byref regs: 0000 {} => 0001 {rax} Byref regs: 0001 {rax} => 0000 {} Scope info: ignoring block end Variable Live Range History Dump for BB15 V00 TypeCtx: rbp[16] (1 slot) [(G_M11011_IG04,ins#0,ofs#0), ...] =============== Generating BB13 [0012] [???..???) -> BB03 (always), preds={BB05,BB15} succs={BB03} flags=0x00000000.10088031: i LIR internal label hascall gcsafe BB13 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M11011_BB13: Saved: G_M11011_IG08: ; offs=0x000083, size=0x0005, bbWeight=0, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB15 [0014], byref Created: G_M11011_IG09: ; offs=0x000088, size=0x0000, bbWeight=0.80, gcrefRegs=0000 {} Label: G_M11011_IG09, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB13, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP (G_M11011_IG09,ins#0,ofs#0) label Added IP mapping: 0x0013 STACK_EMPTY (G_M11011_IG09,ins#0,ofs#0) label Generating: N124 (???,???) [000118] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA Generating: N126 ( 3, 2) [000079] ----------- t79 = LCL_VAR long V04 tmp3 rax REG rax Mapped BB13 to G_M11011_IG09 IN001e: mov rax, qword ptr [V04 rbp-0x28] /--* t79 long Generating: N128 ( 4, 3) [000027] -c--------- t27 = * LEA(b+8) byref REG NA /--* t27 byref Generating: N130 ( 6, 5) [000026] Vc--GO----- t26 = * IND long REG NA /--* t26 long calli tgt Generating: N132 ( 23, 7) [000025] --CXGO----- * CALL ind void REG NA Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} IN001f: call [rax+0x08] Scope info: ignoring block end IN0020: jmp L_M11011_BB03 Variable Live Range History Dump for BB13 V00 TypeCtx: rbp[16] (1 slot) [(G_M11011_IG04,ins#0,ofs#0), ...] =============== Generating BB06 [0005] [???..???) -> BB16,BB18 (cond), preds={BB10} succs={BB18,BB16} flags=0x00000000.10088031: i LIR internal label hascall gcsafe BB06 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M11011_BB06: Saved: G_M11011_IG09: ; offs=0x000088, size=0x000C, bbWeight=0.80, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB13 [0012], byref Created: G_M11011_IG10: ; offs=0x000094, size=0x0000, bbWeight=0.20, gcrefRegs=0000 {} Label: G_M11011_IG10, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB06, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP (G_M11011_IG10,ins#0,ofs#0) label Added IP mapping: 0x0013 STACK_EMPTY (G_M11011_IG10,ins#0,ofs#0) label Generating: N104 (???,???) [000119] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA Generating: N106 ( 1, 4) [000086] H---------- t86 = CNS_INT(h) long 0x4000000000420458 global ptr REG rax Mapped BB06 to G_M11011_IG10 IN0021: lea rax, [(reloc 0x4000000000420458)] /--* t86 long Generating: N108 ( 5, 7) [000087] DA--------- * STORE_LCL_VAR long V05 tmp4 NA REG NA IN0022: mov qword ptr [V05 rbp-0x30], rax Generating: N110 ( 3, 2) [000088] ----------- t88 = LCL_VAR long V05 tmp4 rax REG rax IN0023: mov rax, qword ptr [V05 rbp-0x30] /--* t88 long Generating: N112 ( 9, 10) [000092] -c--------- t92 = * LEA(b+-8) long REG NA /--* t92 long Generating: N114 ( 11, 12) [000093] nA--G------ t93 = * IND long REG NA Generating: N116 ( 1, 1) [000094] -c--------- t94 = CNS_INT long 0 REG NA /--* t93 long +--* t94 long Generating: N118 ( 13, 14) [000095] -A--G------ * CMP void REG NA IN0024: cmp qword ptr [rax-0x08], 0 Generating: N120 ( 15, 16) [000096] -A--G------ JCC void cond=UEQ REG NA IN0025: je L_M11011_BB16 Scope info: ignoring block end Variable Live Range History Dump for BB06 V00 TypeCtx: rbp[16] (1 slot) [(G_M11011_IG04,ins#0,ofs#0), ...] =============== Generating BB18 [0017] [???..???) -> BB16 (always), preds={BB06} succs={BB16} flags=0x00000100.00002021: LIR rare internal q BB18 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M11011_BB18: Adding label due to BB weight difference: BBJ_COND BB06 with weight 20 different from BB18 with weight 0 Saved: G_M11011_IG10: ; offs=0x000094, size=0x001A, bbWeight=0.20, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB06 [0005], byref Created: G_M11011_IG11: ; offs=0x0000AE, size=0x0000, bbWeight=0, gcrefRegs=0000 {} Label: G_M11011_IG11, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB18, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP (G_M11011_IG11,ins#0,ofs#0) label Added IP mapping: 0x0013 STACK_EMPTY (G_M11011_IG11,ins#0,ofs#0) label Generating: N226 (???,???) [000120] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA Generating: N228 ( 14, 5) [000040] H-CXG------ u40 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG rax Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Mapped BB18 to G_M11011_IG11 IN0026: call CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE Byref regs: 0000 {} => 0001 {rax} Byref regs: 0001 {rax} => 0000 {} Scope info: ignoring block end Variable Live Range History Dump for BB18 V00 TypeCtx: rbp[16] (1 slot) [(G_M11011_IG04,ins#0,ofs#0), ...] =============== Generating BB16 [0015] [???..???) -> BB19,BB21 (cond), preds={BB06,BB18} succs={BB21,BB19} flags=0x00000000.10088031: i LIR internal label hascall gcsafe BB16 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M11011_BB16: Saved: G_M11011_IG11: ; offs=0x0000AE, size=0x0005, bbWeight=0, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB18 [0017], byref Created: G_M11011_IG12: ; offs=0x0000B3, size=0x0000, bbWeight=0.20, gcrefRegs=0000 {} Label: G_M11011_IG12, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB16, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP (G_M11011_IG12,ins#0,ofs#0) label Added IP mapping: 0x0013 STACK_EMPTY (G_M11011_IG12,ins#0,ofs#0) label Generating: N154 (???,???) [000121] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA Generating: N156 ( 3, 2) [000090] ----------- t90 = LCL_VAR long V05 tmp4 rax REG rax Mapped BB16 to G_M11011_IG12 IN0027: mov rax, qword ptr [V05 rbp-0x30] /--* t90 long Generating: N158 ( 4, 3) [000039] -c--------- t39 = * LEA(b+8) byref REG NA /--* t39 byref Generating: N160 ( 6, 5) [000038] V---GO----- t38 = * IND long REG rax IN0028: mov rax, qword ptr [rax+0x08] /--* t38 long Generating: N162 ( 9, 8) [000044] -c--------- t44 = * LEA(b+6) long REG NA /--* t44 long Generating: N164 ( 9, 8) [000045] ---XGO----- t45 = * IND long REG rax IN0029: mov rax, qword ptr [rax+0x06] /--* t45 long Generating: N166 ( 13, 11) [000097] DA-XGO----- * STORE_LCL_VAR long V06 tmp5 NA REG NA IN002a: mov qword ptr [V06 rbp-0x38], rax genIPmappingAdd: ignoring duplicate IL offset 0x13 Generating: N168 (???,???) [000122] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA Generating: N170 ( 1, 4) [000099] H---------- t99 = CNS_INT(h) long 0x4000000000420458 global ptr REG rax IN002b: lea rax, [(reloc 0x4000000000420458)] /--* t99 long Generating: N172 ( 5, 7) [000100] DA--------- * STORE_LCL_VAR long V07 tmp6 NA REG NA IN002c: mov qword ptr [V07 rbp-0x40], rax Generating: N174 ( 3, 2) [000101] ----------- t101 = LCL_VAR long V07 tmp6 rax REG rax IN002d: mov rax, qword ptr [V07 rbp-0x40] /--* t101 long Generating: N176 ( 9, 10) [000105] -c--------- t105 = * LEA(b+-8) long REG NA /--* t105 long Generating: N178 ( 11, 12) [000106] nA--G------ t106 = * IND long REG NA Generating: N180 ( 1, 1) [000107] -c--------- t107 = CNS_INT long 0 REG NA /--* t106 long +--* t107 long Generating: N182 ( 13, 14) [000108] -A--G------ * CMP void REG NA IN002e: cmp qword ptr [rax-0x08], 0 Generating: N184 ( 15, 16) [000109] -A--G------ JCC void cond=UEQ REG NA IN002f: je L_M11011_BB19 Scope info: ignoring block end Variable Live Range History Dump for BB16 V00 TypeCtx: rbp[16] (1 slot) [(G_M11011_IG04,ins#0,ofs#0), ...] =============== Generating BB21 [0020] [???..???) -> BB19 (always), preds={BB16} succs={BB19} flags=0x00000100.00002021: LIR rare internal q BB21 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M11011_BB21: Adding label due to BB weight difference: BBJ_COND BB16 with weight 20 different from BB21 with weight 0 Saved: G_M11011_IG12: ; offs=0x0000B3, size=0x002A, bbWeight=0.20, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB16 [0015], byref Created: G_M11011_IG13: ; offs=0x0000DD, size=0x0000, bbWeight=0, gcrefRegs=0000 {} Label: G_M11011_IG13, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB21, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP (G_M11011_IG13,ins#0,ofs#0) label Added IP mapping: 0x0013 STACK_EMPTY (G_M11011_IG13,ins#0,ofs#0) label Generating: N232 (???,???) [000123] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA Generating: N234 ( 14, 5) [000032] H-CXG------ u32 = CALL help byref CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE REG rax Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Mapped BB21 to G_M11011_IG13 IN0030: call CORINFO_HELP_READYTORUN_NONGCSTATIC_BASE Byref regs: 0000 {} => 0001 {rax} Byref regs: 0001 {rax} => 0000 {} Scope info: ignoring block end Variable Live Range History Dump for BB21 V00 TypeCtx: rbp[16] (1 slot) [(G_M11011_IG04,ins#0,ofs#0), ...] =============== Generating BB19 [0018] [013..???) -> BB03 (always), preds={BB16,BB21} succs={BB03} flags=0x00000100.10088031: i LIR internal label hascall gcsafe q BB19 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M11011_BB19: Saved: G_M11011_IG13: ; offs=0x0000DD, size=0x0005, bbWeight=0, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB21 [0020], byref Created: G_M11011_IG14: ; offs=0x0000E2, size=0x0000, bbWeight=0.20, gcrefRegs=0000 {} Label: G_M11011_IG14, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB19, IL range [013..???) ILC: C:\work\runtime\src\coreclr\jit\scopeinfo.cpp:1566 ILC: Assertion failed 'lastBlockILEndOffset < beginOffs' in 'TestEntrypoint:Test_Ldftn_GenericOverReferenceType_ClassAGenericValuetype_GenericOverConstrainedType_NonGeneric_NormalMethod[System.__Canon,System.__Canon]()' during 'Generate code' (IL size 47; hash 0x710bd4fc; MinOpts)