; Assembly listing for method Vector128WithLower.TestClass:byte_GetUpper(System.Runtime.Intrinsics.Vector128`1[Byte]):System.Runtime.Intrinsics.Vector64`1[Byte]
; Emitting BLENDED_CODE for generic ARM64 CPU - Windows
; optimized code
; fp based frame
; partially interruptible
; Final local variable assignments
;
;  V00 arg0         [V00    ] (  3,  3   )  simd16  ->  [fp+0x20]   HFA(simd16)  do-not-enreg[XS] addr-exposed
;# V01 OutArgs      [V01    ] (  1,  1   )  lclBlk ( 0) [sp+0x00]   "OutgoingArgSpace"
;  V02 tmp1         [V02,T01] (  2,  2   )  double  ->   d0         "Inline return value spill temp"
;  V03 tmp2         [V03    ] (  2,  4   )  simd16  ->  [fp+0x10]   HFA(simd16)  do-not-enreg[XS] addr-exposed ld-addr-op overlapping-fields "Inlining Arg"
;  V04 tmp3         [V04,T00] (  2,  2   )   byref  ->   x0         "Inline stloc first use temp"
;
; Lcl frame size = 32

G_M46486_IG01:
        A9BD7BFD          stp     fp, lr, [sp,#-48]!
        910003FD          mov     fp, sp
        3D800BA0          str     q0, [fp,#32]	// [V00 arg0]
						;; bbWeight=1    PerfScore 2.50
G_M46486_IG02:
        3DC00BA0          ldr     q0, [fp,#32]
        3D8007A0          str     q0, [fp,#16]	// [V03 tmp2]
        910043A0          add     x0, fp, #16	// [V03 tmp2]
        FD400400          ldr     d0, [x0,#8]
						;; bbWeight=1    PerfScore 6.50
G_M46486_IG03:
        A8C37BFD          ldp     fp, lr, [sp],#48
        D65F03C0          ret     lr
						;; bbWeight=1    PerfScore 2.00

; Total bytes of code 36, prolog size 8, PerfScore 14.60, (MethodHash=6f6d4a69) for method Vector128WithLower.TestClass:byte_GetUpper(System.Runtime.Intrinsics.Vector128`1[Byte]):System.Runtime.Intrinsics.Vector64`1[Byte]
; ============================================================

byte : <9, 10, 11, 12, 13, 14, 15, 16>
; Assembly listing for method Vector128WithLower.TestClass:sbyte_GetUpper(System.Runtime.Intrinsics.Vector128`1[SByte]):System.Runtime.Intrinsics.Vector64`1[SByte]
; Emitting BLENDED_CODE for generic ARM64 CPU - Windows
; optimized code
; fp based frame
; partially interruptible
; Final local variable assignments
;
;  V00 arg0         [V00    ] (  3,  3   )  simd16  ->  [fp+0x20]   HFA(simd16)  do-not-enreg[XS] addr-exposed
;# V01 OutArgs      [V01    ] (  1,  1   )  lclBlk ( 0) [sp+0x00]   "OutgoingArgSpace"
;  V02 tmp1         [V02,T01] (  2,  2   )  double  ->   d0         "Inline return value spill temp"
;  V03 tmp2         [V03    ] (  2,  4   )  simd16  ->  [fp+0x10]   HFA(simd16)  do-not-enreg[XS] addr-exposed ld-addr-op overlapping-fields "Inlining Arg"
;  V04 tmp3         [V04,T00] (  2,  2   )   byref  ->   x0         "Inline stloc first use temp"
;
; Lcl frame size = 32

G_M58277_IG01:
        A9BD7BFD          stp     fp, lr, [sp,#-48]!
        910003FD          mov     fp, sp
        3D800BA0          str     q0, [fp,#32]	// [V00 arg0]
						;; bbWeight=1    PerfScore 2.50
G_M58277_IG02:
        3DC00BA0          ldr     q0, [fp,#32]
        3D8007A0          str     q0, [fp,#16]	// [V03 tmp2]
        910043A0          add     x0, fp, #16	// [V03 tmp2]
        FD400400          ldr     d0, [x0,#8]
						;; bbWeight=1    PerfScore 6.50
G_M58277_IG03:
        A8C37BFD          ldp     fp, lr, [sp],#48
        D65F03C0          ret     lr
						;; bbWeight=1    PerfScore 2.00

; Total bytes of code 36, prolog size 8, PerfScore 14.60, (MethodHash=136a1c5a) for method Vector128WithLower.TestClass:sbyte_GetUpper(System.Runtime.Intrinsics.Vector128`1[SByte]):System.Runtime.Intrinsics.Vector64`1[SByte]
; ============================================================

sbyte : <9, 10, 11, 12, 13, 14, 15, 16>
; Assembly listing for method Vector128WithLower.TestClass:short_GetUpper(System.Runtime.Intrinsics.Vector128`1[Int16]):System.Runtime.Intrinsics.Vector64`1[Int16]
; Emitting BLENDED_CODE for generic ARM64 CPU - Windows
; optimized code
; fp based frame
; partially interruptible
; Final local variable assignments
;
;  V00 arg0         [V00    ] (  3,  3   )  simd16  ->  [fp+0x20]   HFA(simd16)  do-not-enreg[XS] addr-exposed
;# V01 OutArgs      [V01    ] (  1,  1   )  lclBlk ( 0) [sp+0x00]   "OutgoingArgSpace"
;  V02 tmp1         [V02,T01] (  2,  2   )  double  ->   d0         "Inline return value spill temp"
;  V03 tmp2         [V03    ] (  2,  4   )  simd16  ->  [fp+0x10]   HFA(simd16)  do-not-enreg[XS] addr-exposed ld-addr-op overlapping-fields "Inlining Arg"
;  V04 tmp3         [V04,T00] (  2,  2   )   byref  ->   x0         "Inline stloc first use temp"
;
; Lcl frame size = 32

G_M494_IG01:
        A9BD7BFD          stp     fp, lr, [sp,#-48]!
        910003FD          mov     fp, sp
        3D800BA0          str     q0, [fp,#32]	// [V00 arg0]
						;; bbWeight=1    PerfScore 2.50
G_M494_IG02:
        3DC00BA0          ldr     q0, [fp,#32]
        3D8007A0          str     q0, [fp,#16]	// [V03 tmp2]
        910043A0          add     x0, fp, #16	// [V03 tmp2]
        FD400400          ldr     d0, [x0,#8]
						;; bbWeight=1    PerfScore 6.50
G_M494_IG03:
        A8C37BFD          ldp     fp, lr, [sp],#48
        D65F03C0          ret     lr
						;; bbWeight=1    PerfScore 2.00

; Total bytes of code 36, prolog size 8, PerfScore 14.60, (MethodHash=0563fe11) for method Vector128WithLower.TestClass:short_GetUpper(System.Runtime.Intrinsics.Vector128`1[Int16]):System.Runtime.Intrinsics.Vector64`1[Int16]
; ============================================================

short : <5, 6, 7, 8>
; Assembly listing for method Vector128WithLower.TestClass:ushort_GetUpper(System.Runtime.Intrinsics.Vector128`1[UInt16]):System.Runtime.Intrinsics.Vector64`1[UInt16]
; Emitting BLENDED_CODE for generic ARM64 CPU - Windows
; optimized code
; fp based frame
; partially interruptible
; Final local variable assignments
;
;  V00 arg0         [V00    ] (  3,  3   )  simd16  ->  [fp+0x20]   HFA(simd16)  do-not-enreg[XS] addr-exposed
;# V01 OutArgs      [V01    ] (  1,  1   )  lclBlk ( 0) [sp+0x00]   "OutgoingArgSpace"
;  V02 tmp1         [V02,T01] (  2,  2   )  double  ->   d0         "Inline return value spill temp"
;  V03 tmp2         [V03    ] (  2,  4   )  simd16  ->  [fp+0x10]   HFA(simd16)  do-not-enreg[XS] addr-exposed ld-addr-op overlapping-fields "Inlining Arg"
;  V04 tmp3         [V04,T00] (  2,  2   )   byref  ->   x0         "Inline stloc first use temp"
;
; Lcl frame size = 32

G_M55451_IG01:
        A9BD7BFD          stp     fp, lr, [sp,#-48]!
        910003FD          mov     fp, sp
        3D800BA0          str     q0, [fp,#32]	// [V00 arg0]
						;; bbWeight=1    PerfScore 2.50
G_M55451_IG02:
        3DC00BA0          ldr     q0, [fp,#32]
        3D8007A0          str     q0, [fp,#16]	// [V03 tmp2]
        910043A0          add     x0, fp, #16	// [V03 tmp2]
        FD400400          ldr     d0, [x0,#8]
						;; bbWeight=1    PerfScore 6.50
G_M55451_IG03:
        A8C37BFD          ldp     fp, lr, [sp],#48
        D65F03C0          ret     lr
						;; bbWeight=1    PerfScore 2.00

; Total bytes of code 36, prolog size 8, PerfScore 14.60, (MethodHash=62bf2764) for method Vector128WithLower.TestClass:ushort_GetUpper(System.Runtime.Intrinsics.Vector128`1[UInt16]):System.Runtime.Intrinsics.Vector64`1[UInt16]
; ============================================================

ushort : <5, 6, 7, 8>
; Assembly listing for method Vector128WithLower.TestClass:int_GetUpper(System.Runtime.Intrinsics.Vector128`1[Int32]):System.Runtime.Intrinsics.Vector64`1[Int32]
; Emitting BLENDED_CODE for generic ARM64 CPU - Windows
; optimized code
; fp based frame
; partially interruptible
; Final local variable assignments
;
;  V00 arg0         [V00    ] (  3,  3   )  simd16  ->  [fp+0x20]   HFA(simd16)  do-not-enreg[XS] addr-exposed
;# V01 OutArgs      [V01    ] (  1,  1   )  lclBlk ( 0) [sp+0x00]   "OutgoingArgSpace"
;  V02 tmp1         [V02,T01] (  2,  2   )  double  ->   d0         "Inline return value spill temp"
;  V03 tmp2         [V03    ] (  2,  4   )  simd16  ->  [fp+0x10]   HFA(simd16)  do-not-enreg[XS] addr-exposed ld-addr-op overlapping-fields "Inlining Arg"
;  V04 tmp3         [V04,T00] (  2,  2   )   byref  ->   x0         "Inline stloc first use temp"
;
; Lcl frame size = 32

G_M27343_IG01:
        A9BD7BFD          stp     fp, lr, [sp,#-48]!
        910003FD          mov     fp, sp
        3D800BA0          str     q0, [fp,#32]	// [V00 arg0]
						;; bbWeight=1    PerfScore 2.50
G_M27343_IG02:
        3DC00BA0          ldr     q0, [fp,#32]
        3D8007A0          str     q0, [fp,#16]	// [V03 tmp2]
        910043A0          add     x0, fp, #16	// [V03 tmp2]
        FD400400          ldr     d0, [x0,#8]
						;; bbWeight=1    PerfScore 6.50
G_M27343_IG03:
        A8C37BFD          ldp     fp, lr, [sp],#48
        D65F03C0          ret     lr
						;; bbWeight=1    PerfScore 2.00

; Total bytes of code 36, prolog size 8, PerfScore 14.60, (MethodHash=b1209530) for method Vector128WithLower.TestClass:int_GetUpper(System.Runtime.Intrinsics.Vector128`1[Int32]):System.Runtime.Intrinsics.Vector64`1[Int32]
; ============================================================

int : <3, 4>
; Assembly listing for method Vector128WithLower.TestClass:uint_GetUpper(System.Runtime.Intrinsics.Vector128`1[UInt32]):System.Runtime.Intrinsics.Vector64`1[UInt32]
; Emitting BLENDED_CODE for generic ARM64 CPU - Windows
; optimized code
; fp based frame
; partially interruptible
; Final local variable assignments
;
;  V00 arg0         [V00    ] (  3,  3   )  simd16  ->  [fp+0x20]   HFA(simd16)  do-not-enreg[XS] addr-exposed
;# V01 OutArgs      [V01    ] (  1,  1   )  lclBlk ( 0) [sp+0x00]   "OutgoingArgSpace"
;  V02 tmp1         [V02,T01] (  2,  2   )  double  ->   d0         "Inline return value spill temp"
;  V03 tmp2         [V03    ] (  2,  4   )  simd16  ->  [fp+0x10]   HFA(simd16)  do-not-enreg[XS] addr-exposed ld-addr-op overlapping-fields "Inlining Arg"
;  V04 tmp3         [V04,T00] (  2,  2   )   byref  ->   x0         "Inline stloc first use temp"
;
; Lcl frame size = 32

G_M39866_IG01:
        A9BD7BFD          stp     fp, lr, [sp,#-48]!
        910003FD          mov     fp, sp
        3D800BA0          str     q0, [fp,#32]	// [V00 arg0]
						;; bbWeight=1    PerfScore 2.50
G_M39866_IG02:
        3DC00BA0          ldr     q0, [fp,#32]
        3D8007A0          str     q0, [fp,#16]	// [V03 tmp2]
        910043A0          add     x0, fp, #16	// [V03 tmp2]
        FD400400          ldr     d0, [x0,#8]
						;; bbWeight=1    PerfScore 6.50
G_M39866_IG03:
        A8C37BFD          ldp     fp, lr, [sp],#48
        D65F03C0          ret     lr
						;; bbWeight=1    PerfScore 2.00

; Total bytes of code 36, prolog size 8, PerfScore 14.60, (MethodHash=3af56445) for method Vector128WithLower.TestClass:uint_GetUpper(System.Runtime.Intrinsics.Vector128`1[UInt32]):System.Runtime.Intrinsics.Vector64`1[UInt32]
; ============================================================

uint : <3, 4>
; Assembly listing for method Vector128WithLower.TestClass:long_GetUpper(System.Runtime.Intrinsics.Vector128`1[Int64]):System.Runtime.Intrinsics.Vector64`1[Int64]
; Emitting BLENDED_CODE for generic ARM64 CPU - Windows
; optimized code
; fp based frame
; partially interruptible
; Final local variable assignments
;
;  V00 arg0         [V00    ] (  3,  3   )  simd16  ->  [fp+0x20]   HFA(simd16)  do-not-enreg[XS] addr-exposed
;# V01 OutArgs      [V01    ] (  1,  1   )  lclBlk ( 0) [sp+0x00]   "OutgoingArgSpace"
;  V02 tmp1         [V02,T01] (  2,  2   )  double  ->   d0         "Inline return value spill temp"
;  V03 tmp2         [V03    ] (  2,  4   )  simd16  ->  [fp+0x10]   HFA(simd16)  do-not-enreg[XS] addr-exposed ld-addr-op overlapping-fields "Inlining Arg"
;  V04 tmp3         [V04,T00] (  2,  2   )   byref  ->   x0         "Inline stloc first use temp"
;
; Lcl frame size = 32

G_M36278_IG01:
        A9BD7BFD          stp     fp, lr, [sp,#-48]!
        910003FD          mov     fp, sp
        3D800BA0          str     q0, [fp,#32]	// [V00 arg0]
						;; bbWeight=1    PerfScore 2.50
G_M36278_IG02:
        3DC00BA0          ldr     q0, [fp,#32]
        3D8007A0          str     q0, [fp,#16]	// [V03 tmp2]
        910043A0          add     x0, fp, #16	// [V03 tmp2]
        FD400400          ldr     d0, [x0,#8]
						;; bbWeight=1    PerfScore 6.50
G_M36278_IG03:
        A8C37BFD          ldp     fp, lr, [sp],#48
        D65F03C0          ret     lr
						;; bbWeight=1    PerfScore 2.00

; Total bytes of code 36, prolog size 8, PerfScore 14.60, (MethodHash=a1e47249) for method Vector128WithLower.TestClass:long_GetUpper(System.Runtime.Intrinsics.Vector128`1[Int64]):System.Runtime.Intrinsics.Vector64`1[Int64]
; ============================================================

long : <2>
; Assembly listing for method Vector128WithLower.TestClass:ulong_GetUpper(System.Runtime.Intrinsics.Vector128`1[UInt64]):System.Runtime.Intrinsics.Vector64`1[UInt64]
; Emitting BLENDED_CODE for generic ARM64 CPU - Windows
; optimized code
; fp based frame
; partially interruptible
; Final local variable assignments
;
;  V00 arg0         [V00    ] (  3,  3   )  simd16  ->  [fp+0x20]   HFA(simd16)  do-not-enreg[XS] addr-exposed
;# V01 OutArgs      [V01    ] (  1,  1   )  lclBlk ( 0) [sp+0x00]   "OutgoingArgSpace"
;  V02 tmp1         [V02,T01] (  2,  2   )  double  ->   d0         "Inline return value spill temp"
;  V03 tmp2         [V03    ] (  2,  4   )  simd16  ->  [fp+0x10]   HFA(simd16)  do-not-enreg[XS] addr-exposed ld-addr-op overlapping-fields "Inlining Arg"
;  V04 tmp3         [V04,T00] (  2,  2   )   byref  ->   x0         "Inline stloc first use temp"
;
; Lcl frame size = 32

G_M45891_IG01:
        A9BD7BFD          stp     fp, lr, [sp,#-48]!
        910003FD          mov     fp, sp
        3D800BA0          str     q0, [fp,#32]	// [V00 arg0]
						;; bbWeight=1    PerfScore 2.50
G_M45891_IG02:
        3DC00BA0          ldr     q0, [fp,#32]
        3D8007A0          str     q0, [fp,#16]	// [V03 tmp2]
        910043A0          add     x0, fp, #16	// [V03 tmp2]
        FD400400          ldr     d0, [x0,#8]
						;; bbWeight=1    PerfScore 6.50
G_M45891_IG03:
        A8C37BFD          ldp     fp, lr, [sp],#48
        D65F03C0          ret     lr
						;; bbWeight=1    PerfScore 2.00

; Total bytes of code 36, prolog size 8, PerfScore 14.60, (MethodHash=87b94cbc) for method Vector128WithLower.TestClass:ulong_GetUpper(System.Runtime.Intrinsics.Vector128`1[UInt64]):System.Runtime.Intrinsics.Vector64`1[UInt64]
; ============================================================

ulong : <2>
; Assembly listing for method Vector128WithLower.TestClass:float_GetUpper(System.Runtime.Intrinsics.Vector128`1[Single]):System.Runtime.Intrinsics.Vector64`1[Single]
; Emitting BLENDED_CODE for generic ARM64 CPU - Windows
; optimized code
; fp based frame
; partially interruptible
; Final local variable assignments
;
;  V00 arg0         [V00    ] (  3,  3   )  simd16  ->  [fp+0x20]   HFA(simd16)  do-not-enreg[XS] addr-exposed
;# V01 OutArgs      [V01    ] (  1,  1   )  lclBlk ( 0) [sp+0x00]   "OutgoingArgSpace"
;  V02 tmp1         [V02,T01] (  2,  2   )  double  ->   d0         "Inline return value spill temp"
;  V03 tmp2         [V03    ] (  2,  4   )  simd16  ->  [fp+0x10]   HFA(simd16)  do-not-enreg[XS] addr-exposed ld-addr-op overlapping-fields "Inlining Arg"
;  V04 tmp3         [V04,T00] (  2,  2   )   byref  ->   x0         "Inline stloc first use temp"
;
; Lcl frame size = 32

G_M44108_IG01:
        A9BD7BFD          stp     fp, lr, [sp,#-48]!
        910003FD          mov     fp, sp
        3D800BA0          str     q0, [fp,#32]	// [V00 arg0]
						;; bbWeight=1    PerfScore 2.50
G_M44108_IG02:
        3DC00BA0          ldr     q0, [fp,#32]
        3D8007A0          str     q0, [fp,#16]	// [V03 tmp2]
        910043A0          add     x0, fp, #16	// [V03 tmp2]
        FD400400          ldr     d0, [x0,#8]
						;; bbWeight=1    PerfScore 6.50
G_M44108_IG03:
        A8C37BFD          ldp     fp, lr, [sp],#48
        D65F03C0          ret     lr
						;; bbWeight=1    PerfScore 2.00

; Total bytes of code 36, prolog size 8, PerfScore 14.60, (MethodHash=32d253b3) for method Vector128WithLower.TestClass:float_GetUpper(System.Runtime.Intrinsics.Vector128`1[Single]):System.Runtime.Intrinsics.Vector64`1[Single]
; ============================================================

float : <3, 4>
; Assembly listing for method Vector128WithLower.TestClass:double_GetUpper(System.Runtime.Intrinsics.Vector128`1[Double]):System.Runtime.Intrinsics.Vector64`1[Double]
; Emitting BLENDED_CODE for generic ARM64 CPU - Windows
; optimized code
; fp based frame
; partially interruptible
; Final local variable assignments
;
;  V00 arg0         [V00    ] (  3,  3   )  simd16  ->  [fp+0x20]   HFA(simd16)  do-not-enreg[XS] addr-exposed
;# V01 OutArgs      [V01    ] (  1,  1   )  lclBlk ( 0) [sp+0x00]   "OutgoingArgSpace"
;  V02 tmp1         [V02,T01] (  2,  2   )  double  ->   d0         "Inline return value spill temp"
;  V03 tmp2         [V03    ] (  2,  4   )  simd16  ->  [fp+0x10]   HFA(simd16)  do-not-enreg[XS] addr-exposed ld-addr-op overlapping-fields "Inlining Arg"
;  V04 tmp3         [V04,T00] (  2,  2   )   byref  ->   x0         "Inline stloc first use temp"
;
; Lcl frame size = 32

G_M31945_IG01:
        A9BD7BFD          stp     fp, lr, [sp,#-48]!
        910003FD          mov     fp, sp
        3D800BA0          str     q0, [fp,#32]	// [V00 arg0]
						;; bbWeight=1    PerfScore 2.50
G_M31945_IG02:
        3DC00BA0          ldr     q0, [fp,#32]
        3D8007A0          str     q0, [fp,#16]	// [V03 tmp2]
        910043A0          add     x0, fp, #16	// [V03 tmp2]
        FD400400          ldr     d0, [x0,#8]
						;; bbWeight=1    PerfScore 6.50
G_M31945_IG03:
        A8C37BFD          ldp     fp, lr, [sp],#48
        D65F03C0          ret     lr
						;; bbWeight=1    PerfScore 2.00

; Total bytes of code 36, prolog size 8, PerfScore 14.60, (MethodHash=b3938336) for method Vector128WithLower.TestClass:double_GetUpper(System.Runtime.Intrinsics.Vector128`1[Double]):System.Runtime.Intrinsics.Vector64`1[Double]
; ============================================================

double : <2>