****** START compiling Test.Program:Main(System.String[]):int (MethodHash=efe0a8a8)
Generating code for Windows x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC  = false
OPTIONS: compProcedureSplitting   = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: No PGO data
IL to import:
IL_0000  02                ldarg.0     
IL_0001  8e                ldlen       
IL_0002  69                conv.i4     
IL_0003  1f 2a             ldc.i4.s     0x2A
IL_0005  28 10 00 00 0a    call         0xA000010
IL_000a  2a                ret         

lvaSetClass: setting class for V00 to (00007FFAD3A2F468) System.String[] 
Arg #0    passed in register(s) rcx

lvaGrabTemp returning 1 (V01 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
;  V00 arg0              ref  class-hnd
;  V01 OutArgs        lclBlk <na>  "OutgoingArgSpace"
*************** In compInitDebuggingInfo() for Test.Program:Main(System.String[]):int
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 1
    	VarNum 	LVNum 	      Name 	Beg 	End
 0: 	00h 	00h 	  V00 arg0 	000h   	00Bh
info.compStmtOffsetsCount    = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Test.Program:Main(System.String[]):int
Jump targets:
  none
New Basic Block BB01 [0000] created.
BB01 [000..00B)
IL Code Size,Instr   11,   6, Basic Block count   1, Local Variable Num,Ref count   2,  1 for method Test.Program:Main(System.String[]):int
OPTIONS: opts.MinOpts() == false
Basic block list for 'Test.Program:Main(System.String[]):int'

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Pre-import

*************** Finishing PHASE Pre-import

*************** Starting PHASE Profile incorporation
BBOPT set, but no profile data available (hr=80004001)

*************** Finishing PHASE Profile incorporation [no changes]

*************** Starting PHASE Importation
*************** In impImport() for Test.Program:Main(System.String[]):int

impImportBlockPending for BB01

Importing BB01 (PC=000) of 'Test.Program:Main(System.String[]):int'
    [ 0]   0 (0x000) ldarg.0
    [ 1]   1 (0x001) ldlen
    [ 1]   2 (0x002) conv.i4
    [ 1]   3 (0x003) ldc.i4.s 42
    [ 2]   5 (0x005) call 0A000010
 (Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT)
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0

info.compCompHnd->canTailCall returned false for call [000003]


STMT00000 ( 0x000[E-] ... ??? )
               [000003] I-CXG-------              *  CALL      int    System.Math.Max (exactContextHnd=0x00007FFAD3BE5EF1)
               [000001] ---X-------- arg0         +--*  ARR_LENGTH int   
               [000000] ------------              |  \--*  LCL_VAR   ref    V00 arg0         
               [000002] ------------ arg1         \--*  CNS_INT   int    42

    [ 1]  10 (0x00a) ret

STMT00001 ( 0x000[E-] ... ??? )
               [000005] --C---------              *  RETURN    int   
               [000004] --C---------              \--*  RET_EXPR  int   (inl return expr [000003])

*************** Finishing PHASE Importation
Trees after Importation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00A )
               [000003] I-CXG-------              *  CALL      int    System.Math.Max (exactContextHnd=0x00007FFAD3BE5EF1)
               [000001] ---X-------- arg0         +--*  ARR_LENGTH int   
               [000000] ------------              |  \--*  LCL_VAR   ref    V00 arg0         
               [000002] ------------ arg1         \--*  CNS_INT   int    42

***** BB01
STMT00001 ( 0x000[E-] ... ??? )
               [000005] --C---------              *  RETURN    int   
               [000004] --C---------              \--*  RET_EXPR  int   (inl return expr [000003])

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Expand patchpoints

 -- no patchpoints to transform

*************** Finishing PHASE Expand patchpoints [no changes]

*************** Starting PHASE Indirect call transform

 -- no candidates to transform

*************** Finishing PHASE Indirect call transform [no changes]

*************** Starting PHASE Post-import

*************** Finishing PHASE Post-import

*************** Starting PHASE Morph - Init

New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)

*************** In fgPostImportationCleanup

*************** Finishing PHASE Morph - Init
*************** In fgDebugCheckBBlist

*************** Starting PHASE Morph - Inlining
Expanding INLINE_CANDIDATE in statement STMT00000 in BB01:
STMT00000 ( 0x000[E-] ... 0x00A )
               [000003] I-CXG-------              *  CALL      int    System.Math.Max (exactContextHnd=0x00007FFAD3BE5EF1)
               [000001] ---X-------- arg0         +--*  ARR_LENGTH int   
               [000000] ------------              |  \--*  LCL_VAR   ref    V00 arg0         
               [000002] ------------ arg1         \--*  CNS_INT   int    42

Argument #0: has side effects
               [000001] ---X--------              *  ARR_LENGTH int   
               [000000] ------------              \--*  LCL_VAR   ref    V00 arg0         


Argument #1: is a constant
               [000002] ------------              *  CNS_INT   int    42

INLINER: inlineInfo.tokenLookupContextHandle for System.Math:Max(int,int):int set to 0x00007FFAD3BE5EF1:

Invoking compiler for the inlinee method System.Math:Max(int,int):int :
IL to import:
IL_0000  02                ldarg.0     
IL_0001  03                ldarg.1     
IL_0002  2f 02             bge.s        2 (IL_0006)
IL_0004  03                ldarg.1     
IL_0005  2a                ret         
IL_0006  02                ldarg.0     
IL_0007  2a                ret         

INLINER impTokenLookupContextHandle for System.Math:Max(int,int):int is 0x00007FFAD3BE5EF1.
*************** In compInitDebuggingInfo() for System.Math:Max(int,int):int
info.compStmtOffsetsCount    = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for System.Math:Max(int,int):int
Jump targets:
  IL_0006
New Basic Block BB02 [0001] created.
BB02 [000..004)
New Basic Block BB03 [0002] created.
BB03 [004..006)
New Basic Block BB04 [0003] created.
BB04 [006..008)

lvaGrabTemp returning 2 (V02 tmp1) (a long lifetime temp) called for Inline return value spill temp.
Basic block list for 'System.Math:Max(int,int):int'

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB02 [0001]  1                           100       [000..004)-> BB04 ( cond )                     
BB03 [0002]  1                           100       [004..006)        (return)                     
BB04 [0003]  1                           100       [006..008)        (return)                     
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Inline @[000003] Starting PHASE Pre-import

*************** Inline @[000003] Finishing PHASE Pre-import

*************** Inline @[000003] Starting PHASE Profile incorporation
Have static profile data: 3 schema records (schema at 000002EB2F330BC8, data at 000002EB2F330BC0)
Profile summary: 8 runs, 0 block probes, 2 edge probes, 0 class profiles, 0 other records

Reconstructing block counts from sparse edge instrumentation
... adding known edge BB03 -> BB02: weight 58379
... adding known edge BB04 -> BB02: weight 101276

New BlockSet epoch 2, # of blocks (including unused BB00): 5, bitset array size: 1 (short)
 ... unknown edge BB02 -> BB04
 ... unknown edge BB02 -> BB03

Solver: 3 blocks, 3 unknown; 4 edges, 2 unknown, 0 zero (and so ignored)

Pass [1]: 3 unknown blocks, 2 unknown edges
BB04: 1 incoming unknown, 0 outgoing unknown
BB04: all outgoing edge weights known, summming...
  BB04 -> BB02 has weight 101276
BB04: all outgoing edge weights known, sum is 101276
BB02 -> BB04: target block weight and all other incoming edge weights known, so weight is 101276
BB03: 1 incoming unknown, 0 outgoing unknown
BB03: all outgoing edge weights known, summming...
  BB03 -> BB02 has weight 58379
BB03: all outgoing edge weights known, sum is 58379
BB02 -> BB03: target block weight and all other incoming edge weights known, so weight is 58379
BB02: 0 incoming unknown, 0 outgoing unknown
BB02: all incoming edge weights known, summming...
  BB04 -> BB02 has weight 101276
  BB03 -> BB02 has weight 58379
BB02: all incoming edge weights known, sum is 159655

Solver: converged in 1 passes
Computing inlinee profile scale:
   ... call site not profiled, will use non-pgo weight to scale
   call site count 100 callee entry count 159655 scale 0.0006263506
Scaling inlinee blocks

*************** Inline @[000003] Finishing PHASE Profile incorporation
Trees after Profile incorporation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB02 [0001]  1                           100    100    [000..004)-> BB04 ( cond )                     IBC 
BB03 [0002]  1                            36.57  37    [004..006)        (return)                     IBC 
BB04 [0003]  1                            63.43  63    [006..008)        (return)                     IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB02 [000..004) -> BB04 (cond), preds={} succs={BB03,BB04}

------------ BB03 [004..006) (return), preds={} succs={}

------------ BB04 [006..008) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------

*************** Inline @[000003] Starting PHASE Importation
*************** In impImport() for System.Math:Max(int,int):int

impImportBlockPending for BB02

Importing BB02 (PC=000) of 'System.Math:Max(int,int):int'
    [ 0]   0 (0x000) ldarg.0
lvaGrabTemp returning 3 (V03 tmp2) called for Inlining Arg.

    [ 1]   1 (0x001) ldarg.1
    [ 2]   2 (0x002) bge.s

STMT00002 ( 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000009] ------------              *  JTRUE     void  
               [000008] ------------              \--*  GE        int   
               [000006] ------------                 +--*  LCL_VAR   int    V03 tmp2         
               [000007] ------------                 \--*  CNS_INT   int    42

impImportBlockPending for BB03

impImportBlockPending for BB04

Importing BB04 (PC=006) of 'System.Math:Max(int,int):int'
    [ 0]   6 (0x006) ldarg.0
    [ 1]   7 (0x007) ret

    Inlinee Return expression (before normalization)  =>
               [000010] ------------              *  LCL_VAR   int    V03 tmp2         


STMT00003 ( 0x006[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000012] -A----------              *  ASG       int   
               [000011] D------N----              +--*  LCL_VAR   int    V02 tmp1         
               [000010] ------------              \--*  LCL_VAR   int    V03 tmp2         


    Inlinee Return expression (after normalization) =>
               [000013] ------------              *  LCL_VAR   int    V02 tmp1         

Importing BB03 (PC=004) of 'System.Math:Max(int,int):int'
    [ 0]   4 (0x004) ldarg.1
    [ 1]   5 (0x005) ret

    Inlinee Return expression (before normalization)  =>
               [000014] ------------              *  CNS_INT   int    42


STMT00004 ( 0x004[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000016] -A----------              *  ASG       int   
               [000015] D------N----              +--*  LCL_VAR   int    V02 tmp1         
               [000014] ------------              \--*  CNS_INT   int    42


    Inlinee Return expression (after normalization) =>
               [000017] ------------              *  LCL_VAR   int    V02 tmp1         

*************** Inline @[000003] Finishing PHASE Importation
Trees after Importation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB02 [0001]  1                           100    100    [000..004)-> BB04 ( cond )                     i IBC 
BB03 [0002]  1                            36.57  37    [004..006)        (return)                     i IBC 
BB04 [0003]  1                            63.43  63    [006..008)        (return)                     i IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB02 [000..004) -> BB04 (cond), preds={} succs={BB03,BB04}

***** BB02
STMT00002 ( 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000009] ------------              *  JTRUE     void  
               [000008] ------------              \--*  GE        int   
               [000006] ------------                 +--*  LCL_VAR   int    V03 tmp2         
               [000007] ------------                 \--*  CNS_INT   int    42

------------ BB03 [004..006) (return), preds={} succs={}

***** BB03
STMT00004 ( 0x004[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000016] -A----------              *  ASG       int   
               [000015] D------N----              +--*  LCL_VAR   int    V02 tmp1         
               [000014] ------------              \--*  CNS_INT   int    42

------------ BB04 [006..008) (return), preds={} succs={}

***** BB04
STMT00003 ( 0x006[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000012] -A----------              *  ASG       int   
               [000011] D------N----              +--*  LCL_VAR   int    V02 tmp1         
               [000010] ------------              \--*  LCL_VAR   int    V03 tmp2         

-------------------------------------------------------------------------------------------------------------------

*************** Inline @[000003] Starting PHASE Expand patchpoints

 -- no patchpoints to transform

*************** Inline @[000003] Finishing PHASE Expand patchpoints [no changes]

*************** Inline @[000003] Starting PHASE Indirect call transform

 -- no candidates to transform

*************** Inline @[000003] Finishing PHASE Indirect call transform [no changes]

*************** Inline @[000003] Starting PHASE Post-import

*************** In fgPostImportationCleanup

*************** Inline @[000003] Finishing PHASE Post-import


----------- Statements (and blocks) added due to the inlining of call [000003] -----------

Arguments setup:
STMT00005 ( 0x000[E-] ... ??? )
               [000019] -A-X--------              *  ASG       int   
               [000018] D------N----              +--*  LCL_VAR   int    V03 tmp2         
               [000001] ---X--------              \--*  ARR_LENGTH int   
               [000000] ------------                 \--*  LCL_VAR   ref    V00 arg0         

Inlinee method body:New Basic Block BB05 [0004] created.

Convert bbJumpKind of BB03 to BBJ_ALWAYS to bottomBlock BB05

Convert bbJumpKind of BB04 to BBJ_NONE
fgInlineAppendStatements: no gc ref inline locals.

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB02 [0001]  1                             1    100    [000..001)-> BB04 ( cond )                     i IBC 
BB03 [0002]  1                             0.37  37    [000..001)-> BB05 (always)                     i IBC 
BB04 [0003]  1                             0.63  63    [000..001)                                     i IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB02 [000..001) -> BB04 (cond), preds={} succs={BB03,BB04}

***** BB02
STMT00002 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000009] ------------              *  JTRUE     void  
               [000008] ------------              \--*  GE        int   
               [000006] ------------                 +--*  LCL_VAR   int    V03 tmp2         
               [000007] ------------                 \--*  CNS_INT   int    42

------------ BB03 [000..001) -> BB05 (always), preds={} succs={BB05}

***** BB03
STMT00004 ( INL01 @ 0x004[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000016] -A----------              *  ASG       int   
               [000015] D------N----              +--*  LCL_VAR   int    V02 tmp1         
               [000014] ------------              \--*  CNS_INT   int    42

------------ BB04 [000..001), preds={} succs={BB05}

***** BB04
STMT00003 ( INL01 @ 0x006[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000012] -A----------              *  ASG       int   
               [000011] D------N----              +--*  LCL_VAR   int    V02 tmp1         
               [000010] ------------              \--*  LCL_VAR   int    V03 tmp2         

-------------------------------------------------------------------------------------------------------------------

Return expression for call at [000003] is
               [000017] ------------              *  LCL_VAR   int    V02 tmp1         
Successfully inlined System.Math:Max(int,int):int (8 IL bytes) (depth 1) [below ALWAYS_INLINE size]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Test.Program:Main(System.String[]):int' calling 'System.Math:Max(int,int):int'
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size'

Replacing the return expression placeholder [000004] with [000017]
               [000004] --C---------              *  RET_EXPR  int   (inl return expr [000017])

Inserting the inline return expression
               [000017] ------------              *  LCL_VAR   int    V02 tmp1         

**************** Inline Tree

Inlines into 06000005 [via ExtendedDefaultPolicy] Test.Program:Main(System.String[]):int:
  [INL01 IL=0005 TR=000003 0600055D] [INLINED: callee: below ALWAYS_INLINE size] System.Math:Max(int,int):int
Budget: initialTime=93, finalTime=95, initialBudget=930, currentBudget=930
Budget: initialSize=382, finalSize=382

*************** Finishing PHASE Morph - Inlining
Trees after Morph - Inlining

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1           [000..00B)                                     i idxlen 
BB02 [0001]  1                             1    100    [000..001)-> BB04 ( cond )                     i IBC 
BB03 [0002]  1                             0.37  37    [000..001)-> BB05 (always)                     i IBC 
BB04 [0003]  1                             0.63  63    [000..001)                                     i IBC 
BB05 [0004]  1                             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B), preds={} succs={BB02}

***** BB01
STMT00005 ( 0x000[E-] ... ??? )
               [000019] -A-X--------              *  ASG       int   
               [000018] D------N----              +--*  LCL_VAR   int    V03 tmp2         
               [000001] ---X--------              \--*  ARR_LENGTH int   
               [000000] ------------                 \--*  LCL_VAR   ref    V00 arg0         

------------ BB02 [000..001) -> BB04 (cond), preds={} succs={BB03,BB04}

***** BB02
STMT00002 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000009] ------------              *  JTRUE     void  
               [000008] ------------              \--*  GE        int   
               [000006] ------------                 +--*  LCL_VAR   int    V03 tmp2         
               [000007] ------------                 \--*  CNS_INT   int    42

------------ BB03 [000..001) -> BB05 (always), preds={} succs={BB05}

***** BB03
STMT00004 ( INL01 @ 0x004[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000016] -A----------              *  ASG       int   
               [000015] D------N----              +--*  LCL_VAR   int    V02 tmp1         
               [000014] ------------              \--*  CNS_INT   int    42

------------ BB04 [000..001), preds={} succs={BB05}

***** BB04
STMT00003 ( INL01 @ 0x006[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000012] -A----------              *  ASG       int   
               [000011] D------N----              +--*  LCL_VAR   int    V02 tmp1         
               [000010] ------------              \--*  LCL_VAR   int    V03 tmp2         

------------ BB05 [???..???) (return), preds={} succs={}

***** BB05
STMT00001 ( 0x000[E-] ... ??? )
               [000005] --C---------              *  RETURN    int   
               [000017] ------------              \--*  LCL_VAR   int    V02 tmp1         

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Allocate Objects
no newobjs in this method; punting

*************** Finishing PHASE Allocate Objects [no changes]

*************** Starting PHASE Morph - Add internal blocks

*************** After fgAddInternal()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1           [000..00B)                                     i idxlen 
BB02 [0001]  1                             1    100    [000..001)-> BB04 ( cond )                     i IBC 
BB03 [0002]  1                             0.37  37    [000..001)-> BB05 (always)                     i IBC 
BB04 [0003]  1                             0.63  63    [000..001)                                     i IBC 
BB05 [0004]  1                             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

*************** Finishing PHASE Morph - Add internal blocks

*************** Starting PHASE Remove empty try

*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty try [no changes]

*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty finally [no changes]

*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.

*************** Finishing PHASE Merge callfinally chains [no changes]

*************** Starting PHASE Clone finally
No EH in this method, no cloning.

*************** Finishing PHASE Clone finally [no changes]

*************** Starting PHASE Compute preds

Renumbering the basic blocks for fgComputePred

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1           [000..00B)                                     i idxlen 
BB02 [0001]  1                             1    100    [000..001)-> BB04 ( cond )                     i IBC 
BB03 [0002]  1                             0.37  37    [000..001)-> BB05 (always)                     i IBC 
BB04 [0003]  1                             0.63  63    [000..001)                                     i IBC 
BB05 [0004]  1                             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

*************** After renumbering the basic blocks
=============== No blocks renumbered!

New BlockSet epoch 3, # of blocks (including unused BB00): 6, bitset array size: 1 (short)

*************** In fgComputePreds()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1           [000..00B)                                     i idxlen 
BB02 [0001]  1                             1    100    [000..001)-> BB04 ( cond )                     i IBC 
BB03 [0002]  1                             0.37  37    [000..001)-> BB05 (always)                     i IBC 
BB04 [0003]  1                             0.63  63    [000..001)                                     i IBC 
BB05 [0004]  1                             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

Setting edge weights for BB01 -> BB02 to [0 .. 3.402823e+38]
Setting edge weights for BB02 -> BB04 to [0 .. 3.402823e+38]
Setting edge weights for BB02 -> BB03 to [0 .. 3.402823e+38]
Setting edge weights for BB03 -> BB05 to [0 .. 3.402823e+38]
Setting edge weights for BB04 -> BB05 to [0 .. 3.402823e+38]

*************** After fgComputePreds()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1           [000..00B)                                     i idxlen 
BB02 [0001]  1       BB01                  1    100    [000..001)-> BB04 ( cond )                     i IBC 
BB03 [0002]  1       BB02                  0.37  37    [000..001)-> BB05 (always)                     i IBC 
BB04 [0003]  1       BB02                  0.63  63    [000..001)                                     i IBC 
BB05 [0004]  2       BB03,BB04             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------


*************** Finishing PHASE Compute preds

*************** Starting PHASE Merge throw blocks

*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.

*************** Finishing PHASE Merge throw blocks [no changes]

*************** Starting PHASE Update flow graph early pass

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1           [000..00B)                                     i idxlen 
BB02 [0001]  1       BB01                  1    100    [000..001)-> BB04 ( cond )                     i IBC 
BB03 [0002]  1       BB02                  0.37  37    [000..001)-> BB05 (always)                     i IBC 
BB04 [0003]  1       BB02                  0.63  63    [000..001)                                     i IBC 
BB05 [0004]  2       BB03,BB04             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------


Compacting blocks BB01 and BB02:
*************** In fgDebugCheckBBlist

After updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB04 ( cond )                     i idxlen IBC 
BB03 [0002]  1       BB01                  0.37  37    [000..001)-> BB05 (always)                     i IBC 
BB04 [0003]  1       BB01                  0.63  63    [000..001)                                     i IBC 
BB05 [0004]  2       BB03,BB04             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
*************** In fgDebugCheckBBlist

*************** Finishing PHASE Update flow graph early pass

*************** Starting PHASE Morph - Promote Structs

*************** In fgResetImplicitByRefRefCount()
*************** In fgPromoteStructs()

lvaTable before fgPromoteStructs
; Initial local variable assignments
;
;  V00 arg0              ref  class-hnd
;  V01 OutArgs        lclBlk <na>  "OutgoingArgSpace"
;  V02 tmp1              int  "Inline return value spill temp"
;  V03 tmp2              int  "Inlining Arg"

lvaTable after fgPromoteStructs
; Initial local variable assignments
;
;  V00 arg0              ref  class-hnd
;  V01 OutArgs        lclBlk <na>  "OutgoingArgSpace"
;  V02 tmp1              int  "Inline return value spill temp"
;  V03 tmp2              int  "Inlining Arg"

*************** Finishing PHASE Morph - Promote Structs

*************** Starting PHASE Morph - Structs/AddrExp

*************** In fgMarkAddressExposedLocals()
LocalAddressVisitor visiting statement:
STMT00005 ( 0x000[E-] ... ??? )
               [000019] -A-X--------              *  ASG       int   
               [000018] D------N----              +--*  LCL_VAR   int    V03 tmp2         
               [000001] ---X--------              \--*  ARR_LENGTH int   
               [000000] ------------                 \--*  LCL_VAR   ref    V00 arg0         

LocalAddressVisitor visiting statement:
STMT00002 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000009] ------------              *  JTRUE     void  
               [000008] ------------              \--*  GE        int   
               [000006] ------------                 +--*  LCL_VAR   int    V03 tmp2         
               [000007] ------------                 \--*  CNS_INT   int    42

LocalAddressVisitor visiting statement:
STMT00004 ( INL01 @ 0x004[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000016] -A----------              *  ASG       int   
               [000015] D------N----              +--*  LCL_VAR   int    V02 tmp1         
               [000014] ------------              \--*  CNS_INT   int    42

LocalAddressVisitor visiting statement:
STMT00003 ( INL01 @ 0x006[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000012] -A----------              *  ASG       int   
               [000011] D------N----              +--*  LCL_VAR   int    V02 tmp1         
               [000010] ------------              \--*  LCL_VAR   int    V03 tmp2         

LocalAddressVisitor visiting statement:
STMT00001 ( 0x000[E-] ... ??? )
               [000005] --C---------              *  RETURN    int   
               [000017] ------------              \--*  LCL_VAR   int    V02 tmp1         


*************** Finishing PHASE Morph - Structs/AddrExp

*************** Starting PHASE Forward Substitution


===> BB01
    [000019]:  not asg (single-use lcl)


===> BB03


===> BB04


===> BB05

*************** Finishing PHASE Forward Substitution [no changes]

*************** Starting PHASE Morph - ByRefs

*************** In fgRetypeImplicitByRefArgs()

*************** Finishing PHASE Morph - ByRefs

*************** Starting PHASE Morph - Global

*************** In fgMorphBlocks()

Morphing BB01 of 'Test.Program:Main(System.String[]):int'

fgMorphTree BB01, STMT00005 (before)
               [000019] -A-X--------              *  ASG       int   
               [000018] D------N----              +--*  LCL_VAR   int    V03 tmp2         
               [000001] ---X--------              \--*  ARR_LENGTH int   
               [000000] ------------                 \--*  LCL_VAR   ref    V00 arg0         
Notify VM instruction set (SSE2) must be supported.
GenTreeNode creates assertion:
               [000001] ---X--------              *  ARR_LENGTH int   
In BB01 New Local Constant Assertion: V00 != null, index = #01
GenTreeNode creates assertion:
               [000019] -A-X--------              *  ASG       int   
In BB01 New Local Subrange Assertion: V03 in [0..2147483647], index = #02

fgMorphTree BB01, STMT00002 (before)
               [000009] ------------              *  JTRUE     void  
               [000008] ------------              \--*  GE        int   
               [000006] ------------                 +--*  LCL_VAR   int    V03 tmp2         
               [000007] ------------                 \--*  CNS_INT   int    42

Morphing BB03 of 'Test.Program:Main(System.String[]):int'

fgMorphTree BB03, STMT00004 (before)
               [000016] -A----------              *  ASG       int   
               [000015] D------N----              +--*  LCL_VAR   int    V02 tmp1         
               [000014] ------------              \--*  CNS_INT   int    42
GenTreeNode creates assertion:
               [000016] -A----------              *  ASG       int   
In BB03 New Local Constant Assertion: V02 == 42, index = #01

Morphing BB04 of 'Test.Program:Main(System.String[]):int'

fgMorphTree BB04, STMT00003 (before)
               [000012] -A----------              *  ASG       int   
               [000011] D------N----              +--*  LCL_VAR   int    V02 tmp1         
               [000010] ------------              \--*  LCL_VAR   int    V03 tmp2         
GenTreeNode creates assertion:
               [000012] -A----------              *  ASG       int   
In BB04 New Local Copy     Assertion: V02 == V03, index = #01

Morphing BB05 of 'Test.Program:Main(System.String[]):int'

fgMorphTree BB05, STMT00001 (before)
               [000005] --C---------              *  RETURN    int   
               [000017] ------------              \--*  LCL_VAR   int    V02 tmp1         

*************** In fgMarkDemotedImplicitByRefArgs()

*************** Finishing PHASE Morph - Global
Trees after Morph - Global

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB04 ( cond )                     i idxlen IBC 
BB03 [0002]  1       BB01                  0.37  37    [000..001)-> BB05 (always)                     i IBC 
BB04 [0003]  1       BB01                  0.63  63    [000..001)                                     i IBC 
BB05 [0004]  2       BB03,BB04             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) -> BB04 (cond), preds={} succs={BB03,BB04}

***** BB01
STMT00005 ( 0x000[E-] ... ??? )
               [000019] -A-X-+------              *  ASG       int   
               [000018] D----+-N----              +--*  LCL_VAR   int    V03 tmp2         
               [000001] ---X-+------              \--*  ARR_LENGTH int   
               [000000] -----+------                 \--*  LCL_VAR   ref    V00 arg0         

***** BB01
STMT00002 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000009] -----+------              *  JTRUE     void  
               [000008] J----+-N----              \--*  GE        int   
               [000006] -----+------                 +--*  LCL_VAR   int    V03 tmp2         
               [000007] -----+------                 \--*  CNS_INT   int    42

------------ BB03 [000..001) -> BB05 (always), preds={BB01} succs={BB05}

***** BB03
STMT00004 ( INL01 @ 0x004[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000016] -A---+------              *  ASG       int   
               [000015] D----+-N----              +--*  LCL_VAR   int    V02 tmp1         
               [000014] -----+------              \--*  CNS_INT   int    42

------------ BB04 [000..001), preds={BB01} succs={BB05}

***** BB04
STMT00003 ( INL01 @ 0x006[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000012] -A---+------              *  ASG       int   
               [000011] D----+-N----              +--*  LCL_VAR   int    V02 tmp1         
               [000010] -----+------              \--*  LCL_VAR   int    V03 tmp2         

------------ BB05 [???..???) (return), preds={BB03,BB04} succs={}

***** BB05
STMT00001 ( 0x000[E-] ... ??? )
               [000005] -----+------              *  RETURN    int   
               [000017] -----+------              \--*  LCL_VAR   int    V02 tmp1         

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE GS Cookie
No GS security needed

*************** Finishing PHASE GS Cookie

*************** Starting PHASE Compute edge weights (1, false)
*************** In fgComputeBlockAndEdgeWeights()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB04 ( cond )                     i idxlen IBC 
BB03 [0002]  1       BB01                  0.37  37    [000..001)-> BB05 (always)                     i IBC 
BB04 [0003]  1       BB01                  0.63  63    [000..001)                                     i IBC 
BB05 [0004]  2       BB03,BB04             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

 -- no profile data, so using default called count
 -- not optimizing or no profile data, so not computing edge weights

*************** Finishing PHASE Compute edge weights (1, false)

*************** Starting PHASE Create EH funclets
*************** In fgCreateFunclets()

After fgCreateFunclets()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB04 ( cond )                     i idxlen IBC 
BB03 [0002]  1       BB01                  0.37  37    [000..001)-> BB05 (always)                     i IBC 
BB04 [0003]  1       BB01                  0.63  63    [000..001)                                     i IBC 
BB05 [0004]  2       BB03,BB04             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
*************** In fgDebugCheckBBlist

*************** Finishing PHASE Create EH funclets

*************** Starting PHASE Invert loops

*************** Finishing PHASE Invert loops [no changes]

*************** Starting PHASE Optimize layout

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB04 ( cond )                     i idxlen IBC 
BB03 [0002]  1       BB01                  0.37  37    [000..001)-> BB05 (always)                     i IBC 
BB04 [0003]  1       BB01                  0.63  63    [000..001)                                     i IBC 
BB05 [0004]  2       BB03,BB04             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

Considering uncond to cond BB03 -> BB05
Considering uncond to cond BB04 -> BB05
*************** In fgDebugCheckBBlist

*************** In fgExpandRarelyRunBlocks()
*************** In fgReorderBlocks()

Initial BasicBlocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB04 ( cond )                     i idxlen IBC 
BB03 [0002]  1       BB01                  0.37  37    [000..001)-> BB05 (always)                     i IBC 
BB04 [0003]  1       BB01                  0.63  63    [000..001)                                     i IBC 
BB05 [0004]  2       BB03,BB04             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

Decided to relocate block(s) after block BB03 since they are uncommonly run block(s)
fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB03, jumpBlk=BB00, runRarely=false)
Could not relocate block BB04

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB04 ( cond )                     i idxlen IBC 
BB03 [0002]  1       BB01                  0.37  37    [000..001)-> BB05 (always)                     i IBC 
BB04 [0003]  1       BB01                  0.63  63    [000..001)                                     i IBC 
BB05 [0004]  2       BB03,BB04             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize layout
Trees after Optimize layout

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB04 ( cond )                     i idxlen IBC 
BB03 [0002]  1       BB01                  0.37  37    [000..001)-> BB05 (always)                     i IBC 
BB04 [0003]  1       BB01                  0.63  63    [000..001)                                     i IBC 
BB05 [0004]  2       BB03,BB04             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) -> BB04 (cond), preds={} succs={BB03,BB04}

***** BB01
STMT00005 ( 0x000[E-] ... ??? )
               [000019] -A-X-+------              *  ASG       int   
               [000018] D----+-N----              +--*  LCL_VAR   int    V03 tmp2         
               [000001] ---X-+------              \--*  ARR_LENGTH int   
               [000000] -----+------                 \--*  LCL_VAR   ref    V00 arg0         

***** BB01
STMT00002 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000009] -----+------              *  JTRUE     void  
               [000008] J----+-N----              \--*  GE        int   
               [000006] -----+------                 +--*  LCL_VAR   int    V03 tmp2         
               [000007] -----+------                 \--*  CNS_INT   int    42

------------ BB03 [000..001) -> BB05 (always), preds={BB01} succs={BB05}

***** BB03
STMT00004 ( INL01 @ 0x004[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000016] -A---+------              *  ASG       int   
               [000015] D----+-N----              +--*  LCL_VAR   int    V02 tmp1         
               [000014] -----+------              \--*  CNS_INT   int    42

------------ BB04 [000..001), preds={BB01} succs={BB05}

***** BB04
STMT00003 ( INL01 @ 0x006[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000012] -A---+------              *  ASG       int   
               [000011] D----+-N----              +--*  LCL_VAR   int    V02 tmp1         
               [000010] -----+------              \--*  LCL_VAR   int    V03 tmp2         

------------ BB05 [???..???) (return), preds={BB03,BB04} succs={}

***** BB05
STMT00001 ( 0x000[E-] ... ??? )
               [000005] -----+------              *  RETURN    int   
               [000017] -----+------              \--*  LCL_VAR   int    V02 tmp1         

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE Compute blocks reachability
*************** In fgComputeReachability
*************** In fgDebugCheckBBlist
Return blocks: BB05

Renumbering the basic blocks for fgComputeReachability pass #1

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB04 ( cond )                     i idxlen IBC 
BB03 [0002]  1       BB01                  0.37  37    [000..001)-> BB05 (always)                     i IBC 
BB04 [0003]  1       BB01                  0.63  63    [000..001)                                     i IBC 
BB05 [0004]  2       BB03,BB04             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
Renumber BB03 to BB02
Renumber BB04 to BB03
Renumber BB05 to BB04

*************** After renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC 
BB02 [0002]  1       BB01                  0.37  37    [000..001)-> BB04 (always)                     i IBC 
BB03 [0003]  1       BB01                  0.63  63    [000..001)                                     i IBC 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

New BlockSet epoch 4, # of blocks (including unused BB00): 5, bitset array size: 1 (short)
Enter blocks: BB01 

After computing reachability sets:
------------------------------------------------
BBnum  Reachable by 
------------------------------------------------
BB01 : BB01 
BB02 : BB01 BB02 
BB03 : BB01 BB03 
BB04 : BB01 BB02 BB03 BB04 

After computing reachability:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC 
BB02 [0002]  1       BB01                  0.37  37    [000..001)-> BB04 (always)                     i IBC 
BB03 [0003]  1       BB01                  0.63  63    [000..001)                                     i IBC 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist

Dominator computation start blocks (those blocks with no incoming edges):
BB01 
------------------------------------------------
BBnum  Dominated by
------------------------------------------------
BB01:  BB01 
BB02:  BB02 BB01 
BB03:  BB03 BB01 
BB04:  BB04 BB01 

Inside fgBuildDomTree

After computing the Dominance Tree:
BB01 : BB04 BB03 BB02 


After numbering the dominator tree:
BB01: pre=01, post=04
BB02: pre=04, post=03
BB03: pre=03, post=02
BB04: pre=02, post=01

*************** Finishing PHASE Compute blocks reachability

*************** Starting PHASE Set block weights

After optSetBlockWeights:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Set block weights

*************** Starting PHASE Find loops
*************** In optFindLoops()
*************** In optMarkLoopHeads()
0 loop heads marked
*************** In fgDebugCheckLoopTable

*************** Finishing PHASE Find loops
Trees after Find loops

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00005 ( 0x000[E-] ... ??? )
               [000019] -A-X-+------              *  ASG       int   
               [000018] D----+-N----              +--*  LCL_VAR   int    V03 tmp2         
               [000001] ---X-+------              \--*  ARR_LENGTH int   
               [000000] -----+------                 \--*  LCL_VAR   ref    V00 arg0         

***** BB01
STMT00002 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000009] -----+------              *  JTRUE     void  
               [000008] J----+-N----              \--*  GE        int   
               [000006] -----+------                 +--*  LCL_VAR   int    V03 tmp2         
               [000007] -----+------                 \--*  CNS_INT   int    42

------------ BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00004 ( INL01 @ 0x004[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000016] -A---+------              *  ASG       int   
               [000015] D----+-N----              +--*  LCL_VAR   int    V02 tmp1         
               [000014] -----+------              \--*  CNS_INT   int    42

------------ BB03 [000..001), preds={BB01} succs={BB04}

***** BB03
STMT00003 ( INL01 @ 0x006[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000012] -A---+------              *  ASG       int   
               [000011] D----+-N----              +--*  LCL_VAR   int    V02 tmp1         
               [000010] -----+------              \--*  LCL_VAR   int    V03 tmp2         

------------ BB04 [???..???) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00001 ( 0x000[E-] ... ??? )
               [000005] -----+------              *  RETURN    int   
               [000017] -----+------              \--*  LCL_VAR   int    V02 tmp1         

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE Clone loops

*************** In optCloneLoops()
  No loops to clone

*************** Finishing PHASE Clone loops [no changes]

*************** Starting PHASE Unroll loops

*************** Finishing PHASE Unroll loops [no changes]

*************** Starting PHASE Clear loop info

*************** Finishing PHASE Clear loop info

*************** Starting PHASE Mark local vars

*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***

*** marking local variables in block BB01 (weight=1   )
STMT00005 ( 0x000[E-] ... ??? )
               [000019] -A-X-+------              *  ASG       int   
               [000018] D----+-N----              +--*  LCL_VAR   int    V03 tmp2         
               [000001] ---X-+------              \--*  ARR_LENGTH int   
               [000000] -----+------                 \--*  LCL_VAR   ref    V00 arg0         
New refCnts for V03: refCnt =  1, refCntWtd = 2   
V03 needs explicit zero init. Disqualified as a single-def register candidate.
New refCnts for V00: refCnt =  1, refCntWtd = 1   
STMT00002 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000009] -----+------              *  JTRUE     void  
               [000008] J----+-N----              \--*  GE        int   
               [000006] -----+------                 +--*  LCL_VAR   int    V03 tmp2         
               [000007] -----+------                 \--*  CNS_INT   int    42
New refCnts for V03: refCnt =  2, refCntWtd = 4   

*** marking local variables in block BB02 (weight=0.18)
STMT00004 ( INL01 @ 0x004[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000016] -A---+------              *  ASG       int   
               [000015] D----+-N----              +--*  LCL_VAR   int    V02 tmp1         
               [000014] -----+------              \--*  CNS_INT   int    42
New refCnts for V02: refCnt =  1, refCntWtd = 0.18
V02 needs explicit zero init. Disqualified as a single-def register candidate.

*** marking local variables in block BB03 (weight=0.32)
STMT00003 ( INL01 @ 0x006[E-] ... ??? ) <- INLRT @ 0x000[E-]
               [000012] -A---+------              *  ASG       int   
               [000011] D----+-N----              +--*  LCL_VAR   int    V02 tmp1         
               [000010] -----+------              \--*  LCL_VAR   int    V03 tmp2         
New refCnts for V02: refCnt =  2, refCntWtd = 0.50
New refCnts for V03: refCnt =  3, refCntWtd = 4.63

*** marking local variables in block BB04 (weight=1   )
STMT00001 ( 0x000[E-] ... ??? )
               [000005] -----+------              *  RETURN    int   
               [000017] -----+------              \--*  LCL_VAR   int    V02 tmp1         
New refCnts for V02: refCnt =  3, refCntWtd = 1.50

*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt =  2, refCntWtd = 2   
New refCnts for V00: refCnt =  3, refCntWtd = 3   

*************** In optAddCopies()


*************** Finishing PHASE Mark local vars

*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()
*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize bools

*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()

*************** Finishing PHASE Find oper order

*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has    4 tree nodes

*************** Finishing PHASE Set block order
Trees before Build SSA representation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00005 ( 0x000[E-] ... ??? )
N004 (  3,  3) [000019] -A-X----R---              *  ASG       int   
N003 (  1,  1) [000018] D------N----              +--*  LCL_VAR   int    V03 tmp2         
N002 (  3,  3) [000001] ---X--------              \--*  ARR_LENGTH int   
N001 (  1,  1) [000000] ------------                 \--*  LCL_VAR   ref    V00 arg0         

***** BB01
STMT00002 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-]
N004 (  5,  5) [000009] ------------              *  JTRUE     void  
N003 (  3,  3) [000008] J------N----              \--*  GE        int   
N001 (  1,  1) [000006] ------------                 +--*  LCL_VAR   int    V03 tmp2         
N002 (  1,  1) [000007] ------------                 \--*  CNS_INT   int    42

------------ BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00004 ( INL01 @ 0x004[E-] ... ??? ) <- INLRT @ 0x000[E-]
N003 (  5,  4) [000016] -A------R---              *  ASG       int   
N002 (  3,  2) [000015] D------N----              +--*  LCL_VAR   int    V02 tmp1         
N001 (  1,  1) [000014] ------------              \--*  CNS_INT   int    42

------------ BB03 [000..001), preds={BB01} succs={BB04}

***** BB03
STMT00003 ( INL01 @ 0x006[E-] ... ??? ) <- INLRT @ 0x000[E-]
N003 (  5,  4) [000012] -A------R---              *  ASG       int   
N002 (  3,  2) [000011] D------N----              +--*  LCL_VAR   int    V02 tmp1         
N001 (  1,  1) [000010] ------------              \--*  LCL_VAR   int    V03 tmp2         

------------ BB04 [???..???) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00001 ( 0x000[E-] ... ??? )
N002 (  4,  3) [000005] ------------              *  RETURN    int   
N001 (  3,  2) [000017] ------------              \--*  LCL_VAR   int    V02 tmp1         

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 5.

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]

Inside fgBuildDomTree

After computing the Dominance Tree:
BB01 : BB04 BB03 BB02 

*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit
Tracked variable (3 out of 4) table:
V00 arg0          [   ref]: refCnt =    3, refCntWtd =   3   
V03 tmp2          [   int]: refCnt =    3, refCntWtd =   4.63
V02 tmp1          [   int]: refCnt =    3, refCntWtd =   1.50

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00    }
     DEF(1)={    V03}

BB02 USE(0)={   }
     DEF(1)={V02}

BB03 USE(1)={V03    }
     DEF(1)={    V02}

BB04 USE(1)={V02}
     DEF(0)={   }

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (1)={V00    }
     OUT(1)={    V03}

BB02 IN (0)={   }
     OUT(1)={V02}

BB03 IN (1)={V03    }
     OUT(1)={    V02}

BB04 IN (1)={V02}
     OUT(0)={   }

*************** In optRemoveRedundantZeroInits()
Marking L03 as having an explicit init
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
Added PHI definition for V02 at start of BB04.
*************** In SsaBuilder::RenameVariables()

After fgSsaBuild:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00005 ( 0x000[E-] ... ??? )
N004 (  3,  3) [000019] -A-X----R---              *  ASG       int   
N003 (  1,  1) [000018] D------N----              +--*  LCL_VAR   int    V03 tmp2         d:1
N002 (  3,  3) [000001] ---X--------              \--*  ARR_LENGTH int   
N001 (  1,  1) [000000] ------------                 \--*  LCL_VAR   ref    V00 arg0         u:1 (last use)

***** BB01
STMT00002 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-]
N004 (  5,  5) [000009] ------------              *  JTRUE     void  
N003 (  3,  3) [000008] J------N----              \--*  GE        int   
N001 (  1,  1) [000006] ------------                 +--*  LCL_VAR   int    V03 tmp2         u:1
N002 (  1,  1) [000007] ------------                 \--*  CNS_INT   int    42

------------ BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00004 ( INL01 @ 0x004[E-] ... ??? ) <- INLRT @ 0x000[E-]
N003 (  5,  4) [000016] -A------R---              *  ASG       int   
N002 (  3,  2) [000015] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:3
N001 (  1,  1) [000014] ------------              \--*  CNS_INT   int    42

------------ BB03 [000..001), preds={BB01} succs={BB04}

***** BB03
STMT00003 ( INL01 @ 0x006[E-] ... ??? ) <- INLRT @ 0x000[E-]
N003 (  5,  4) [000012] -A------R---              *  ASG       int   
N002 (  3,  2) [000011] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:2
N001 (  1,  1) [000010] ------------              \--*  LCL_VAR   int    V03 tmp2         u:1 (last use)

------------ BB04 [???..???) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00006 ( ??? ... ??? )
N005 (  0,  0) [000023] -A------R---              *  ASG       int   
N004 (  0,  0) [000021] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:1
N003 (  0,  0) [000022] ------------              \--*  PHI       int   
N001 (  0,  0) [000025] ------------ pred BB02       +--*  PHI_ARG   int    V02 tmp1         u:3
N002 (  0,  0) [000024] ------------ pred BB03       \--*  PHI_ARG   int    V02 tmp1         u:2

***** BB04
STMT00001 ( 0x000[E-] ... ??? )
N002 (  4,  3) [000005] ------------              *  RETURN    int   
N001 (  3,  2) [000017] ------------              \--*  LCL_VAR   int    V02 tmp1         u:1 (last use)

-------------------------------------------------------------------------------------------------------------------

*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00005 ( 0x000[E-] ... ??? )
N004 (  3,  3) [000019] -A-X----R---              *  ASG       int   
N003 (  1,  1) [000018] D------N----              +--*  LCL_VAR   int    V03 tmp2         d:1
N002 (  3,  3) [000001] ---X--------              \--*  ARR_LENGTH int   
N001 (  1,  1) [000000] ------------                 \--*  LCL_VAR   ref    V00 arg0         u:1 (last use)

***** BB01
STMT00002 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-]
N004 (  5,  5) [000009] ------------              *  JTRUE     void  
N003 (  3,  3) [000008] J------N----              \--*  GE        int   
N001 (  1,  1) [000006] ------------                 +--*  LCL_VAR   int    V03 tmp2         u:1
N002 (  1,  1) [000007] ------------                 \--*  CNS_INT   int    42

------------ BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00004 ( INL01 @ 0x004[E-] ... ??? ) <- INLRT @ 0x000[E-]
N003 (  5,  4) [000016] -A------R---              *  ASG       int   
N002 (  3,  2) [000015] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:3
N001 (  1,  1) [000014] ------------              \--*  CNS_INT   int    42

------------ BB03 [000..001), preds={BB01} succs={BB04}

***** BB03
STMT00003 ( INL01 @ 0x006[E-] ... ??? ) <- INLRT @ 0x000[E-]
N003 (  5,  4) [000012] -A------R---              *  ASG       int   
N002 (  3,  2) [000011] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:2
N001 (  1,  1) [000010] ------------              \--*  LCL_VAR   int    V03 tmp2         u:1 (last use)

------------ BB04 [???..???) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00006 ( ??? ... ??? )
N005 (  0,  0) [000023] -A------R---              *  ASG       int   
N004 (  0,  0) [000021] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:1
N003 (  0,  0) [000022] ------------              \--*  PHI       int   
N001 (  0,  0) [000025] ------------ pred BB02       +--*  PHI_ARG   int    V02 tmp1         u:3
N002 (  0,  0) [000024] ------------ pred BB03       \--*  PHI_ARG   int    V02 tmp1         u:2

***** BB04
STMT00001 ( 0x000[E-] ... ??? )
N002 (  4,  3) [000005] ------------              *  RETURN    int   
N001 (  3,  2) [000017] ------------              \--*  LCL_VAR   int    V02 tmp1         u:1 (last use)

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE Early Value Propagation
*************** In optEarlyProp()

After optEarlyProp:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00005 ( 0x000[E-] ... ??? )
N004 (  3,  3) [000019] -A-X----R---              *  ASG       int   
N003 (  1,  1) [000018] D------N----              +--*  LCL_VAR   int    V03 tmp2         d:1
N002 (  3,  3) [000001] ---X--------              \--*  ARR_LENGTH int   
N001 (  1,  1) [000000] ------------                 \--*  LCL_VAR   ref    V00 arg0         u:1 (last use)

***** BB01
STMT00002 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-]
N004 (  5,  5) [000009] ------------              *  JTRUE     void  
N003 (  3,  3) [000008] J------N----              \--*  GE        int   
N001 (  1,  1) [000006] ------------                 +--*  LCL_VAR   int    V03 tmp2         u:1
N002 (  1,  1) [000007] ------------                 \--*  CNS_INT   int    42

------------ BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00004 ( INL01 @ 0x004[E-] ... ??? ) <- INLRT @ 0x000[E-]
N003 (  5,  4) [000016] -A------R---              *  ASG       int   
N002 (  3,  2) [000015] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:3
N001 (  1,  1) [000014] ------------              \--*  CNS_INT   int    42

------------ BB03 [000..001), preds={BB01} succs={BB04}

***** BB03
STMT00003 ( INL01 @ 0x006[E-] ... ??? ) <- INLRT @ 0x000[E-]
N003 (  5,  4) [000012] -A------R---              *  ASG       int   
N002 (  3,  2) [000011] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:2
N001 (  1,  1) [000010] ------------              \--*  LCL_VAR   int    V03 tmp2         u:1 (last use)

------------ BB04 [???..???) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00006 ( ??? ... ??? )
N005 (  0,  0) [000023] -A------R---              *  ASG       int   
N004 (  0,  0) [000021] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:1
N003 (  0,  0) [000022] ------------              \--*  PHI       int   
N001 (  0,  0) [000025] ------------ pred BB02       +--*  PHI_ARG   int    V02 tmp1         u:3
N002 (  0,  0) [000024] ------------ pred BB03       \--*  PHI_ARG   int    V02 tmp1         u:2

***** BB04
STMT00001 ( 0x000[E-] ... ??? )
N002 (  4,  3) [000005] ------------              *  RETURN    int   
N001 (  3,  2) [000017] ------------              \--*  LCL_VAR   int    V02 tmp1         u:1 (last use)

-------------------------------------------------------------------------------------------------------------------

*************** Finishing PHASE Early Value Propagation

*************** Starting PHASE Do value numbering

*************** In fgValueNumber()
Memory Initial Value in BB01 is: $c0
The SSA definition for ByrefExposed (#1) at start of BB01 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB01 is $c0 {InitVal($41)}

***** BB01, STMT00005(before)
N004 (  3,  3) [000019] -A-X----R---              *  ASG       int   
N003 (  1,  1) [000018] D------N----              +--*  LCL_VAR   int    V03 tmp2         d:1
N002 (  3,  3) [000001] ---X--------              \--*  ARR_LENGTH int   
N001 (  1,  1) [000000] ------------                 \--*  LCL_VAR   ref    V00 arg0         u:1 (last use)

N001 [000000]   LCL_VAR   V00 arg0         u:1 (last use) => $80 {InitVal($40)}
N002 [000001]   ARR_LENGTH => $180 {norm=$100 {ARR_LENGTH($80)}, exc=$140 {NullPtrExc($80)}}
N003 [000018]   LCL_VAR   V03 tmp2         d:1 => $VN.Void
Tree [000019] assigned VN to local var V03/1: $100 {ARR_LENGTH($80)}
N004 [000019]   ASG       => $141 {norm=$VN.Void, exc=$140 {NullPtrExc($80)}}

***** BB01, STMT00005(after)
N004 (  3,  3) [000019] -A-X----R---              *  ASG       int    $141
N003 (  1,  1) [000018] D------N----              +--*  LCL_VAR   int    V03 tmp2         d:1 $VN.Void
N002 (  3,  3) [000001] ---X--------              \--*  ARR_LENGTH int    $180
N001 (  1,  1) [000000] ------------                 \--*  LCL_VAR   ref    V00 arg0         u:1 (last use) $80

---------

***** BB01, STMT00002(before)
N004 (  5,  5) [000009] ------------              *  JTRUE     void  
N003 (  3,  3) [000008] J------N----              \--*  GE        int   
N001 (  1,  1) [000006] ------------                 +--*  LCL_VAR   int    V03 tmp2         u:1
N002 (  1,  1) [000007] ------------                 \--*  CNS_INT   int    42

N001 [000006]   LCL_VAR   V03 tmp2         u:1 => $100 {ARR_LENGTH($80)}
N002 [000007]   CNS_INT   42 => $42 {IntCns 42}
N003 [000008]   GE        => $181 { {IntCns 42} LE  {ARR_LENGTH($80)}}
N004 [000009]   JTRUE     => $VN.Void

***** BB01, STMT00002(after)
N004 (  5,  5) [000009] ------------              *  JTRUE     void   $VN.Void
N003 (  3,  3) [000008] J------N----              \--*  GE        int    $181
N001 (  1,  1) [000006] ------------                 +--*  LCL_VAR   int    V03 tmp2         u:1 $100
N002 (  1,  1) [000007] ------------                 \--*  CNS_INT   int    42 $42

finish(BB01).
   Succ(BB02).
     Not yet completed.
     All preds complete, adding to allDone.
   Succ(BB03).
     Not yet completed.
     All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#1) at start of BB03 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB03 is $c0 {InitVal($41)}

***** BB03, STMT00003(before)
N003 (  5,  4) [000012] -A------R---              *  ASG       int   
N002 (  3,  2) [000011] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:2
N001 (  1,  1) [000010] ------------              \--*  LCL_VAR   int    V03 tmp2         u:1 (last use)

N001 [000010]   LCL_VAR   V03 tmp2         u:1 (last use) => $100 {ARR_LENGTH($80)}
N002 [000011]   LCL_VAR   V02 tmp1         d:2 => $VN.Void
Tree [000012] assigned VN to local var V02/2: $100 {ARR_LENGTH($80)}
N003 [000012]   ASG       => $VN.Void

***** BB03, STMT00003(after)
N003 (  5,  4) [000012] -A------R---              *  ASG       int    $VN.Void
N002 (  3,  2) [000011] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:2 $VN.Void
N001 (  1,  1) [000010] ------------              \--*  LCL_VAR   int    V03 tmp2         u:1 (last use) $100

finish(BB03).
   Succ(BB04).
     Not yet completed.
     Not all preds complete  Adding to notallDone, if necessary...
       Was necessary.
The SSA definition for ByrefExposed (#1) at start of BB02 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB02 is $c0 {InitVal($41)}

***** BB02, STMT00004(before)
N003 (  5,  4) [000016] -A------R---              *  ASG       int   
N002 (  3,  2) [000015] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:3
N001 (  1,  1) [000014] ------------              \--*  CNS_INT   int    42

N001 [000014]   CNS_INT   42 => $42 {IntCns 42}
N002 [000015]   LCL_VAR   V02 tmp1         d:3 => $VN.Void
Tree [000016] assigned VN to local var V02/3: $42 {IntCns 42}
N003 [000016]   ASG       => $VN.Void

***** BB02, STMT00004(after)
N003 (  5,  4) [000016] -A------R---              *  ASG       int    $VN.Void
N002 (  3,  2) [000015] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:3 $VN.Void
N001 (  1,  1) [000014] ------------              \--*  CNS_INT   int    42 $42

finish(BB02).
   Succ(BB04).
     Not yet completed.
     All preds complete, adding to allDone.
SSA PHI definition: set VN of local 2/1 to $1c0 {PhiDef($2, $1, $182)} .
The SSA definition for ByrefExposed (#1) at start of BB04 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB04 is $c0 {InitVal($41)}

***** BB04, STMT00001(before)
N002 (  4,  3) [000005] ------------              *  RETURN    int   
N001 (  3,  2) [000017] ------------              \--*  LCL_VAR   int    V02 tmp1         u:1 (last use)

N001 [000017]   LCL_VAR   V02 tmp1         u:1 (last use) => $1c0 {PhiDef($2, $1, $182)}
N002 [000005]   RETURN    => $VN.Void

***** BB04, STMT00001(after)
N002 (  4,  3) [000005] ------------              *  RETURN    int    $VN.Void
N001 (  3,  2) [000017] ------------              \--*  LCL_VAR   int    V02 tmp1         u:1 (last use) $1c0

finish(BB04).

*************** Finishing PHASE Do value numbering

*************** Starting PHASE Hoist loop code

No loops; no hoisting

*************** Finishing PHASE Hoist loop code

*************** Starting PHASE VN based copy prop
*************** In optVnCopyProp()
Copy Assertion for BB01
  curSsaName stack: { }

							Live vars: {V00} => {}
							Live vars: {} => {V03}
Copy Assertion for BB04
  curSsaName stack: { 0-[000000]:V00 3-[000018]:V03 }

							Live vars: {V02} => {}
Copy Assertion for BB03
  curSsaName stack: { 0-[000000]:V00 3-[000018]:V03 }

							Live vars: {V03} => {}
							Live vars: {} => {V02}
Copy Assertion for BB02
  curSsaName stack: { 0-[000000]:V00 3-[000018]:V03 }

							Live vars: {} => {V02}

*************** Finishing PHASE VN based copy prop

*************** Starting PHASE Redundant branch opts

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

optRedundantRelop in BB01; jump tree is
N004 (  5,  5) [000009] ------------              *  JTRUE     void   $VN.Void
N003 (  3,  3) [000008] J------N----              \--*  GE        int    $181
N001 (  1,  1) [000006] ------------                 +--*  LCL_VAR   int    V03 tmp2         u:1 $100
N002 (  1,  1) [000007] ------------                 \--*  CNS_INT   int    42 $42
 ... checking previous tree
N004 (  3,  3) [000019] -A-X----R---              *  ASG       int    $141
N003 (  1,  1) [000018] D------N----              +--*  LCL_VAR   int    V03 tmp2         d:1 $VN.Void
N002 (  3,  3) [000001] ---X--------              \--*  ARR_LENGTH int    $180
N001 (  1,  1) [000000] ------------                 \--*  LCL_VAR   ref    V00 arg0         u:1 (last use) $80
 -- prev tree VN is not related

*************** Finishing PHASE Redundant branch opts [no changes]
Trees before Optimize Valnum CSEs

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00005 ( 0x000[E-] ... ??? )
N004 (  3,  3) [000019] -A-X----R---              *  ASG       int    $141
N003 (  1,  1) [000018] D------N----              +--*  LCL_VAR   int    V03 tmp2         d:1 $VN.Void
N002 (  3,  3) [000001] ---X--------              \--*  ARR_LENGTH int    $180
N001 (  1,  1) [000000] ------------                 \--*  LCL_VAR   ref    V00 arg0         u:1 (last use) $80

***** BB01
STMT00002 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-]
N004 (  5,  5) [000009] ------------              *  JTRUE     void   $VN.Void
N003 (  3,  3) [000008] J------N----              \--*  GE        int    $181
N001 (  1,  1) [000006] ------------                 +--*  LCL_VAR   int    V03 tmp2         u:1 $100
N002 (  1,  1) [000007] ------------                 \--*  CNS_INT   int    42 $42

------------ BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00004 ( INL01 @ 0x004[E-] ... ??? ) <- INLRT @ 0x000[E-]
N003 (  5,  4) [000016] -A------R---              *  ASG       int    $VN.Void
N002 (  3,  2) [000015] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:3 $VN.Void
N001 (  1,  1) [000014] ------------              \--*  CNS_INT   int    42 $42

------------ BB03 [000..001), preds={BB01} succs={BB04}

***** BB03
STMT00003 ( INL01 @ 0x006[E-] ... ??? ) <- INLRT @ 0x000[E-]
N003 (  5,  4) [000012] -A------R---              *  ASG       int    $VN.Void
N002 (  3,  2) [000011] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:2 $VN.Void
N001 (  1,  1) [000010] ------------              \--*  LCL_VAR   int    V03 tmp2         u:1 (last use) $100

------------ BB04 [???..???) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00006 ( ??? ... ??? )
N005 (  0,  0) [000023] -A------R---              *  ASG       int    $VN.Void
N004 (  0,  0) [000021] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:1 $VN.Void
N003 (  0,  0) [000022] ------------              \--*  PHI       int    $1c0
N001 (  0,  0) [000025] ------------ pred BB02       +--*  PHI_ARG   int    V02 tmp1         u:3 $42
N002 (  0,  0) [000024] ------------ pred BB03       \--*  PHI_ARG   int    V02 tmp1         u:2 $100

***** BB04
STMT00001 ( 0x000[E-] ... ??? )
N002 (  4,  3) [000005] ------------              *  RETURN    int    $VN.Void
N001 (  3,  2) [000017] ------------              \--*  LCL_VAR   int    V02 tmp1         u:1 (last use) $1c0

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Optimize Valnum CSEs

*************** Finishing PHASE Optimize Valnum CSEs

*************** Starting PHASE Assertion prop
*************** In optAssertionPropMain()
Blocks/Trees at start of phase

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00005 ( 0x000[E-] ... ??? )
N004 (  3,  3) [000019] -A-X----R---              *  ASG       int    $141
N003 (  1,  1) [000018] D------N----              +--*  LCL_VAR   int    V03 tmp2         d:1 $VN.Void
N002 (  3,  3) [000001] ---X--------              \--*  ARR_LENGTH int    $180
N001 (  1,  1) [000000] ------------                 \--*  LCL_VAR   ref    V00 arg0         u:1 (last use) $80

***** BB01
STMT00002 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-]
N004 (  5,  5) [000009] ------------              *  JTRUE     void   $VN.Void
N003 (  3,  3) [000008] J------N----              \--*  GE        int    $181
N001 (  1,  1) [000006] ------------                 +--*  LCL_VAR   int    V03 tmp2         u:1 $100
N002 (  1,  1) [000007] ------------                 \--*  CNS_INT   int    42 $42

------------ BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00004 ( INL01 @ 0x004[E-] ... ??? ) <- INLRT @ 0x000[E-]
N003 (  5,  4) [000016] -A------R---              *  ASG       int    $VN.Void
N002 (  3,  2) [000015] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:3 $VN.Void
N001 (  1,  1) [000014] ------------              \--*  CNS_INT   int    42 $42

------------ BB03 [000..001), preds={BB01} succs={BB04}

***** BB03
STMT00003 ( INL01 @ 0x006[E-] ... ??? ) <- INLRT @ 0x000[E-]
N003 (  5,  4) [000012] -A------R---              *  ASG       int    $VN.Void
N002 (  3,  2) [000011] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:2 $VN.Void
N001 (  1,  1) [000010] ------------              \--*  LCL_VAR   int    V03 tmp2         u:1 (last use) $100

------------ BB04 [???..???) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00006 ( ??? ... ??? )
N005 (  0,  0) [000023] -A------R---              *  ASG       int    $VN.Void
N004 (  0,  0) [000021] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:1 $VN.Void
N003 (  0,  0) [000022] ------------              \--*  PHI       int    $1c0
N001 (  0,  0) [000025] ------------ pred BB02       +--*  PHI_ARG   int    V02 tmp1         u:3 $42
N002 (  0,  0) [000024] ------------ pred BB03       \--*  PHI_ARG   int    V02 tmp1         u:2 $100

***** BB04
STMT00001 ( 0x000[E-] ... ??? )
N002 (  4,  3) [000005] ------------              *  RETURN    int    $VN.Void
N001 (  3,  2) [000017] ------------              \--*  LCL_VAR   int    V02 tmp1         u:1 (last use) $1c0

-------------------------------------------------------------------------------------------------------------------
GenTreeNode creates assertion:
N002 (  3,  3) [000001] ---X--------              *  ARR_LENGTH int    $180
In BB01 New Global Constant Assertion: ($80,$0) V00.01 != null, index = #01
GenTreeNode creates assertion:
N004 (  5,  5) [000009] ------------              *  JTRUE     void   $VN.Void
In BB01 New Global Constant Assertion: ($181,$40) Loop_Bnd { {IntCns 42} LE  {ARR_LENGTH($80)}} is not  {IntCns 0}, index = #02
GenTreeNode creates assertion:
N004 (  5,  5) [000009] ------------              *  JTRUE     void   $VN.Void
In BB01 New Global Constant Assertion: ($181,$40) Loop_Bnd { {IntCns 42} LE  {ARR_LENGTH($80)}} is  {IntCns 0}, index = #03

BB01 valueGen = #01 #03 => BB03 valueGen = #01 #02
BB02 valueGen = #NA
BB03 valueGen = #NA
BB04 valueGen = #NA

BB01:
 in   = #NA
 out  = #01 #03
 BB03 = #01 #02
BB02:
 in   = #01 #03
 out  = #01 #03
BB03:
 in   = #01 #02
 out  = #01 #02
BB04:
 in   = #01
 out  = #01

Propagating #NA for BB01, stmt STMT00005, tree [000000], tree -> #NA
Propagating #NA for BB01, stmt STMT00005, tree [000001], tree -> #01
Propagating #01 for BB01, stmt STMT00005, tree [000018], tree -> #NA
Propagating #01 for BB01, stmt STMT00005, tree [000019], tree -> #NA
Propagating #01 for BB01, stmt STMT00002, tree [000006], tree -> #NA
Propagating #01 for BB01, stmt STMT00002, tree [000007], tree -> #NA
Propagating #01 for BB01, stmt STMT00002, tree [000008], tree -> #NA
Propagating #01 for BB01, stmt STMT00002, tree [000009], tree -> #02
Propagating #01 #03 for BB02, stmt STMT00004, tree [000014], tree -> #NA
Propagating #01 #03 for BB02, stmt STMT00004, tree [000015], tree -> #NA
Propagating #01 #03 for BB02, stmt STMT00004, tree [000016], tree -> #NA
Propagating #01 #02 for BB03, stmt STMT00003, tree [000010], tree -> #NA
Propagating #01 #02 for BB03, stmt STMT00003, tree [000011], tree -> #NA
Propagating #01 #02 for BB03, stmt STMT00003, tree [000012], tree -> #NA
Propagating #01 for BB04, stmt STMT00001, tree [000017], tree -> #NA
Propagating #01 for BB04, stmt STMT00001, tree [000005], tree -> #NA
*************** In fgDebugCheckBBlist

*************** Finishing PHASE Assertion prop

*************** Starting PHASE Optimize index checks
*************** In OptimizeRangeChecks()
Blocks/trees before phase

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00005 ( 0x000[E-] ... ??? )
N004 (  3,  3) [000019] -A-X----R---              *  ASG       int    $141
N003 (  1,  1) [000018] D------N----              +--*  LCL_VAR   int    V03 tmp2         d:1 $VN.Void
N002 (  3,  3) [000001] ---X--------              \--*  ARR_LENGTH int    $180
N001 (  1,  1) [000000] ------------                 \--*  LCL_VAR   ref    V00 arg0         u:1 (last use) $80

***** BB01
STMT00002 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-]
N004 (  5,  5) [000009] ------------              *  JTRUE     void   $VN.Void
N003 (  3,  3) [000008] J------N----              \--*  GE        int    $181
N001 (  1,  1) [000006] ------------                 +--*  LCL_VAR   int    V03 tmp2         u:1 $100
N002 (  1,  1) [000007] ------------                 \--*  CNS_INT   int    42 $42

------------ BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00004 ( INL01 @ 0x004[E-] ... ??? ) <- INLRT @ 0x000[E-]
N003 (  5,  4) [000016] -A------R---              *  ASG       int    $VN.Void
N002 (  3,  2) [000015] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:3 $VN.Void
N001 (  1,  1) [000014] ------------              \--*  CNS_INT   int    42 $42

------------ BB03 [000..001), preds={BB01} succs={BB04}

***** BB03
STMT00003 ( INL01 @ 0x006[E-] ... ??? ) <- INLRT @ 0x000[E-]
N003 (  5,  4) [000012] -A------R---              *  ASG       int    $VN.Void
N002 (  3,  2) [000011] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:2 $VN.Void
N001 (  1,  1) [000010] ------------              \--*  LCL_VAR   int    V03 tmp2         u:1 (last use) $100

------------ BB04 [???..???) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00006 ( ??? ... ??? )
N005 (  0,  0) [000023] -A------R---              *  ASG       int    $VN.Void
N004 (  0,  0) [000021] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:1 $VN.Void
N003 (  0,  0) [000022] ------------              \--*  PHI       int    $1c0
N001 (  0,  0) [000025] ------------ pred BB02       +--*  PHI_ARG   int    V02 tmp1         u:3 $42
N002 (  0,  0) [000024] ------------ pred BB03       \--*  PHI_ARG   int    V02 tmp1         u:2 $100

***** BB04
STMT00001 ( 0x000[E-] ... ??? )
N002 (  4,  3) [000005] ------------              *  RETURN    int    $VN.Void
N001 (  3,  2) [000017] ------------              \--*  LCL_VAR   int    V02 tmp1         u:1 (last use) $1c0

-------------------------------------------------------------------------------------------------------------------

*************** Finishing PHASE Optimize index checks

*************** Starting PHASE Remove dead blocks
*************** In fgDebugCheckBBlist

*************** Finishing PHASE Remove dead blocks

*************** Starting PHASE Insert GC Polls

*************** Finishing PHASE Insert GC Polls [no changes]

*************** Starting PHASE Determine first cold block

*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method

*************** Finishing PHASE Determine first cold block [no changes]
Trees before Rationalize IR

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00005 ( 0x000[E-] ... ??? )
N004 (  3,  3) [000019] -A-X----R---              *  ASG       int    $141
N003 (  1,  1) [000018] D------N----              +--*  LCL_VAR   int    V03 tmp2         d:1 $VN.Void
N002 (  3,  3) [000001] ---X--------              \--*  ARR_LENGTH int    $180
N001 (  1,  1) [000000] ------------                 \--*  LCL_VAR   ref    V00 arg0         u:1 (last use) $80

***** BB01
STMT00002 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-]
N004 (  5,  5) [000009] ------------              *  JTRUE     void   $VN.Void
N003 (  3,  3) [000008] J------N----              \--*  GE        int    $181
N001 (  1,  1) [000006] ------------                 +--*  LCL_VAR   int    V03 tmp2         u:1 $100
N002 (  1,  1) [000007] ------------                 \--*  CNS_INT   int    42 $42

------------ BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00004 ( INL01 @ 0x004[E-] ... ??? ) <- INLRT @ 0x000[E-]
N003 (  5,  4) [000016] -A------R---              *  ASG       int    $VN.Void
N002 (  3,  2) [000015] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:3 $VN.Void
N001 (  1,  1) [000014] ------------              \--*  CNS_INT   int    42 $42

------------ BB03 [000..001), preds={BB01} succs={BB04}

***** BB03
STMT00003 ( INL01 @ 0x006[E-] ... ??? ) <- INLRT @ 0x000[E-]
N003 (  5,  4) [000012] -A------R---              *  ASG       int    $VN.Void
N002 (  3,  2) [000011] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:2 $VN.Void
N001 (  1,  1) [000010] ------------              \--*  LCL_VAR   int    V03 tmp2         u:1 (last use) $100

------------ BB04 [???..???) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00006 ( ??? ... ??? )
N005 (  0,  0) [000023] -A------R---              *  ASG       int    $VN.Void
N004 (  0,  0) [000021] D------N----              +--*  LCL_VAR   int    V02 tmp1         d:1 $VN.Void
N003 (  0,  0) [000022] ------------              \--*  PHI       int    $1c0
N001 (  0,  0) [000025] ------------ pred BB02       +--*  PHI_ARG   int    V02 tmp1         u:3 $42
N002 (  0,  0) [000024] ------------ pred BB03       \--*  PHI_ARG   int    V02 tmp1         u:2 $100

***** BB04
STMT00001 ( 0x000[E-] ... ??? )
N002 (  4,  3) [000005] ------------              *  RETURN    int    $VN.Void
N001 (  3,  2) [000017] ------------              \--*  LCL_VAR   int    V02 tmp1         u:1 (last use) $1c0

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Rationalize IR
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 (  3,  3) [000019] DA-X--------              *  STORE_LCL_VAR int    V03 tmp2         d:1

rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 (  5,  4) [000016] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:3

rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 (  5,  4) [000012] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:2


*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC LIR 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC LIR 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC LIR 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}
               [000026] ------------                 IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  1,  1) [000000] ------------         t0 =    LCL_VAR   ref    V00 arg0         u:1 (last use) $80
                                                  /--*  t0     ref    
N002 (  3,  3) [000001] ---X--------         t1 = *  ARR_LENGTH int    $180
                                                  /--*  t1     int    
N004 (  3,  3) [000019] DA-X--------              *  STORE_LCL_VAR int    V03 tmp2         d:1
               [000027] ------------                 IL_OFFSET void   INL01 @ 0x000[E-] <- INLRT @ 0x000[E-]
N001 (  1,  1) [000006] ------------         t6 =    LCL_VAR   int    V03 tmp2         u:1 $100
N002 (  1,  1) [000007] ------------         t7 =    CNS_INT   int    42 $42
                                                  /--*  t6     int    
                                                  +--*  t7     int    
N003 (  3,  3) [000008] J------N----         t8 = *  GE        int    $181
                                                  /--*  t8     int    
N004 (  5,  5) [000009] ------------              *  JTRUE     void   $VN.Void

------------ BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}
               [000028] ------------                 IL_OFFSET void   INL01 @ 0x004[E-] <- INLRT @ 0x000[E-]
N001 (  1,  1) [000014] ------------        t14 =    CNS_INT   int    42 $42
                                                  /--*  t14    int    
N003 (  5,  4) [000016] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:3

------------ BB03 [000..001), preds={BB01} succs={BB04}
               [000029] ------------                 IL_OFFSET void   INL01 @ 0x006[E-] <- INLRT @ 0x000[E-]
N001 (  1,  1) [000010] ------------        t10 =    LCL_VAR   int    V03 tmp2         u:1 (last use) $100
                                                  /--*  t10    int    
N003 (  5,  4) [000012] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:2

------------ BB04 [???..???) (return), preds={BB02,BB03} succs={}
               [000030] ------------                 IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  3,  2) [000017] ------------        t17 =    LCL_VAR   int    V02 tmp1         u:1 (last use) $1c0
                                                  /--*  t17    int    
N002 (  4,  3) [000005] ------------              *  RETURN    int    $VN.Void

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE Do 'simple' lowering
*************** In fgDebugCheckBBlist

*************** Finishing PHASE Do 'simple' lowering
Trees before Lowering nodeinfo

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC LIR 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC LIR 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC LIR 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}
               [000026] ------------                 IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  1,  1) [000000] ------------         t0 =    LCL_VAR   ref    V00 arg0         u:1 (last use) $80
               [000031] ------------        t31 =    CNS_INT   long   8
                                                  /--*  t0     ref    
                                                  +--*  t31    long   
               [000032] ------------        t32 = *  ADD       ref   
                                                  /--*  t32    ref    
N002 (  3,  3) [000001] ---X--------         t1 = *  IND       int    $180
                                                  /--*  t1     int    
N004 (  3,  3) [000019] DA-X--------              *  STORE_LCL_VAR int    V03 tmp2         d:1
               [000027] ------------                 IL_OFFSET void   INL01 @ 0x000[E-] <- INLRT @ 0x000[E-]
N001 (  1,  1) [000006] ------------         t6 =    LCL_VAR   int    V03 tmp2         u:1 $100
N002 (  1,  1) [000007] ------------         t7 =    CNS_INT   int    42 $42
                                                  /--*  t6     int    
                                                  +--*  t7     int    
N003 (  3,  3) [000008] J------N----         t8 = *  GE        int    $181
                                                  /--*  t8     int    
N004 (  5,  5) [000009] ------------              *  JTRUE     void   $VN.Void

------------ BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}
               [000028] ------------                 IL_OFFSET void   INL01 @ 0x004[E-] <- INLRT @ 0x000[E-]
N001 (  1,  1) [000014] ------------        t14 =    CNS_INT   int    42 $42
                                                  /--*  t14    int    
N003 (  5,  4) [000016] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:3

------------ BB03 [000..001), preds={BB01} succs={BB04}
               [000029] ------------                 IL_OFFSET void   INL01 @ 0x006[E-] <- INLRT @ 0x000[E-]
N001 (  1,  1) [000010] ------------        t10 =    LCL_VAR   int    V03 tmp2         u:1 (last use) $100
                                                  /--*  t10    int    
N003 (  5,  4) [000012] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:2

------------ BB04 [???..???) (return), preds={BB02,BB03} succs={}
               [000030] ------------                 IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  3,  2) [000017] ------------        t17 =    LCL_VAR   int    V02 tmp1         u:1 (last use) $1c0
                                                  /--*  t17    int    
N002 (  4,  3) [000005] ------------              *  RETURN    int    $VN.Void

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Lowering nodeinfo
Addressing mode:
  Base
    N001 (  1,  1) [000000] ------------              *  LCL_VAR   ref    V00 arg0         u:1 (last use) $80
  + 8
Removing unused node:
                 [000031] -c----------              *  CNS_INT   long   8
New addressing mode node:
                 [000032] ------------              *  LEA(b+8)  ref   

lowering store lcl var/field (before):
N001 (  1,  1) [000000] ------------         t0 =    LCL_VAR   ref    V00 arg0         u:1 (last use) $80
                                                  /--*  t0     ref    
               [000032] -c----------        t32 = *  LEA(b+8)  ref   
                                                  /--*  t32    ref    
N002 (  3,  3) [000001] ---X--------         t1 = *  IND       int    $180
                                                  /--*  t1     int    
N004 (  3,  3) [000019] DA-X--------              *  STORE_LCL_VAR int    V03 tmp2         d:1

lowering store lcl var/field (after):
N001 (  1,  1) [000000] ------------         t0 =    LCL_VAR   ref    V00 arg0         u:1 (last use) $80
                                                  /--*  t0     ref    
               [000032] -c----------        t32 = *  LEA(b+8)  ref   
                                                  /--*  t32    ref    
N002 (  3,  3) [000001] ---X--------         t1 = *  IND       int    $180
                                                  /--*  t1     int    
N004 (  3,  3) [000019] DA-X--------              *  STORE_LCL_VAR int    V03 tmp2         d:1

lowering store lcl var/field (before):
N001 (  1,  1) [000014] ------------        t14 =    CNS_INT   int    42 $42
                                                  /--*  t14    int    
N003 (  5,  4) [000016] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:3

lowering store lcl var/field (after):
N001 (  1,  1) [000014] -c----------        t14 =    CNS_INT   int    42 $42
                                                  /--*  t14    int    
N003 (  5,  4) [000016] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:3

lowering store lcl var/field (before):
N001 (  1,  1) [000010] ------------        t10 =    LCL_VAR   int    V03 tmp2         u:1 (last use) $100
                                                  /--*  t10    int    
N003 (  5,  4) [000012] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:2

lowering store lcl var/field (after):
N001 (  1,  1) [000010] ------------        t10 =    LCL_VAR   int    V03 tmp2         u:1 (last use) $100
                                                  /--*  t10    int    
N003 (  5,  4) [000012] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:2

lowering GT_RETURN
N002 (  4,  3) [000005] ------------              *  RETURN    int    $VN.Void
============Lower has completed modifying nodes.

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC LIR 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC LIR 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC LIR 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}
               [000026] ------------                 IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  1,  1) [000000] ------------         t0 =    LCL_VAR   ref    V00 arg0         u:1 (last use) $80
                                                  /--*  t0     ref    
               [000032] -c----------        t32 = *  LEA(b+8)  ref   
                                                  /--*  t32    ref    
N002 (  3,  3) [000001] ---X--------         t1 = *  IND       int    $180
                                                  /--*  t1     int    
N004 (  3,  3) [000019] DA-X--------              *  STORE_LCL_VAR int    V03 tmp2         d:1
               [000027] ------------                 IL_OFFSET void   INL01 @ 0x000[E-] <- INLRT @ 0x000[E-]
N001 (  1,  1) [000006] ------------         t6 =    LCL_VAR   int    V03 tmp2         u:1 $100
N002 (  1,  1) [000007] -c----------         t7 =    CNS_INT   int    42 $42
                                                  /--*  t6     int    
                                                  +--*  t7     int    
N003 (  3,  3) [000008] J------N----              *  GE        void   $181
N004 (  5,  5) [000009] ------------              *  JTRUE     void   $VN.Void

------------ BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}
               [000028] ------------                 IL_OFFSET void   INL01 @ 0x004[E-] <- INLRT @ 0x000[E-]
N001 (  1,  1) [000014] -c----------        t14 =    CNS_INT   int    42 $42
                                                  /--*  t14    int    
N003 (  5,  4) [000016] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:3

------------ BB03 [000..001), preds={BB01} succs={BB04}
               [000029] ------------                 IL_OFFSET void   INL01 @ 0x006[E-] <- INLRT @ 0x000[E-]
N001 (  1,  1) [000010] ------------        t10 =    LCL_VAR   int    V03 tmp2         u:1 (last use) $100
                                                  /--*  t10    int    
N003 (  5,  4) [000012] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:2

------------ BB04 [???..???) (return), preds={BB02,BB03} succs={}
               [000030] ------------                 IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  3,  2) [000017] ------------        t17 =    LCL_VAR   int    V02 tmp1         u:1 (last use) $1c0
                                                  /--*  t17    int    
N002 (  4,  3) [000005] ------------              *  RETURN    int    $VN.Void

-------------------------------------------------------------------------------------------------------------------

*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V00: refCnt =  1, refCntWtd = 1   
New refCnts for V03: refCnt =  1, refCntWtd = 2   
New refCnts for V03: refCnt =  2, refCntWtd = 4   
New refCnts for V02: refCnt =  1, refCntWtd = 0.18
New refCnts for V03: refCnt =  3, refCntWtd = 4.63
New refCnts for V02: refCnt =  2, refCntWtd = 0.50
New refCnts for V02: refCnt =  3, refCntWtd = 1.50

*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt =  2, refCntWtd = 2   
New refCnts for V00: refCnt =  3, refCntWtd = 3   
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
;  V00 arg0              ref  class-hnd single-def
;  V01 OutArgs        lclBlk <0>  "OutgoingArgSpace"
;  V02 tmp1              int  "Inline return value spill temp"
;  V03 tmp2              int  "Inlining Arg"
In fgLocalVarLivenessInit
Tracked variable (3 out of 4) table:
V00 arg0          [   ref]: refCnt =    3, refCntWtd =   3   
V03 tmp2          [   int]: refCnt =    3, refCntWtd =   4.63
V02 tmp1          [   int]: refCnt =    3, refCntWtd =   1.50

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00    } + ByrefExposed + GcHeap
     DEF(1)={    V03}

BB02 USE(0)={   }
     DEF(1)={V02}

BB03 USE(1)={V03    }
     DEF(1)={    V02}

BB04 USE(1)={V02}
     DEF(0)={   }

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (1)={V00    } + ByrefExposed + GcHeap
     OUT(1)={    V03}

BB02 IN (0)={   }
     OUT(1)={V02}

BB03 IN (1)={V03    }
     OUT(1)={    V02}

BB04 IN (1)={V02}
     OUT(0)={   }


*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC LIR 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC LIR 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC LIR 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V00: refCnt =  1, refCntWtd = 1   
New refCnts for V03: refCnt =  1, refCntWtd = 2   
New refCnts for V03: refCnt =  2, refCntWtd = 4   
New refCnts for V02: refCnt =  1, refCntWtd = 0.18
New refCnts for V03: refCnt =  3, refCntWtd = 4.63
New refCnts for V02: refCnt =  2, refCntWtd = 0.50
New refCnts for V02: refCnt =  3, refCntWtd = 1.50

*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt =  2, refCntWtd = 2   
New refCnts for V00: refCnt =  3, refCntWtd = 3   

*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC LIR 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC LIR 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC LIR 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}
               [000026] ------------                 IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  1,  1) [000000] ------------         t0 =    LCL_VAR   ref    V00 arg0         u:1 (last use) $80
                                                  /--*  t0     ref    
               [000032] -c----------        t32 = *  LEA(b+8)  ref   
                                                  /--*  t32    ref    
N002 (  3,  3) [000001] ---X--------         t1 = *  IND       int    $180
                                                  /--*  t1     int    
N004 (  3,  3) [000019] DA-X--------              *  STORE_LCL_VAR int    V03 tmp2         d:1
               [000027] ------------                 IL_OFFSET void   INL01 @ 0x000[E-] <- INLRT @ 0x000[E-]
N001 (  1,  1) [000006] ------------         t6 =    LCL_VAR   int    V03 tmp2         u:1 $100
N002 (  1,  1) [000007] -c----------         t7 =    CNS_INT   int    42 $42
                                                  /--*  t6     int    
                                                  +--*  t7     int    
N003 (  3,  3) [000008] J------N----              *  GE        void   $181
N004 (  5,  5) [000009] ------------              *  JTRUE     void   $VN.Void

------------ BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}
               [000028] ------------                 IL_OFFSET void   INL01 @ 0x004[E-] <- INLRT @ 0x000[E-]
N001 (  1,  1) [000014] -c----------        t14 =    CNS_INT   int    42 $42
                                                  /--*  t14    int    
N003 (  5,  4) [000016] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:3

------------ BB03 [000..001), preds={BB01} succs={BB04}
               [000029] ------------                 IL_OFFSET void   INL01 @ 0x006[E-] <- INLRT @ 0x000[E-]
N001 (  1,  1) [000010] ------------        t10 =    LCL_VAR   int    V03 tmp2         u:1 (last use) $100
                                                  /--*  t10    int    
N003 (  5,  4) [000012] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:2

------------ BB04 [???..???) (return), preds={BB02,BB03} succs={}
               [000030] ------------                 IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  3,  2) [000017] ------------        t17 =    LCL_VAR   int    V02 tmp1         u:1 (last use) $1c0
                                                  /--*  t17    int    
N002 (  4,  3) [000005] ------------              *  RETURN    int    $VN.Void

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Trees before Calculate stack level slots

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC LIR 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC LIR 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC LIR 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}
               [000026] ------------                 IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  1,  1) [000000] ------------         t0 =    LCL_VAR   ref    V00 arg0         u:1 (last use) $80
                                                  /--*  t0     ref    
               [000032] -c----------        t32 = *  LEA(b+8)  ref   
                                                  /--*  t32    ref    
N002 (  3,  3) [000001] ---X--------         t1 = *  IND       int    $180
                                                  /--*  t1     int    
N004 (  3,  3) [000019] DA-X--------              *  STORE_LCL_VAR int    V03 tmp2         d:1
               [000027] ------------                 IL_OFFSET void   INL01 @ 0x000[E-] <- INLRT @ 0x000[E-]
N001 (  1,  1) [000006] ------------         t6 =    LCL_VAR   int    V03 tmp2         u:1 $100
N002 (  1,  1) [000007] -c----------         t7 =    CNS_INT   int    42 $42
                                                  /--*  t6     int    
                                                  +--*  t7     int    
N003 (  3,  3) [000008] J------N----              *  GE        void   $181
N004 (  5,  5) [000009] ------------              *  JTRUE     void   $VN.Void

------------ BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}
               [000028] ------------                 IL_OFFSET void   INL01 @ 0x004[E-] <- INLRT @ 0x000[E-]
N001 (  1,  1) [000014] -c----------        t14 =    CNS_INT   int    42 $42
                                                  /--*  t14    int    
N003 (  5,  4) [000016] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:3

------------ BB03 [000..001), preds={BB01} succs={BB04}
               [000029] ------------                 IL_OFFSET void   INL01 @ 0x006[E-] <- INLRT @ 0x000[E-]
N001 (  1,  1) [000010] ------------        t10 =    LCL_VAR   int    V03 tmp2         u:1 (last use) $100
                                                  /--*  t10    int    
N003 (  5,  4) [000012] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:2

------------ BB04 [???..???) (return), preds={BB02,BB03} succs={}
               [000030] ------------                 IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  3,  2) [000017] ------------        t17 =    LCL_VAR   int    V02 tmp1         u:1 (last use) $1c0
                                                  /--*  t17    int    
N002 (  4,  3) [000005] ------------              *  RETURN    int    $VN.Void

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Calculate stack level slots

*************** Finishing PHASE Calculate stack level slots [no changes]

*************** Starting PHASE Linear scan register alloc
Clearing modified regs.

buildIntervals ========

-----------------
LIVENESS:
-----------------
BB01 use def in out
{V00}
{V03}
{V00}
{V03}
BB02 use def in out
{}
{V02}
{}
{V02}
BB03 use def in out
{V03}
{V02}
{V03}
{V02}
BB04 use def in out
{V02}
{}
{V02}
{}
Interval  0: ref RefPositions {} physReg:NA Preferences=[allInt]
  Interval  0: (V00) ref RefPositions {} physReg:NA Preferences=[allInt]
Interval  1: int RefPositions {} physReg:NA Preferences=[allInt]
  Interval  1: (V02) int RefPositions {} physReg:NA Preferences=[allInt]
Interval  2: int RefPositions {} physReg:NA Preferences=[allInt]
  Interval  2: (V03) int RefPositions {} physReg:NA Preferences=[allInt]

FP callee save candidate vars: None

floatVarCount = 0; hasLoops = false, singleExit = true
TUPLE STYLE DUMP BEFORE LSRA
Start LSRA Block Sequence: 
Current block: BB01
	Succ block: BB02, Criteria: weight, Worklist: [BB02 ]
	Succ block: BB03, Criteria: bbNum, Worklist: [BB02 BB03 ]
Current block: BB02
	Succ block: BB04, Criteria: weight, Worklist: [BB03 BB04 ]
Current block: BB03
Current block: BB04
Final LSRA Block Sequence: 
BB01(  1   ) 
BB02(  0.18) 
BB03(  0.32) 
BB04(  1   ) 

BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
  N000.                    IL_OFFSET INLRT @ 0x000[E-]
  N001.                    V00(t0*)
  N000. t32             =  LEA(b+8) ; t0*
  N002. t1              =  IND      ; t32
  N004.                    V03(t19); t1
  N000.                    IL_OFFSET INL01 @ 0x000[E-] <- INLRT @ 0x000[E-]
  N001.                    V03(t6)
  N002.                    CNS_INT   42
  N003.                    GE       ; t6
  N004.                    JTRUE    

BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}
=====
  N000.                    IL_OFFSET INL01 @ 0x004[E-] <- INLRT @ 0x000[E-]
  N001.                    CNS_INT   42
  N003.                    V02(t16)

BB03 [000..001), preds={BB01} succs={BB04}
=====
  N000.                    IL_OFFSET INL01 @ 0x006[E-] <- INLRT @ 0x000[E-]
  N001.                    V03(t10*)
  N003.                    V02(t12); t10*

BB04 [???..???) (return), preds={BB02,BB03} succs={}
=====
  N000.                    IL_OFFSET INLRT @ 0x000[E-]
  N001.                    V02(t17*)
  N002.                    RETURN   ; t17*




buildIntervals second part ========
Int arg V00 in reg rcx
<RefPosition #0   @0   RefTypeParamDef <Ivl:0 V00>  BB00 regmask=[rcx] minReg=1 fixed wt=100.00>

NEW BLOCK BB01
<RefPosition #1   @1   RefTypeBB  BB01 regmask=[] minReg=1 wt=100.00>

DefList: {  }
N003 (???,???) [000026] ------------              *  IL_OFFSET void   INLRT @ 0x000[E-] REG NA

DefList: {  }
N005 (  1,  1) [000000] ------------              *  LCL_VAR   ref    V00 arg0         u:1 NA (last use) REG NA $80

DefList: {  }
N007 (???,???) [000032] -c----------              *  LEA(b+8)  ref    REG NA
Contained
DefList: {  }
N009 (  3,  3) [000001] ---X--------              *  IND       int    REG NA $180
<RefPosition #2   @9   RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
Interval  3: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #3   @10  RefTypeDef <Ivl:3> IND BB01 regmask=[allInt] minReg=1 wt=400.00>

DefList: { N009.t1. IND }
N011 (  3,  3) [000019] DA-X--------              *  STORE_LCL_VAR int    V03 tmp2         d:1 NA REG NA
<RefPosition #4   @11  RefTypeUse <Ivl:3>  BB01 regmask=[allInt] minReg=1 last wt=100.00>
Assigning related <V03/L2> to <I3>
<RefPosition #5   @12  RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=463.43>

DefList: {  }
N013 (???,???) [000027] ------------              *  IL_OFFSET void   INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] REG NA

DefList: {  }
N015 (  1,  1) [000006] ------------              *  LCL_VAR   int    V03 tmp2         u:1 NA REG NA $100

DefList: {  }
N017 (  1,  1) [000007] -c----------              *  CNS_INT   int    42 REG NA $42
Contained
DefList: {  }
N019 (  3,  3) [000008] J------N----              *  GE        void   REG NA $181
<RefPosition #6   @19  RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=463.43>

DefList: {  }
N021 (  5,  5) [000009] ------------              *  JTRUE     void   REG NA $VN.Void



CHECKING LAST USES for BB01, liveout={V03}
==============================
use: {V00}
def: {V03}

NEW BLOCK BB02


Setting BB01 as the predecessor for determining incoming variable registers of BB02
<RefPosition #7   @23  RefTypeBB  BB02 regmask=[] minReg=1 wt=18.28>

DefList: {  }
N025 (???,???) [000028] ------------              *  IL_OFFSET void   INL01 @ 0x004[E-] <- INLRT @ 0x000[E-] REG NA

DefList: {  }
N027 (  1,  1) [000014] -c----------              *  CNS_INT   int    42 REG NA $42
Contained
DefList: {  }
N029 (  5,  4) [000016] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:3 NA REG NA
<RefPosition #8   @30  RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last wt=150.00>



CHECKING LAST USES for BB02, liveout={V02}
==============================
use: {}
def: {V02}

NEW BLOCK BB03


Setting BB01 as the predecessor for determining incoming variable registers of BB03
<RefPosition #9   @31  RefTypeBB  BB03 regmask=[] minReg=1 wt=31.72>

DefList: {  }
N033 (???,???) [000029] ------------              *  IL_OFFSET void   INL01 @ 0x006[E-] <- INLRT @ 0x000[E-] REG NA

DefList: {  }
N035 (  1,  1) [000010] ------------              *  LCL_VAR   int    V03 tmp2         u:1 NA (last use) REG NA $100

DefList: {  }
N037 (  5,  4) [000012] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:2 NA REG NA
<RefPosition #10  @37  RefTypeUse <Ivl:2 V03> LCL_VAR BB03 regmask=[allInt] minReg=1 last wt=463.43>
Assigning related <V02/L1> to <V03/L2>
<RefPosition #11  @38  RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 last wt=150.00>



CHECKING LAST USES for BB03, liveout={V02}
==============================
use: {V03}
def: {V02}

NEW BLOCK BB04


Setting BB03 as the predecessor for determining incoming variable registers of BB04
<RefPosition #12  @39  RefTypeBB  BB04 regmask=[] minReg=1 wt=100.00>

DefList: {  }
N041 (???,???) [000030] ------------              *  IL_OFFSET void   INLRT @ 0x000[E-] REG NA

DefList: {  }
N043 (  3,  2) [000017] ------------              *  LCL_VAR   int    V02 tmp1         u:1 NA (last use) REG NA $1c0

DefList: {  }
N045 (  4,  3) [000005] ------------              *  RETURN    int    REG NA $VN.Void
<RefPosition #13  @45  RefTypeFixedReg <Reg:rax>  BB04 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #14  @45  RefTypeUse <Ivl:1 V02> LCL_VAR BB04 regmask=[rax] minReg=1 last fixed wt=150.00>



CHECKING LAST USES for BB04, liveout={}
==============================
use: {V02}
def: {}

Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval  0: (V00) ref RefPositions {#0@0 #2@9} physReg:rcx Preferences=[rcx]
Interval  1: (V02) int RefPositions {#8@30 #11@38 #14@45} physReg:NA Preferences=[rax]
Interval  2: (V03) int RefPositions {#5@12 #6@19 #10@37} physReg:NA Preferences=[allInt] RelatedInterval <V02/L1>
Interval  3: int RefPositions {#3@10 #4@11} physReg:NA Preferences=[allInt] RelatedInterval <V03/L2>

------------
REFPOSITIONS BEFORE VALIDATING INTERVALS: 
------------
<RefPosition #0   @0   RefTypeParamDef <Ivl:0 V00>  BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1   @1   RefTypeBB  BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #2   @9   RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
<RefPosition #3   @10  RefTypeDef <Ivl:3> IND BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #4   @11  RefTypeUse <Ivl:3>  BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #5   @12  RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=463.43>
<RefPosition #6   @19  RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional wt=463.43>
<RefPosition #7   @23  RefTypeBB  BB02 regmask=[] minReg=1 wt=18.28>
<RefPosition #8   @30  RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 wt=150.00>
<RefPosition #9   @31  RefTypeBB  BB03 regmask=[] minReg=1 wt=31.72>
<RefPosition #10  @37  RefTypeUse <Ivl:2 V03> LCL_VAR BB03 regmask=[allInt] minReg=1 last wt=463.43>
<RefPosition #11  @38  RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 wt=150.00>
<RefPosition #12  @39  RefTypeBB  BB04 regmask=[] minReg=1 wt=100.00>
<RefPosition #13  @45  RefTypeFixedReg <Reg:rax>  BB04 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #14  @45  RefTypeUse <Ivl:1 V02> LCL_VAR BB04 regmask=[rax] minReg=1 last fixed wt=150.00>
-----------------
<RefPosition #0   @0   RefTypeParamDef <Ivl:0 V00>  BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2   @9   RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
-----------------
<RefPosition #5   @12  RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=463.43>
<RefPosition #6   @19  RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional wt=463.43>
<RefPosition #10  @37  RefTypeUse <Ivl:2 V03> LCL_VAR BB03 regmask=[allInt] minReg=1 last wt=463.43>
-----------------
<RefPosition #8   @30  RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 wt=150.00>
<RefPosition #11  @38  RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 wt=150.00>
<RefPosition #14  @45  RefTypeUse <Ivl:1 V02> LCL_VAR BB04 regmask=[rax] minReg=1 last fixed wt=150.00>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters:  V00
BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
  N003.                    IL_OFFSET INLRT @ 0x000[E-]
  N005.                    V00(L0)
  N007.                    LEA(b+8) 
  N009.                    IND      
                               Use:<V00/L0>(#2) *
        Def:<I3>(#3) Pref:<V03/L2>
  N011.                    V03(L2)
                               Use:<I3>(#4) *
        Def:<V03/L2>(#5) Pref:<V02/L1>
  N013.                    IL_OFFSET INL01 @ 0x000[E-] <- INLRT @ 0x000[E-]
  N015.                    V03(L2)
  N017.                    CNS_INT   42
  N019.                    GE       
                               Use:<V03/L2>(#6)
  N021.                    JTRUE    

BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}
=====
  N025.                    IL_OFFSET INL01 @ 0x004[E-] <- INLRT @ 0x000[E-]
  N027.                    CNS_INT   42
  N029.                    V02(L1)
        Def:<V02/L1>(#8)

BB03 [000..001), preds={BB01} succs={BB04}
=====
  N033.                    IL_OFFSET INL01 @ 0x006[E-] <- INLRT @ 0x000[E-]
  N035.                    V03(L2)
  N037.                    V02(L1)
                               Use:<V03/L2>(#10) *
        Def:<V02/L1>(#11)

BB04 [???..???) (return), preds={BB02,BB03} succs={}
=====
  N041.                    IL_OFFSET INLRT @ 0x000[E-]
  N043.                    V02(L1)
  N045.                    RETURN   
                               Use:<V02/L1>(#14) Fixed:rax(#13) *




Linear scan intervals after buildIntervals:
Interval  0: (V00) ref RefPositions {#0@0 #2@9} physReg:rcx Preferences=[rcx]
Interval  1: (V02) int RefPositions {#8@30 #11@38 #14@45} physReg:NA Preferences=[rax]
Interval  2: (V03) int RefPositions {#5@12 #6@19 #10@37} physReg:NA Preferences=[allInt] RelatedInterval <V02/L1>
Interval  3: int RefPositions {#3@10 #4@11} physReg:NA Preferences=[allInt] RelatedInterval <V03/L2>

*************** In LinearScan::allocateRegisters()

Linear scan intervals before allocateRegisters:
Interval  0: (V00) ref RefPositions {#0@0 #2@9} physReg:rcx Preferences=[rcx]
Interval  1: (V02) int RefPositions {#8@30 #11@38 #14@45} physReg:NA Preferences=[rax]
Interval  2: (V03) int RefPositions {#5@12 #6@19 #10@37} physReg:NA Preferences=[allInt] RelatedInterval <V02/L1>
Interval  3: int RefPositions {#3@10 #4@11} physReg:NA Preferences=[allInt] RelatedInterval <V03/L2>

------------
REFPOSITIONS BEFORE ALLOCATION: 
------------
<RefPosition #0   @0   RefTypeParamDef <Ivl:0 V00>  BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1   @1   RefTypeBB  BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #2   @9   RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
<RefPosition #3   @10  RefTypeDef <Ivl:3> IND BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #4   @11  RefTypeUse <Ivl:3>  BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #5   @12  RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=463.43>
<RefPosition #6   @19  RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional wt=463.43>
<RefPosition #7   @23  RefTypeBB  BB02 regmask=[] minReg=1 wt=18.28>
<RefPosition #8   @30  RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 wt=150.00>
<RefPosition #9   @31  RefTypeBB  BB03 regmask=[] minReg=1 wt=31.72>
<RefPosition #10  @37  RefTypeUse <Ivl:2 V03> LCL_VAR BB03 regmask=[allInt] minReg=1 last wt=463.43>
<RefPosition #11  @38  RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 wt=150.00>
<RefPosition #12  @39  RefTypeBB  BB04 regmask=[] minReg=1 wt=100.00>
<RefPosition #13  @45  RefTypeFixedReg <Reg:rax>  BB04 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #14  @45  RefTypeUse <Ivl:1 V02> LCL_VAR BB04 regmask=[rax] minReg=1 last fixed wt=150.00>

VAR REFPOSITIONS BEFORE ALLOCATION
--- V00  (Interval 0)
<RefPosition #0   @0   RefTypeParamDef <Ivl:0 V00>  BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2   @9   RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
--- V01
--- V02  (Interval 1)
<RefPosition #8   @30  RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 wt=150.00>
<RefPosition #11  @38  RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 wt=150.00>
<RefPosition #14  @45  RefTypeUse <Ivl:1 V02> LCL_VAR BB04 regmask=[rax] minReg=1 last fixed wt=150.00>
--- V03  (Interval 2)
<RefPosition #5   @12  RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=463.43>
<RefPosition #6   @19  RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional wt=463.43>
<RefPosition #10  @37  RefTypeUse <Ivl:2 V03> LCL_VAR BB03 regmask=[allInt] minReg=1 last wt=463.43>



Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive.
Columns are only printed up to the last modifed register, which may increase during allocation,
in which case additional columns will appear.  
Registers which are not marked modified have ---- in their column.

---------------------------------+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
---------------------------------+----+----+----+----+----+----+----+----+----+
                                 |    |V0 a|    |    |    |    |    |    |    |
 0.#0  V0   Parm   Keep     rcx  |    |V0 a|    |    |    |    |    |    |    |
 1.#1  BB1 PredBB0               |    |V0 a|    |    |    |    |    |    |    |
 9.#2  V0   Use *  Keep     rcx  |    |V0 a|    |    |    |    |    |    |    |
10.#3  I3   Def    COREL(A) rax  |I3 a|    |    |    |    |    |    |    |    |
11.#4  I3   Use *  Keep     rax  |I3 a|    |    |    |    |    |    |    |    |
12.#5  V3   Def    COVRS(A) rax  |V3 a|    |    |    |    |    |    |    |    |
19.#6  V3   Use    Keep     rax  |V3 a|    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
---------------------------------+----+----+----+----+----+----+----+----+----+
23.#7  BB2 PredBB1               |V3 i|    |    |    |    |    |    |    |    |
30.#8  V2   Def    OWNPR(A) rax  |V2 a|    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
---------------------------------+----+----+----+----+----+----+----+----+----+
31.#9  BB3 PredBB1               |V3 a|    |    |    |    |    |    |    |    |
37.#10 V3   Use *  Keep     rax  |V3 a|    |    |    |    |    |    |    |    |
38.#11 V2   Def    THISA(A) rax  |V2 a|    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
---------------------------------+----+----+----+----+----+----+----+----+----+
39.#12 BB4 PredBB3               |V2 a|    |    |    |    |    |    |    |    |
45.#13 rax  Fixd   Keep     rax  |V2 a|    |    |    |    |    |    |    |    |
45.#14 V2   Use *  Keep     rax  |    |    |    |    |    |    |    |    |    |

------------
REFPOSITIONS AFTER ALLOCATION: 
------------
<RefPosition #0   @0   RefTypeParamDef <Ivl:0 V00>  BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1   @1   RefTypeBB  BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #2   @9   RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 last wt=300.00>
<RefPosition #3   @10  RefTypeDef <Ivl:3> IND BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #4   @11  RefTypeUse <Ivl:3>  BB01 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #5   @12  RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[rax] minReg=1 wt=463.43>
<RefPosition #6   @19  RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[rax] minReg=1 regOptional wt=463.43>
<RefPosition #7   @23  RefTypeBB  BB02 regmask=[] minReg=1 wt=18.28>
<RefPosition #8   @30  RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB02 regmask=[rax] minReg=1 wt=150.00>
<RefPosition #9   @31  RefTypeBB  BB03 regmask=[] minReg=1 wt=31.72>
<RefPosition #10  @37  RefTypeUse <Ivl:2 V03> LCL_VAR BB03 regmask=[rax] minReg=1 last wt=463.43>
<RefPosition #11  @38  RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB03 regmask=[rax] minReg=1 wt=150.00>
<RefPosition #12  @39  RefTypeBB  BB04 regmask=[] minReg=1 wt=100.00>
<RefPosition #13  @45  RefTypeFixedReg <Reg:rax>  BB04 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #14  @45  RefTypeUse <Ivl:1 V02> LCL_VAR BB04 regmask=[rax] minReg=1 last fixed wt=150.00>

VAR REFPOSITIONS AFTER ALLOCATION
--- V00  (Interval 0)
<RefPosition #0   @0   RefTypeParamDef <Ivl:0 V00>  BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2   @9   RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 last wt=300.00>
--- V01
--- V02  (Interval 1)
<RefPosition #8   @30  RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB02 regmask=[rax] minReg=1 wt=150.00>
<RefPosition #11  @38  RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB03 regmask=[rax] minReg=1 wt=150.00>
<RefPosition #14  @45  RefTypeUse <Ivl:1 V02> LCL_VAR BB04 regmask=[rax] minReg=1 last fixed wt=150.00>
--- V03  (Interval 2)
<RefPosition #5   @12  RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[rax] minReg=1 wt=463.43>
<RefPosition #6   @19  RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[rax] minReg=1 regOptional wt=463.43>
<RefPosition #10  @37  RefTypeUse <Ivl:2 V03> LCL_VAR BB03 regmask=[rax] minReg=1 last wt=463.43>

Active intervals at end of allocation:

-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {V00 V02 V03}
Has No Critical Edges

Prior to Resolution

BB01
use def in out
{V00}
{V03}
{V00}
{V03}
Var=Reg beg of BB01: V00=rcx 
Var=Reg end of BB01: V03=rax 

BB02
use def in out
{}
{V02}
{}
{V02}
Var=Reg beg of BB02: none
Var=Reg end of BB02: V02=rax 

BB03
use def in out
{V03}
{V02}
{V03}
{V02}
Var=Reg beg of BB03: V03=rax 
Var=Reg end of BB03: V02=rax 

BB04
use def in out
{V02}
{}
{V02}
{}
Var=Reg beg of BB04: V02=rax 
Var=Reg end of BB04: none


RESOLVING EDGES
  Set V00 argument initial register to rcx
Trees after linear scan register allocator (LSRA)

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC LIR 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC LIR 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC LIR 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}
N003 (???,???) [000026] ------------                 IL_OFFSET void   INLRT @ 0x000[E-] REG NA
N005 (  1,  1) [000000] ------------         t0 =    LCL_VAR   ref    V00 arg0         u:1 rcx (last use) REG rcx $80
                                                  /--*  t0     ref    
N007 (???,???) [000032] -c----------        t32 = *  LEA(b+8)  ref    REG NA
                                                  /--*  t32    ref    
N009 (  3,  3) [000001] ---X--------         t1 = *  IND       int    REG rax $180
                                                  /--*  t1     int    
N011 (  3,  3) [000019] DA-X--------              *  STORE_LCL_VAR int    V03 tmp2         d:1 rax REG rax
N013 (???,???) [000027] ------------                 IL_OFFSET void   INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] REG NA
N015 (  1,  1) [000006] ------------         t6 =    LCL_VAR   int    V03 tmp2         u:1 rax REG rax $100
N017 (  1,  1) [000007] -c----------         t7 =    CNS_INT   int    42 REG NA $42
                                                  /--*  t6     int    
                                                  +--*  t7     int    
N019 (  3,  3) [000008] J------N----              *  GE        void   REG NA $181
N021 (  5,  5) [000009] ------------              *  JTRUE     void   REG NA $VN.Void

------------ BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}
N025 (???,???) [000028] ------------                 IL_OFFSET void   INL01 @ 0x004[E-] <- INLRT @ 0x000[E-] REG NA
N027 (  1,  1) [000014] -c----------        t14 =    CNS_INT   int    42 REG NA $42
                                                  /--*  t14    int    
N029 (  5,  4) [000016] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:3 rax REG rax

------------ BB03 [000..001), preds={BB01} succs={BB04}
N033 (???,???) [000029] ------------                 IL_OFFSET void   INL01 @ 0x006[E-] <- INLRT @ 0x000[E-] REG NA
N035 (  1,  1) [000010] ------------        t10 =    LCL_VAR   int    V03 tmp2         u:1 rax (last use) REG rax $100
                                                  /--*  t10    int    
N037 (  5,  4) [000012] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:2 rax REG rax

------------ BB04 [???..???) (return), preds={BB02,BB03} succs={}
N041 (???,???) [000030] ------------                 IL_OFFSET void   INLRT @ 0x000[E-] REG NA
N043 (  3,  2) [000017] ------------        t17 =    LCL_VAR   int    V02 tmp1         u:1 rax (last use) REG rax $1c0
                                                  /--*  t17    int    
N045 (  4,  3) [000005] ------------              *  RETURN    int    REG NA $VN.Void

-------------------------------------------------------------------------------------------------------------------

Final allocation
---------------------------------+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
---------------------------------+----+----+----+----+----+----+----+----+----+
 0.#0  V0   Parm   Alloc    rcx  |    |V0 a|    |    |    |    |    |    |    |
 1.#1  BB1 PredBB0               |    |V0 a|    |    |    |    |    |    |    |
 9.#2  V0   Use *  Keep     rcx  |    |V0 i|    |    |    |    |    |    |    |
10.#3  I3   Def    Alloc    rax  |I3 a|    |    |    |    |    |    |    |    |
11.#4  I3   Use *  Keep     rax  |I3 i|    |    |    |    |    |    |    |    |
12.#5  V3   Def    Alloc    rax  |V3 a|    |    |    |    |    |    |    |    |
19.#6  V3   Use    Keep     rax  |V3 a|    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
---------------------------------+----+----+----+----+----+----+----+----+----+
23.#7  BB2 PredBB1               |    |    |    |    |    |    |    |    |    |
30.#8  V2   Def    Alloc    rax  |V2 a|    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
---------------------------------+----+----+----+----+----+----+----+----+----+
31.#9  BB3 PredBB1               |V3 a|    |    |    |    |    |    |    |    |
37.#10 V3   Use *  Keep     rax  |V3 i|    |    |    |    |    |    |    |    |
38.#11 V2   Def    Alloc    rax  |V2 a|    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
---------------------------------+----+----+----+----+----+----+----+----+----+
39.#12 BB4 PredBB3               |V2 a|    |    |    |    |    |    |    |    |
45.#13 rax  Fixd   Keep     rax  |V2 a|    |    |    |    |    |    |    |    |
45.#14 V2   Use *  Keep     rax  |V2 i|    |    |    |    |    |    |    |    |

Recording the maximum number of concurrent spills:

----------
LSRA Stats
----------
Register selection order: ABCDEFGHIJKLMNOPQ
Total Tracked Vars:  3
Total Reg Cand Vars: 3
Total number of Intervals: 3
Total number of RefPositions: 14
Total Number of spill temps created: 0
..........
BB01 [  100.00]: COVERS = 1, COVERS_RELATED = 1
BB02 [   18.28]: OWN_PREFERENCE = 1
BB03 [   31.72]: THIS_ASSIGNED = 1
..........
Total SpillCount : 0   Weighted: 0.000000
Total CopyReg : 0   Weighted: 0.000000
Total ResolutionMovs : 0   Weighted: 0.000000
Total SplitEdges : 0   Weighted: 0.000000
..........
Total THIS_ASSIGNED [# 3] : 1   Weighted: 31.717140
Total COVERS [# 4] : 1   Weighted: 100.000000
Total OWN_PREFERENCE [# 5] : 1   Weighted: 18.282860
Total COVERS_RELATED [# 6] : 1   Weighted: 100.000000

TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters:  V00(rcx)
BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
  N003.                    IL_OFFSET INLRT @ 0x000[E-]
  N005.                    V00(rcx*)
  N007. STK             =  LEA(b+8) ; rcx*
  N009. rax             =  IND      ; STK
* N011.                    V03(rax); rax
  N013.                    IL_OFFSET INL01 @ 0x000[E-] <- INLRT @ 0x000[E-]
  N015.                    V03(rax)
  N017.                    CNS_INT   42
  N019.                    GE       ; rax
  N021.                    JTRUE    
Var=Reg end of BB01: V03=rax 

BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB02: none
  N025.                    IL_OFFSET INL01 @ 0x004[E-] <- INLRT @ 0x000[E-]
  N027.                    CNS_INT   42
* N029.                    V02(rax)
Var=Reg end of BB02: V02=rax 

BB03 [000..001), preds={BB01} succs={BB04}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB03: V03=rax 
  N033.                    IL_OFFSET INL01 @ 0x006[E-] <- INLRT @ 0x000[E-]
  N035.                    V03(rax*)
* N037.                    V02(rax); rax*
Var=Reg end of BB03: V02=rax 

BB04 [???..???) (return), preds={BB02,BB03} succs={}
=====
Predecessor for variable locations: BB03
Var=Reg beg of BB04: V02=rax 
  N041.                    IL_OFFSET INLRT @ 0x000[E-]
  N043.                    V02(rax*)
  N045.                    RETURN   ; rax*
Var=Reg end of BB04: none




*************** Finishing PHASE Linear scan register alloc

*************** Starting PHASE Place 'align' instructions

*************** Finishing PHASE Place 'align' instructions
*************** In genGenerateCode()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i idxlen IBC LIR 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC LIR 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i IBC LIR 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal idxlen IBC LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
; Assembly listing for method Test.Program:Main(System.String[]):int
; Emitting BLENDED_CODE for X64 CPU with AVX - Windows
; optimized code
; rsp based frame
; partially interruptible
; No PGO data
; 1 inlinees with PGO data; 0 single block inlinees; 0 inlinees without PGO data
Finalizing stack frame
Recording Var Locations at start of BB01
  V00(rcx)
Modified regs: [rax rcx]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
--- delta bump 8 for RA
--- delta bump 0 for RSP frame
--- virtual stack offset to actual stack offset delta is 8
-- V00 was 0, now 8
-- V01 was 0, now 8
; Final local variable assignments
;
;  V00 arg0         [V00,T00] (  3,  3   )     ref  ->  rcx         class-hnd single-def
;# V01 OutArgs      [V01    ] (  1,  1   )  lclBlk ( 0) [rsp+00H]   "OutgoingArgSpace"
;  V02 tmp1         [V02,T02] (  3,  1.50)     int  ->  rax         "Inline return value spill temp"
;  V03 tmp2         [V03,T01] (  3,  4.63)     int  ->  rax         "Inlining Arg"
;
; Lcl frame size = 0
Mark labels for codegen
  BB01 : first block
  BB03 : branch target
  BB04 : branch target
*************** After genMarkLabelsForCodegen()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC  lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    100    [000..00B)-> BB03 ( cond )                     i label idxlen IBC LIR 
BB02 [0002]  1       BB01                  0.18  18    [000..001)-> BB04 (always)                     i IBC LIR 
BB03 [0003]  1       BB01                  0.32  32    [000..001)                                     i label IBC LIR 
BB04 [0004]  2       BB02,BB03             1    100    [???..???)        (return)                     internal label idxlen IBC LIR 
-----------------------------------------------------------------------------------------------------------------------------------------
Setting stack level from -572662307 to 0

=============== Generating BB01 [000..00B) -> BB03 (cond), preds={} succs={BB02,BB03} flags=0x00000000.30110020: i label idxlen IBC LIR 
BB01 IN (1)={V00    } + ByrefExposed + GcHeap
     OUT(1)={    V03}

Recording Var Locations at start of BB01
  V00(rcx)
Change life 0000000000000000 {} -> 0000000000000001 {V00}
							V00 in reg rcx is becoming live  [------]
							Live regs: 00000000 {} => 00000002 {rcx}
New debug range: first
							Live regs: (unchanged) 00000002 {rcx}
							GC regs: (unchanged) 00000002 {rcx}
							Byref regs: (unchanged) 00000000 {}

      L_M22359_BB01:
Mapped BB01 to G_M22359_IG02
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}

Scope info: begin block BB01, IL range [000..00B)
Added IP mapping: 0x0000 STACK_EMPTY (G_M22359_IG02,ins#0,ofs#0) label
Generating: N003 (???,???) [000026] ------------                 IL_OFFSET void   INLRT @ 0x000[E-] REG NA
Generating: N005 (  1,  1) [000000] ------------         t0 =    LCL_VAR   ref    V00 arg0         u:1 rcx (last use) REG rcx $80
                                                              /--*  t0     ref    
Generating: N007 (???,???) [000032] -c----------        t32 = *  LEA(b+8)  ref    REG NA
                                                              /--*  t32    ref    
Generating: N009 (  3,  3) [000001] ---X--------         t1 = *  IND       int    REG rax $180
							V00 in reg rcx is becoming dead  [000000]
							Live regs: 00000002 {rcx} => 00000000 {}
							Live vars: {V00} => {}
							GC regs: 00000002 {rcx} => 00000000 {}
IN0001:        mov      eax, dword ptr [rcx+8]
                                                              /--*  t1     int    
Generating: N011 (  3,  3) [000019] DA-X--------              *  STORE_LCL_VAR int    V03 tmp2         d:1 rax REG rax
							V03 in reg rax is becoming live  [000019]
							Live regs: 00000000 {} => 00000001 {rax}
							Live vars: {} => {V03}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N013 (???,???) [000027] ------------                 IL_OFFSET void   INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] REG NA
Generating: N015 (  1,  1) [000006] ------------         t6 =    LCL_VAR   int    V03 tmp2         u:1 rax REG rax $100
Generating: N017 (  1,  1) [000007] -c----------         t7 =    CNS_INT   int    42 REG NA $42
                                                              /--*  t6     int    
                                                              +--*  t7     int    
Generating: N019 (  3,  3) [000008] J------N----              *  GE        void   REG NA $181
IN0002:        cmp      eax, 42
Generating: N021 (  5,  5) [000009] ------------              *  JTRUE     void   REG NA $VN.Void
IN0003:        jge      L_M22359_BB03

Variable Live Range History Dump for BB01
V00 arg0: rcx [(G_M22359_IG02,ins#0,ofs#0), (G_M22359_IG02,ins#0,ofs#0)]

=============== Generating BB02 [000..001) -> BB04 (always), preds={BB01} succs={BB04} flags=0x00000000.30000020: i IBC LIR 
BB02 IN (0)={   }
     OUT(1)={V02}

Recording Var Locations at start of BB02
  <none>

Change life 0000000000000002 {V03} -> 0000000000000000 {}
							V03 in reg rax is becoming dead  [------]
							Live regs: (unchanged) 00000000 {}
							Live regs: (unchanged) 00000000 {}
							GC regs: (unchanged) 00000000 {}
							Byref regs: (unchanged) 00000000 {}

      L_M22359_BB02:
Adding label due to BB weight difference: BBJ_COND BB01 with weight 100 different from BB02 with weight 18.28286

      G_M22359_IG02:        ; offs=000000H, funclet=00, bbWeight=1   
Mapped BB02 to G_M22359_IG03
Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}

Scope info: begin block BB02, IL range [000..001)
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N025 (???,???) [000028] ------------                 IL_OFFSET void   INL01 @ 0x004[E-] <- INLRT @ 0x000[E-] REG NA
Generating: N027 (  1,  1) [000014] -c----------        t14 =    CNS_INT   int    42 REG NA $42
                                                              /--*  t14    int    
Generating: N029 (  5,  4) [000016] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:3 rax REG rax
IN0004:        mov      eax, 42
							V02 in reg rax is becoming live  [000016]
							Live regs: 00000000 {} => 00000001 {rax}
							Live vars: {} => {V02}
IN0005:        jmp      L_M22359_BB04

Variable Live Range History Dump for BB02
..None..

=============== Generating BB03 [000..001), preds={BB01} succs={BB04} flags=0x00000000.30010020: i label IBC LIR 
BB03 IN (1)={V03    }
     OUT(1)={    V02}

Recording Var Locations at start of BB03
  V03(rax)
Change life 0000000000000004 {V02} -> 0000000000000002 {V03}
							V02 in reg rax is becoming dead  [------]
							Live regs: (unchanged) 00000000 {}
							V03 in reg rax is becoming live  [------]
							Live regs: 00000000 {} => 00000001 {rax}
							Live regs: (unchanged) 00000001 {rax}
							GC regs: (unchanged) 00000000 {}
							Byref regs: (unchanged) 00000000 {}

      L_M22359_BB03:

      G_M22359_IG03:        ; offs=00000CH, funclet=00, bbWeight=0.18
Mapped BB03 to G_M22359_IG04
Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}

Scope info: begin block BB03, IL range [000..001)
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N033 (???,???) [000029] ------------                 IL_OFFSET void   INL01 @ 0x006[E-] <- INLRT @ 0x000[E-] REG NA
Generating: N035 (  1,  1) [000010] ------------        t10 =    LCL_VAR   int    V03 tmp2         u:1 rax (last use) REG rax $100
                                                              /--*  t10    int    
Generating: N037 (  5,  4) [000012] DA----------              *  STORE_LCL_VAR int    V02 tmp1         d:2 rax REG rax
							V03 in reg rax is becoming dead  [000010]
							Live regs: 00000001 {rax} => 00000000 {}
							Live vars: {V03} => {}
							V02 in reg rax is becoming live  [000012]
							Live regs: 00000000 {} => 00000001 {rax}
							Live vars: {} => {V02}

Variable Live Range History Dump for BB03
..None..

=============== Generating BB04 [???..???) (return), preds={BB02,BB03} succs={} flags=0x00000000.30110040: internal label idxlen IBC LIR 
BB04 IN (1)={V02}
     OUT(0)={   }

Recording Var Locations at start of BB04
  V02(rax)
Liveness not changing: 0000000000000004 {V02}
							Live regs: 00000000 {} => 00000001 {rax}
							GC regs: (unchanged) 00000000 {}
							Byref regs: (unchanged) 00000000 {}

      L_M22359_BB04:
Mapped BB04 to G_M22359_IG04
Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}

Scope info: begin block BB04, IL range [???..???)
Scope info: ignoring block beginning
Added IP mapping: NO_MAP (G_M22359_IG04,ins#0,ofs#0) label
Added IP mapping: 0x0000 STACK_EMPTY (G_M22359_IG04,ins#0,ofs#0) label
Generating: N041 (???,???) [000030] ------------                 IL_OFFSET void   INLRT @ 0x000[E-] REG NA
Generating: N043 (  3,  2) [000017] ------------        t17 =    LCL_VAR   int    V02 tmp1         u:1 rax (last use) REG rax $1c0
                                                              /--*  t17    int    
Generating: N045 (  4,  3) [000005] ------------              *  RETURN    int    REG NA $VN.Void
							V02 in reg rax is becoming dead  [000017]
							Live regs: 00000001 {rax} => 00000000 {}
							Live vars: {V02} => {}
Scope info: ignoring block end
Added IP mapping: EPILOG (G_M22359_IG04,ins#0,ofs#0) label
Reserving epilog IG for block BB04
*************** After placeholder IG creation
G_M22359_IG01:        ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M22359_IG02:        ; offs=000000H, size=000CH, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, BB01 [0000], byref
G_M22359_IG03:        ; offs=00000CH, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB02 [0002], byref
G_M22359_IG04:        ; epilog placeholder, next placeholder=<END>, BB04 [0004], epilog <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}

Variable Live Range History Dump for BB04
..None..
Liveness not changing: 0000000000000000 {}

# compCycleEstimate =     22, compSizeEstimate =    19 Test.Program:Main(System.String[]):int
; Final local variable assignments
;
;  V00 arg0         [V00,T00] (  3,  3   )     ref  ->  rcx         class-hnd single-def
;# V01 OutArgs      [V01    ] (  1,  1   )  lclBlk ( 0) [rsp+00H]   "OutgoingArgSpace"
;  V02 tmp1         [V02,T02] (  3,  1.50)     int  ->  rax         "Inline return value spill temp"
;  V03 tmp2         [V03,T01] (  3,  4.63)     int  ->  rax         "Inlining Arg"
;
; Lcl frame size = 0
*************** Before prolog / epilog generation
G_M22359_IG01:        ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M22359_IG02:        ; offs=000000H, size=000CH, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, BB01 [0000], byref
G_M22359_IG03:        ; offs=00000CH, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB02 [0002], byref
G_M22359_IG04:        ; epilog placeholder, next placeholder=<END>, BB04 [0004], epilog <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Recording Var Locations at start of BB01
  V00(rcx)
*************** In genFnProlog()
Added IP mapping to front: PROLOG (G_M22359_IG01,ins#0,ofs#0) label

__prolog:
New debug range: first
*************** In genFnPrologCalleeRegArgs() for int regs
*************** In genEnregisterIncomingStackArgs()


      G_M22359_IG01:        ; offs=000000H, funclet=00, bbWeight=1   
*************** In genFnEpilog()

__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN0006:        ret      

      G_M22359_IG04:        ; offs=000016H, funclet=00, bbWeight=1   
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M22359_IG01:        ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M22359_IG02:        ; offs=000000H, size=000CH, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, BB01 [0000], byref
G_M22359_IG03:        ; offs=00000CH, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB02 [0002], byref
G_M22359_IG04:        ; offs=000016H, size=0001H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc
*************** In emitJumpDistBind()
Binding: IN0003: 000000 jge      L_M22359_BB03
Binding L_M22359_BB03 to G_M22359_IG04
Estimate of fwd jump [2F487B64/003]: 0006 -> 0016 = 000E
Shrinking jump [2F487B64/003]
Adjusted offset of BB03 from 000C to 0008
Binding: IN0005: 000000 jmp      L_M22359_BB04
Binding L_M22359_BB04 to G_M22359_IG04
Estimate of fwd jump [2F487D34/005]: 000D -> 0012 = 0003
Shrinking jump [2F487D34/005]
Adjusted offset of BB04 from 0016 to 000F
Total shrinkage =   7, min extra jump size = 4294967295

*************** Finishing PHASE Generate code

*************** Starting PHASE Emit code

Hot  code size = 0x10 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0x4)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)

***************************************************************************
Instructions as they come out of the scheduler


G_M22359_IG01:        ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
						;; size=0 bbWeight=1    PerfScore 0.00
G_M22359_IG02:        ; func=00, offs=000000H, size=0008H, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, BB01 [0000], byref, isz
                            ; gcrRegs +[rcx]
IN0001: 000000 8B4108               mov      eax, dword ptr [rcx+8]
IN0002: 000003 83F82A               cmp      eax, 42
IN0003: 000006 7D07                 jge      SHORT G_M22359_IG04
						;; size=8 bbWeight=1    PerfScore 3.25
G_M22359_IG03:        ; func=00, offs=000008H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB02 [0002], byref, isz
                            ; gcrRegs -[rcx]
IN0004: 000008 B82A000000           mov      eax, 42
IN0005: 00000D EB00                 jmp      SHORT G_M22359_IG04
						;; size=7 bbWeight=0.18 PerfScore 0.41
G_M22359_IG04:        ; func=00, offs=00000FH, size=0001H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc
IN0006: 00000F C3                   ret      
						;; size=1 bbWeight=1    PerfScore 1.00
Allocated method code size =   16 , actual size =   16, unused size =    0

; Total bytes of code 16, prolog size 0, PerfScore 6.26, instruction count 6, allocated bytes for code 16 (MethodHash=efe0a8a8) for method Test.Program:Main(System.String[]):int
; ============================================================

*************** After end code gen, before unwindEmit()
G_M22359_IG01:        ; func=00, offs=000000H, size=0000H, bbWeight=1    PerfScore 0.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M22359_IG02:        ; offs=000000H, size=0008H, bbWeight=1    PerfScore 3.25, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, BB01 [0000], byref, isz

IN0001: 000000 mov      eax, dword ptr [rcx+8]
IN0002: 000003 cmp      eax, 42
IN0003: 000006 jge      SHORT G_M22359_IG04

G_M22359_IG03:        ; offs=000008H, size=0007H, bbWeight=0.18 PerfScore 0.41, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB02 [0002], byref, isz

IN0004: 000008 mov      eax, 42
IN0005: 00000D jmp      SHORT G_M22359_IG04

G_M22359_IG04:        ; offs=00000FH, size=0001H, bbWeight=1    PerfScore 1.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc

IN0006: 00000F ret      


*************** Finishing PHASE Emit code

*************** Starting PHASE Emit GC+EH tables
Unwind Info:
  >> Start offset   : 0x000000 (not in unwind data)
  >>   End offset   : 0x000010 (not in unwind data)
  Version           : 1
  Flags             : 0x00
  SizeOfProlog      : 0x00
  CountOfUnwindCodes: 0
  FrameRegister     : none (0)
  FrameOffset       : N/A (no FrameRegister) (Value=0)
  UnwindCodes       :
allocUnwindInfo(pHotCode=0x00007FFAD38810C0, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x10, unwindSize=0x4, pUnwindBlock=0x000002EB2F47FD5C, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 4
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x0000000F ( STACK_EMPTY )
IL offs EPILOG : 0x0000000F ( STACK_EMPTY )

*************** In genSetScopeInfo()
VarLocInfo count is 2
; Variable debug info: 1 live ranges, 1 vars for method Test.Program:Main(System.String[]):int
  0(   UNKNOWN) : From 00000000h to 00000001h, in rcx
VARIABLE LIVE RANGES:
V00 arg0: rcx [0, 0)
*************** In gcInfoBlockHdrSave()
Set code length to 16.
Set ReturnKind to Scalar.
Set Outgoing stack arg area size to 0.
Defining 0 call sites:

*************** Finishing PHASE Emit GC+EH tables
Method code size: 16

Allocations for Test.Program:Main(System.String[]):int (MethodHash=efe0a8a8)
count:        582, size:      53731, max =       3072
allocateMemory:      65536, nraUsed:      58904

Alloc'd bytes by kind:
                  kind |       size |     pct
  ---------------------+------------+--------
         AssertionProp |       6652 |  12.38%
               ASTNode |       4360 |   8.11%
              InstDesc |       2488 |   4.63%
              ImpStack |        384 |   0.71%
            BasicBlock |       2000 |   3.72%
             fgArgInfo |          0 |   0.00%
       fgArgInfoPtrArr |          0 |   0.00%
              FlowList |        200 |   0.37%
     TreeStatementList |          0 |   0.00%
               SiScope |          0 |   0.00%
       DominatorMemory |        240 |   0.45%
                  LSRA |       4908 |   9.13%
         LSRA_Interval |        320 |   0.60%
      LSRA_RefPosition |        960 |   1.79%
          Reachability |        136 |   0.25%
                   SSA |        608 |   1.13%
           ValueNumber |       6741 |  12.55%
              LvaTable |       2192 |   4.08%
            UnwindInfo |          0 |   0.00%
                hashBv |        160 |   0.30%
                bitset |         56 |   0.10%
          FixedBitVect |         32 |   0.06%
               Generic |       1328 |   2.47%
   LocalAddressVisitor |          0 |   0.00%
         FieldSeqStore |          0 |   0.00%
    ZeroOffsetFieldMap |         80 |   0.15%
          MemorySsaMap |         40 |   0.07%
          MemoryPhiArg |          0 |   0.00%
                   CSE |       1144 |   2.13%
                    GC |       1312 |   2.44%
       CorTailCallInfo |          0 |   0.00%
              Inlining |       1272 |   2.37%
            ArrayStack |          0 |   0.00%
             DebugInfo |        280 |   0.52%
             DebugOnly |      12677 |  23.59%
               Codegen |        848 |   1.58%
               LoopOpt |         48 |   0.09%
             LoopClone |          0 |   0.00%
             LoopHoist |          0 |   0.00%
               Unknown |        217 |   0.40%
            RangeCheck |          0 |   0.00%
              CopyProp |        952 |   1.77%
           SideEffects |          0 |   0.00%
       ObjectAllocator |          0 |   0.00%
    VariableLiveRanges |        328 |   0.61%
           ClassLayout |          0 |   0.00%
       TailMergeThrows |          0 |   0.00%
             EarlyProp |          0 |   0.00%
              ZeroInit |        192 |   0.36%
                   Pgo |        576 |   1.07%

****** DONE compiling Test.Program:Main(System.String[]):int