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[JIT][arm64] recognize Interlocked.Increment in volatile increment #60021
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Tagging subscribers to this area: @JulieLeeMSFT Issue Detailsvolatile int a;
void Test() => a++; Currently emits: ; Method Program:Test():this
G_M27469_IG01: ;; offset=0000H
A9BF7BFD stp fp, lr, [sp,#-16]!
910003FD mov fp, sp
;; bbWeight=1 PerfScore 1.50
G_M27469_IG02: ;; offset=0008H
B9400801 ldr w1, [x0,#8]
D50339BF dmb ishld
52800022 mov w2, #1
0B020021 add w1, w1, w2
D5033BBF dmb ish
B9000801 str w1, [x0,#8]
;; bbWeight=1 PerfScore 25.00
G_M27469_IG03: ;; offset=0020H
A8C17BFD ldp fp, lr, [sp],#16
D65F03C0 ret lr
;; bbWeight=1 PerfScore 2.00
; Total bytes of code: 40 I guess we can use armv8.1 LDADDAL (acquire and release) here? to get: ; Method Program:Test2():this
G_M27469_IG01: ;; offset=0000H
A9BF7BFD stp fp, lr, [sp,#-16]!
910003FD mov fp, sp
;; bbWeight=1 PerfScore 1.50
G_M27469_IG02: ;; offset=0008H
B940001F ldr wzr, [x0]
D2800101 mov x1, #8
8B010000 add x0, x0, x1
52800021 mov w1, #1
B8E10000 ldaddal w1, w0, [x0]
;; bbWeight=1 PerfScore 7.50
G_M27469_IG03: ;; offset=001CH
A8C17BFD ldp fp, lr, [sp],#16
D65F03C0 ret lr
;; bbWeight=1 PerfScore 2.00
; Total bytes of code: 36 Basically replace
with am I correct? @dotnet/jit-contrib
|
NOTE: we have >1000 of volatile fields across the base class libs, perhaps some of the access patterns also can be optimized with Atomics |
I am wondering whether in the baseline case (Armv8.0) it should be sufficient to have one memory barrier inserted after the load? ldr w1, [x0,#8]
dmb ishld
mov w2, #1
add w1, w1, w2
str w1, [x0,#8] Also interesting why we are not using |
Currently emits two
dmb
:I guess we can use armv8.1 LDADDAL (acquire and release) here? to get:
Basically replace
with
GT_XADD(GT_FIELD)
am I correct? @dotnet/jit-contrib
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