From 1d1317af7c5af5c8302f4116a1734b8fe205031b Mon Sep 17 00:00:00 2001 From: Khushal Modi Date: Mon, 18 Nov 2024 14:02:44 -0800 Subject: [PATCH 1/5] Add CPUID for AVX10.2 --- src/coreclr/inc/clrconfigvalues.h | 1 + src/coreclr/inc/corinfoinstructionset.h | 154 +++++++++----- src/coreclr/inc/jiteeversionguid.h | 10 +- src/coreclr/inc/readytoruninstructionset.h | 2 + src/coreclr/jit/hwintrinsic.cpp | 5 + src/coreclr/jit/jitconfigvalues.h | 1 + .../Compiler/HardwareIntrinsicHelpers.cs | 10 + .../Runtime/ReadyToRunInstructionSet.cs | 2 + .../Runtime/ReadyToRunInstructionSetHelper.cs | 10 + .../JitInterface/CorInfoInstructionSet.cs | 191 +++++++++++++----- .../ThunkGenerator/InstructionSetDesc.txt | 7 + src/coreclr/vm/codeman.cpp | 11 + src/native/minipal/cpufeatures.c | 8 +- src/native/minipal/cpufeatures.h | 4 + 14 files changed, 309 insertions(+), 107 deletions(-) diff --git a/src/coreclr/inc/clrconfigvalues.h b/src/coreclr/inc/clrconfigvalues.h index 7f74a4fefcc10..78a9400e8383a 100644 --- a/src/coreclr/inc/clrconfigvalues.h +++ b/src/coreclr/inc/clrconfigvalues.h @@ -771,6 +771,7 @@ RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX512F_VL, W("EnableAVX512F RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX512VBMI, W("EnableAVX512VBMI"), 1, "Allows AVX512VBMI+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX512VBMI_VL, W("EnableAVX512VBMI_VL"), 1, "Allows AVX512VBMI_VL+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX10v1, W("EnableAVX10v1"), 1, "Allows AVX10v1+ hardware intrinsics to be disabled") +RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX10v2, W("EnableAVX10v2"), 1, "Allows AVX10v2+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVXVNNI, W("EnableAVXVNNI"), 1, "Allows AVXVNNI+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableBMI1, W("EnableBMI1"), 1, "Allows BMI1+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableBMI2, W("EnableBMI2"), 1, "Allows BMI2+ hardware intrinsics to be disabled") diff --git a/src/coreclr/inc/corinfoinstructionset.h b/src/coreclr/inc/corinfoinstructionset.h index 90e9824f179b4..adc60cb44806e 100644 --- a/src/coreclr/inc/corinfoinstructionset.h +++ b/src/coreclr/inc/corinfoinstructionset.h @@ -84,31 +84,36 @@ enum CORINFO_InstructionSet InstructionSet_VectorT256=39, InstructionSet_VectorT512=40, InstructionSet_APX=41, - InstructionSet_X86Base_X64=42, - InstructionSet_SSE_X64=43, - InstructionSet_SSE2_X64=44, - InstructionSet_SSE3_X64=45, - InstructionSet_SSSE3_X64=46, - InstructionSet_SSE41_X64=47, - InstructionSet_SSE42_X64=48, - InstructionSet_AVX_X64=49, - InstructionSet_AVX2_X64=50, - InstructionSet_AES_X64=51, - InstructionSet_BMI1_X64=52, - InstructionSet_BMI2_X64=53, - InstructionSet_FMA_X64=54, - InstructionSet_LZCNT_X64=55, - InstructionSet_PCLMULQDQ_X64=56, - InstructionSet_POPCNT_X64=57, - InstructionSet_AVXVNNI_X64=58, - InstructionSet_X86Serialize_X64=59, - InstructionSet_AVX512F_X64=60, - InstructionSet_AVX512BW_X64=61, - InstructionSet_AVX512CD_X64=62, - InstructionSet_AVX512DQ_X64=63, - InstructionSet_AVX512VBMI_X64=64, - InstructionSet_AVX10v1_X64=65, - InstructionSet_AVX10v1_V512_X64=66, + InstructionSet_AVX10v2=42, + InstructionSet_AVX10v2_V512=43, + InstructionSet_X86Base_X64=44, + InstructionSet_SSE_X64=45, + InstructionSet_SSE2_X64=46, + InstructionSet_SSE3_X64=47, + InstructionSet_SSSE3_X64=48, + InstructionSet_SSE41_X64=49, + InstructionSet_SSE42_X64=50, + InstructionSet_AVX_X64=51, + InstructionSet_AVX2_X64=52, + InstructionSet_AES_X64=53, + InstructionSet_BMI1_X64=54, + InstructionSet_BMI2_X64=55, + InstructionSet_FMA_X64=56, + InstructionSet_LZCNT_X64=57, + InstructionSet_PCLMULQDQ_X64=58, + InstructionSet_POPCNT_X64=59, + InstructionSet_AVXVNNI_X64=60, + InstructionSet_X86Serialize_X64=61, + InstructionSet_AVX512F_X64=62, + InstructionSet_AVX512BW_X64=63, + InstructionSet_AVX512CD_X64=64, + InstructionSet_AVX512DQ_X64=65, + InstructionSet_AVX512VBMI_X64=66, + InstructionSet_AVX10v1_X64=67, + InstructionSet_AVX10v1_V512_X64=68, + InstructionSet_APX_X64=69, + InstructionSet_AVX10v2_X64=70, + InstructionSet_AVX10v2_V512_X64=71, #endif // TARGET_AMD64 #ifdef TARGET_X86 InstructionSet_X86Base=1, @@ -152,31 +157,36 @@ enum CORINFO_InstructionSet InstructionSet_VectorT256=39, InstructionSet_VectorT512=40, InstructionSet_APX=41, - InstructionSet_X86Base_X64=42, - InstructionSet_SSE_X64=43, - InstructionSet_SSE2_X64=44, - InstructionSet_SSE3_X64=45, - InstructionSet_SSSE3_X64=46, - InstructionSet_SSE41_X64=47, - InstructionSet_SSE42_X64=48, - InstructionSet_AVX_X64=49, - InstructionSet_AVX2_X64=50, - InstructionSet_AES_X64=51, - InstructionSet_BMI1_X64=52, - InstructionSet_BMI2_X64=53, - InstructionSet_FMA_X64=54, - InstructionSet_LZCNT_X64=55, - InstructionSet_PCLMULQDQ_X64=56, - InstructionSet_POPCNT_X64=57, - InstructionSet_AVXVNNI_X64=58, - InstructionSet_X86Serialize_X64=59, - InstructionSet_AVX512F_X64=60, - InstructionSet_AVX512BW_X64=61, - InstructionSet_AVX512CD_X64=62, - InstructionSet_AVX512DQ_X64=63, - InstructionSet_AVX512VBMI_X64=64, - InstructionSet_AVX10v1_X64=65, - InstructionSet_AVX10v1_V512_X64=66, + InstructionSet_AVX10v2=42, + InstructionSet_AVX10v2_V512=43, + InstructionSet_X86Base_X64=44, + InstructionSet_SSE_X64=45, + InstructionSet_SSE2_X64=46, + InstructionSet_SSE3_X64=47, + InstructionSet_SSSE3_X64=48, + InstructionSet_SSE41_X64=49, + InstructionSet_SSE42_X64=50, + InstructionSet_AVX_X64=51, + InstructionSet_AVX2_X64=52, + InstructionSet_AES_X64=53, + InstructionSet_BMI1_X64=54, + InstructionSet_BMI2_X64=55, + InstructionSet_FMA_X64=56, + InstructionSet_LZCNT_X64=57, + InstructionSet_PCLMULQDQ_X64=58, + InstructionSet_POPCNT_X64=59, + InstructionSet_AVXVNNI_X64=60, + InstructionSet_X86Serialize_X64=61, + InstructionSet_AVX512F_X64=62, + InstructionSet_AVX512BW_X64=63, + InstructionSet_AVX512CD_X64=64, + InstructionSet_AVX512DQ_X64=65, + InstructionSet_AVX512VBMI_X64=66, + InstructionSet_AVX10v1_X64=67, + InstructionSet_AVX10v1_V512_X64=68, + InstructionSet_APX_X64=69, + InstructionSet_AVX10v2_X64=70, + InstructionSet_AVX10v2_V512_X64=71, #endif // TARGET_X86 }; @@ -342,6 +352,12 @@ struct CORINFO_InstructionSetFlags AddInstructionSet(InstructionSet_AVX10v1_X64); if (HasInstructionSet(InstructionSet_AVX10v1_V512)) AddInstructionSet(InstructionSet_AVX10v1_V512_X64); + if (HasInstructionSet(InstructionSet_APX)) + AddInstructionSet(InstructionSet_APX_X64); + if (HasInstructionSet(InstructionSet_AVX10v2)) + AddInstructionSet(InstructionSet_AVX10v2_X64); + if (HasInstructionSet(InstructionSet_AVX10v2_V512)) + AddInstructionSet(InstructionSet_AVX10v2_V512_X64); #endif // TARGET_AMD64 #ifdef TARGET_X86 #endif // TARGET_X86 @@ -522,6 +538,18 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512); if (resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512_X64) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512)) resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512_X64); + if (resultflags.HasInstructionSet(InstructionSet_APX) && !resultflags.HasInstructionSet(InstructionSet_APX_X64)) + resultflags.RemoveInstructionSet(InstructionSet_APX); + if (resultflags.HasInstructionSet(InstructionSet_APX_X64) && !resultflags.HasInstructionSet(InstructionSet_APX)) + resultflags.RemoveInstructionSet(InstructionSet_APX_X64); + if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVX10v2_X64)) + resultflags.RemoveInstructionSet(InstructionSet_AVX10v2); + if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_X64) && !resultflags.HasInstructionSet(InstructionSet_AVX10v2)) + resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_X64); + if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512_X64)) + resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512); + if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512_X64) && !resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512)) + resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512_X64); if (resultflags.HasInstructionSet(InstructionSet_SSE) && !resultflags.HasInstructionSet(InstructionSet_X86Base)) resultflags.RemoveInstructionSet(InstructionSet_SSE); if (resultflags.HasInstructionSet(InstructionSet_SSE2) && !resultflags.HasInstructionSet(InstructionSet_SSE)) @@ -622,6 +650,10 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512); if (resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX512VBMI_VL)) resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512); + if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1)) + resultflags.RemoveInstructionSet(InstructionSet_AVX10v2); + if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512)) + resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512); if (resultflags.HasInstructionSet(InstructionSet_Vector128) && !resultflags.HasInstructionSet(InstructionSet_SSE)) resultflags.RemoveInstructionSet(InstructionSet_Vector128); if (resultflags.HasInstructionSet(InstructionSet_Vector256) && !resultflags.HasInstructionSet(InstructionSet_AVX)) @@ -736,6 +768,10 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512); if (resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX512VBMI_VL)) resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512); + if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1)) + resultflags.RemoveInstructionSet(InstructionSet_AVX10v2); + if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512)) + resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512); if (resultflags.HasInstructionSet(InstructionSet_Vector128) && !resultflags.HasInstructionSet(InstructionSet_SSE)) resultflags.RemoveInstructionSet(InstructionSet_Vector128); if (resultflags.HasInstructionSet(InstructionSet_Vector256) && !resultflags.HasInstructionSet(InstructionSet_AVX)) @@ -948,6 +984,16 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet) return "VectorT512"; case InstructionSet_APX : return "APX"; + case InstructionSet_APX_X64 : + return "APX_X64"; + case InstructionSet_AVX10v2 : + return "AVX10v2"; + case InstructionSet_AVX10v2_X64 : + return "AVX10v2_X64"; + case InstructionSet_AVX10v2_V512 : + return "AVX10v2_V512"; + case InstructionSet_AVX10v2_V512_X64 : + return "AVX10v2_V512_X64"; #endif // TARGET_AMD64 #ifdef TARGET_X86 case InstructionSet_X86Base : @@ -1032,6 +1078,10 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet) return "VectorT512"; case InstructionSet_APX : return "APX"; + case InstructionSet_AVX10v2 : + return "AVX10v2"; + case InstructionSet_AVX10v2_V512 : + return "AVX10v2_V512"; #endif // TARGET_X86 default: @@ -1105,6 +1155,8 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst case READYTORUN_INSTRUCTION_VectorT256: return InstructionSet_VectorT256; case READYTORUN_INSTRUCTION_VectorT512: return InstructionSet_VectorT512; case READYTORUN_INSTRUCTION_Apx: return InstructionSet_APX; + case READYTORUN_INSTRUCTION_Avx10v2: return InstructionSet_AVX10v2; + case READYTORUN_INSTRUCTION_Avx10v2_V512: return InstructionSet_AVX10v2_V512; #endif // TARGET_AMD64 #ifdef TARGET_X86 case READYTORUN_INSTRUCTION_X86Base: return InstructionSet_X86Base; @@ -1145,6 +1197,8 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst case READYTORUN_INSTRUCTION_VectorT256: return InstructionSet_VectorT256; case READYTORUN_INSTRUCTION_VectorT512: return InstructionSet_VectorT512; case READYTORUN_INSTRUCTION_Apx: return InstructionSet_APX; + case READYTORUN_INSTRUCTION_Avx10v2: return InstructionSet_AVX10v2; + case READYTORUN_INSTRUCTION_Avx10v2_V512: return InstructionSet_AVX10v2_V512; #endif // TARGET_X86 default: diff --git a/src/coreclr/inc/jiteeversionguid.h b/src/coreclr/inc/jiteeversionguid.h index 7f4ed543df2f5..eefd5dab1d81f 100644 --- a/src/coreclr/inc/jiteeversionguid.h +++ b/src/coreclr/inc/jiteeversionguid.h @@ -43,11 +43,11 @@ typedef const GUID *LPCGUID; #define GUID_DEFINED #endif // !GUID_DEFINED -constexpr GUID JITEEVersionIdentifier = { /* 9014d652-5dc7-4edf-9285-6644d0898fb5 */ - 0x9014d652, - 0x5dc7, - 0x4edf, - {0x92, 0x85, 0x66, 0x44, 0xd0, 0x89, 0x8f, 0xb5} +constexpr GUID JITEEVersionIdentifier = { /* 15b8f677-894e-4671-9dc8-fc4e2c50e269 */ + 0x15b8f677, + 0x894e, + 0x4671, + {0x9d, 0xc8, 0xfc, 0x4e, 0x2c, 0x50, 0xe2, 0x69} }; ////////////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/src/coreclr/inc/readytoruninstructionset.h b/src/coreclr/inc/readytoruninstructionset.h index 2da697a62394f..6b7256163b77c 100644 --- a/src/coreclr/inc/readytoruninstructionset.h +++ b/src/coreclr/inc/readytoruninstructionset.h @@ -58,6 +58,8 @@ enum ReadyToRunInstructionSet READYTORUN_INSTRUCTION_Apx=48, READYTORUN_INSTRUCTION_Pclmulqdq_V256=49, READYTORUN_INSTRUCTION_Pclmulqdq_V512=50, + READYTORUN_INSTRUCTION_Avx10v2=51, + READYTORUN_INSTRUCTION_Avx10v2_V512=52, }; diff --git a/src/coreclr/jit/hwintrinsic.cpp b/src/coreclr/jit/hwintrinsic.cpp index 84f5c01920fe6..03d459da2d441 100644 --- a/src/coreclr/jit/hwintrinsic.cpp +++ b/src/coreclr/jit/hwintrinsic.cpp @@ -807,6 +807,8 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = { { NI_Illegal, NI_Illegal }, // VectorT256 { NI_Illegal, NI_Illegal }, // VectorT512 { NI_Illegal, NI_Illegal }, // APX + { NI_Illegal, NI_Illegal }, // AVX10v2 + { NI_Illegal, NI_Illegal }, // AVX10v2_V512 { FIRST_NI_X86Base_X64, LAST_NI_X86Base_X64 }, { FIRST_NI_SSE_X64, LAST_NI_SSE_X64 }, { FIRST_NI_SSE2_X64, LAST_NI_SSE2_X64 }, @@ -832,6 +834,9 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = { { NI_Illegal, NI_Illegal }, // AVX512VBMI_X64 { FIRST_NI_AVX10v1_X64, LAST_NI_AVX10v1_X64 }, { NI_Illegal, NI_Illegal }, // AVX10v1_V512_X64 + { NI_Illegal, NI_Illegal }, // APX_X64 + { NI_Illegal, NI_Illegal }, // AVX10v2_X64 + { NI_Illegal, NI_Illegal }, // AVX10v2_V512_X64 #elif defined (TARGET_ARM64) { FIRST_NI_ArmBase, LAST_NI_ArmBase }, { FIRST_NI_AdvSimd, LAST_NI_AdvSimd }, diff --git a/src/coreclr/jit/jitconfigvalues.h b/src/coreclr/jit/jitconfigvalues.h index c964554667abf..36162934bdf1b 100644 --- a/src/coreclr/jit/jitconfigvalues.h +++ b/src/coreclr/jit/jitconfigvalues.h @@ -400,6 +400,7 @@ RELEASE_CONFIG_INTEGER(EnableAVX512F_VL, "EnableAVX512F_VL", RELEASE_CONFIG_INTEGER(EnableAVX512VBMI, "EnableAVX512VBMI", 1) // Allows AVX512VBMI+ hardware intrinsics to be disabled RELEASE_CONFIG_INTEGER(EnableAVX512VBMI_VL, "EnableAVX512VBMI_VL", 1) // Allows AVX512VBMI_VL+ hardware intrinsics to be disabled RELEASE_CONFIG_INTEGER(EnableAVX10v1, "EnableAVX10v1", 1) // Allows AVX10v1+ hardware intrinsics to be disabled +RELEASE_CONFIG_INTEGER(EnableAVX10v2, "EnableAVX10v2", 1) // Allows AVX10v2+ hardware intrinsics to be disabled RELEASE_CONFIG_INTEGER(EnableAVXVNNI, "EnableAVXVNNI", 1) // Allows AVXVNNI+ hardware intrinsics to be disabled RELEASE_CONFIG_INTEGER(EnableBMI1, "EnableBMI1", 1) // Allows BMI1+ hardware intrinsics to be disabled RELEASE_CONFIG_INTEGER(EnableBMI2, "EnableBMI2", 1) // Allows BMI2+ hardware intrinsics to be disabled diff --git a/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs b/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs index 3d0e4ba886bb4..254813c374160 100644 --- a/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs +++ b/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs @@ -80,6 +80,7 @@ private static class XArchIntrinsicConstants public const int Evex = 0x80000; public const int Apx = 0x100000; public const int Vpclmulqdq = 0x200000; + public const int Avx10v2 = 0x400000; public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags) { @@ -145,6 +146,10 @@ public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags) if ((flags & Avx512) != 0) builder.AddSupportedInstructionSet("vpclmul_v512"); } + if ((flags & Avx10v2) != 0) + builder.AddSupportedInstructionSet("avx10v2"); + if (((flags & Avx10v2) != 0) && ((flags & Avx512) != 0)) + builder.AddSupportedInstructionSet("avx10v2_v512"); } public static int FromInstructionSet(InstructionSet instructionSet) @@ -210,6 +215,11 @@ public static int FromInstructionSet(InstructionSet instructionSet) InstructionSet.X64_APX => Apx, InstructionSet.X64_PCLMULQDQ_V256 => Vpclmulqdq, InstructionSet.X64_PCLMULQDQ_V512 => (Vpclmulqdq | Avx512), + InstructionSet.X64_APX_X64 => Apx, + InstructionSet.X64_AVX10v2 => Avx10v2, + InstructionSet.X64_AVX10v2_X64 => Avx10v2, + InstructionSet.X64_AVX10v2_V512 => (Avx10v2 | Avx512), + InstructionSet.X64_AVX10v2_V512_X64 => (Avx10v2 | Avx512), // Baseline ISAs - they're always available InstructionSet.X64_SSE => 0, diff --git a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs index eab9b4584433e..afcfd808bffac 100644 --- a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs +++ b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs @@ -61,6 +61,8 @@ public enum ReadyToRunInstructionSet Apx=48, Pclmulqdq_V256=49, Pclmulqdq_V512=50, + Avx10v2=51, + Avx10v2_V512=52, } } diff --git a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs index 9e97bc9dc991a..6b16c470cd048 100644 --- a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs +++ b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs @@ -123,6 +123,11 @@ public static class ReadyToRunInstructionSetHelper case InstructionSet.X64_VectorT256: return ReadyToRunInstructionSet.VectorT256; case InstructionSet.X64_VectorT512: return ReadyToRunInstructionSet.VectorT512; case InstructionSet.X64_APX: return ReadyToRunInstructionSet.Apx; + case InstructionSet.X64_APX_X64: return ReadyToRunInstructionSet.Apx; + case InstructionSet.X64_AVX10v2: return ReadyToRunInstructionSet.Avx10v2; + case InstructionSet.X64_AVX10v2_X64: return ReadyToRunInstructionSet.Avx10v2; + case InstructionSet.X64_AVX10v2_V512: return ReadyToRunInstructionSet.Avx10v2_V512; + case InstructionSet.X64_AVX10v2_V512_X64: return ReadyToRunInstructionSet.Avx10v2_V512; default: throw new Exception("Unknown instruction set"); } @@ -198,6 +203,11 @@ public static class ReadyToRunInstructionSetHelper case InstructionSet.X86_VectorT256: return ReadyToRunInstructionSet.VectorT256; case InstructionSet.X86_VectorT512: return ReadyToRunInstructionSet.VectorT512; case InstructionSet.X86_APX: return ReadyToRunInstructionSet.Apx; + case InstructionSet.X86_APX_X64: return null; + case InstructionSet.X86_AVX10v2: return ReadyToRunInstructionSet.Avx10v2; + case InstructionSet.X86_AVX10v2_X64: return null; + case InstructionSet.X86_AVX10v2_V512: return ReadyToRunInstructionSet.Avx10v2_V512; + case InstructionSet.X86_AVX10v2_V512_X64: return null; default: throw new Exception("Unknown instruction set"); } diff --git a/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs b/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs index 7c3d68eedad6b..0174c65d1a70c 100644 --- a/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs +++ b/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs @@ -82,6 +82,8 @@ public enum InstructionSet X64_VectorT256 = InstructionSet_X64.VectorT256, X64_VectorT512 = InstructionSet_X64.VectorT512, X64_APX = InstructionSet_X64.APX, + X64_AVX10v2 = InstructionSet_X64.AVX10v2, + X64_AVX10v2_V512 = InstructionSet_X64.AVX10v2_V512, X64_X86Base_X64 = InstructionSet_X64.X86Base_X64, X64_SSE_X64 = InstructionSet_X64.SSE_X64, X64_SSE2_X64 = InstructionSet_X64.SSE2_X64, @@ -107,6 +109,9 @@ public enum InstructionSet X64_AVX512VBMI_X64 = InstructionSet_X64.AVX512VBMI_X64, X64_AVX10v1_X64 = InstructionSet_X64.AVX10v1_X64, X64_AVX10v1_V512_X64 = InstructionSet_X64.AVX10v1_V512_X64, + X64_APX_X64 = InstructionSet_X64.APX_X64, + X64_AVX10v2_X64 = InstructionSet_X64.AVX10v2_X64, + X64_AVX10v2_V512_X64 = InstructionSet_X64.AVX10v2_V512_X64, X86_X86Base = InstructionSet_X86.X86Base, X86_SSE = InstructionSet_X86.SSE, X86_SSE2 = InstructionSet_X86.SSE2, @@ -148,6 +153,8 @@ public enum InstructionSet X86_VectorT256 = InstructionSet_X86.VectorT256, X86_VectorT512 = InstructionSet_X86.VectorT512, X86_APX = InstructionSet_X86.APX, + X86_AVX10v2 = InstructionSet_X86.AVX10v2, + X86_AVX10v2_V512 = InstructionSet_X86.AVX10v2_V512, X86_X86Base_X64 = InstructionSet_X86.X86Base_X64, X86_SSE_X64 = InstructionSet_X86.SSE_X64, X86_SSE2_X64 = InstructionSet_X86.SSE2_X64, @@ -173,6 +180,9 @@ public enum InstructionSet X86_AVX512VBMI_X64 = InstructionSet_X86.AVX512VBMI_X64, X86_AVX10v1_X64 = InstructionSet_X86.AVX10v1_X64, X86_AVX10v1_V512_X64 = InstructionSet_X86.AVX10v1_V512_X64, + X86_APX_X64 = InstructionSet_X86.APX_X64, + X86_AVX10v2_X64 = InstructionSet_X86.AVX10v2_X64, + X86_AVX10v2_V512_X64 = InstructionSet_X86.AVX10v2_V512_X64, } public enum InstructionSet_ARM64 { @@ -250,31 +260,36 @@ public enum InstructionSet_X64 VectorT256 = 39, VectorT512 = 40, APX = 41, - X86Base_X64 = 42, - SSE_X64 = 43, - SSE2_X64 = 44, - SSE3_X64 = 45, - SSSE3_X64 = 46, - SSE41_X64 = 47, - SSE42_X64 = 48, - AVX_X64 = 49, - AVX2_X64 = 50, - AES_X64 = 51, - BMI1_X64 = 52, - BMI2_X64 = 53, - FMA_X64 = 54, - LZCNT_X64 = 55, - PCLMULQDQ_X64 = 56, - POPCNT_X64 = 57, - AVXVNNI_X64 = 58, - X86Serialize_X64 = 59, - AVX512F_X64 = 60, - AVX512BW_X64 = 61, - AVX512CD_X64 = 62, - AVX512DQ_X64 = 63, - AVX512VBMI_X64 = 64, - AVX10v1_X64 = 65, - AVX10v1_V512_X64 = 66, + AVX10v2 = 42, + AVX10v2_V512 = 43, + X86Base_X64 = 44, + SSE_X64 = 45, + SSE2_X64 = 46, + SSE3_X64 = 47, + SSSE3_X64 = 48, + SSE41_X64 = 49, + SSE42_X64 = 50, + AVX_X64 = 51, + AVX2_X64 = 52, + AES_X64 = 53, + BMI1_X64 = 54, + BMI2_X64 = 55, + FMA_X64 = 56, + LZCNT_X64 = 57, + PCLMULQDQ_X64 = 58, + POPCNT_X64 = 59, + AVXVNNI_X64 = 60, + X86Serialize_X64 = 61, + AVX512F_X64 = 62, + AVX512BW_X64 = 63, + AVX512CD_X64 = 64, + AVX512DQ_X64 = 65, + AVX512VBMI_X64 = 66, + AVX10v1_X64 = 67, + AVX10v1_V512_X64 = 68, + APX_X64 = 69, + AVX10v2_X64 = 70, + AVX10v2_V512_X64 = 71, } public enum InstructionSet_X86 @@ -322,31 +337,36 @@ public enum InstructionSet_X86 VectorT256 = 39, VectorT512 = 40, APX = 41, - X86Base_X64 = 42, - SSE_X64 = 43, - SSE2_X64 = 44, - SSE3_X64 = 45, - SSSE3_X64 = 46, - SSE41_X64 = 47, - SSE42_X64 = 48, - AVX_X64 = 49, - AVX2_X64 = 50, - AES_X64 = 51, - BMI1_X64 = 52, - BMI2_X64 = 53, - FMA_X64 = 54, - LZCNT_X64 = 55, - PCLMULQDQ_X64 = 56, - POPCNT_X64 = 57, - AVXVNNI_X64 = 58, - X86Serialize_X64 = 59, - AVX512F_X64 = 60, - AVX512BW_X64 = 61, - AVX512CD_X64 = 62, - AVX512DQ_X64 = 63, - AVX512VBMI_X64 = 64, - AVX10v1_X64 = 65, - AVX10v1_V512_X64 = 66, + AVX10v2 = 42, + AVX10v2_V512 = 43, + X86Base_X64 = 44, + SSE_X64 = 45, + SSE2_X64 = 46, + SSE3_X64 = 47, + SSSE3_X64 = 48, + SSE41_X64 = 49, + SSE42_X64 = 50, + AVX_X64 = 51, + AVX2_X64 = 52, + AES_X64 = 53, + BMI1_X64 = 54, + BMI2_X64 = 55, + FMA_X64 = 56, + LZCNT_X64 = 57, + PCLMULQDQ_X64 = 58, + POPCNT_X64 = 59, + AVXVNNI_X64 = 60, + X86Serialize_X64 = 61, + AVX512F_X64 = 62, + AVX512BW_X64 = 63, + AVX512CD_X64 = 64, + AVX512DQ_X64 = 65, + AVX512VBMI_X64 = 66, + AVX10v1_X64 = 67, + AVX10v1_V512_X64 = 68, + APX_X64 = 69, + AVX10v2_X64 = 70, + AVX10v2_V512_X64 = 71, } public unsafe struct InstructionSetFlags : IEnumerable @@ -666,6 +686,18 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target resultflags.AddInstructionSet(InstructionSet.X64_AVX10v1_V512_X64); if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v1_V512_X64)) resultflags.AddInstructionSet(InstructionSet.X64_AVX10v1_V512); + if (resultflags.HasInstructionSet(InstructionSet.X64_APX)) + resultflags.AddInstructionSet(InstructionSet.X64_APX_X64); + if (resultflags.HasInstructionSet(InstructionSet.X64_APX_X64)) + resultflags.AddInstructionSet(InstructionSet.X64_APX); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v2)) + resultflags.AddInstructionSet(InstructionSet.X64_AVX10v2_X64); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v2_X64)) + resultflags.AddInstructionSet(InstructionSet.X64_AVX10v2); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v2_V512)) + resultflags.AddInstructionSet(InstructionSet.X64_AVX10v2_V512_X64); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v2_V512_X64)) + resultflags.AddInstructionSet(InstructionSet.X64_AVX10v2_V512); if (resultflags.HasInstructionSet(InstructionSet.X64_SSE)) resultflags.AddInstructionSet(InstructionSet.X64_X86Base); if (resultflags.HasInstructionSet(InstructionSet.X64_SSE2)) @@ -766,6 +798,10 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target resultflags.AddInstructionSet(InstructionSet.X64_AVX512VBMI); if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v1_V512)) resultflags.AddInstructionSet(InstructionSet.X64_AVX512VBMI_VL); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v2)) + resultflags.AddInstructionSet(InstructionSet.X64_AVX10v1); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v2_V512)) + resultflags.AddInstructionSet(InstructionSet.X64_AVX10v1_V512); if (resultflags.HasInstructionSet(InstructionSet.X64_Vector128)) resultflags.AddInstructionSet(InstructionSet.X64_SSE); if (resultflags.HasInstructionSet(InstructionSet.X64_Vector256)) @@ -881,6 +917,10 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target resultflags.AddInstructionSet(InstructionSet.X86_AVX512VBMI); if (resultflags.HasInstructionSet(InstructionSet.X86_AVX10v1_V512)) resultflags.AddInstructionSet(InstructionSet.X86_AVX512VBMI_VL); + if (resultflags.HasInstructionSet(InstructionSet.X86_AVX10v2)) + resultflags.AddInstructionSet(InstructionSet.X86_AVX10v1); + if (resultflags.HasInstructionSet(InstructionSet.X86_AVX10v2_V512)) + resultflags.AddInstructionSet(InstructionSet.X86_AVX10v1_V512); if (resultflags.HasInstructionSet(InstructionSet.X86_Vector128)) resultflags.AddInstructionSet(InstructionSet.X86_SSE); if (resultflags.HasInstructionSet(InstructionSet.X86_Vector256)) @@ -1009,6 +1049,12 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe resultflags.AddInstructionSet(InstructionSet.X64_AVX10v1); if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v1_V512_X64)) resultflags.AddInstructionSet(InstructionSet.X64_AVX10v1_V512); + if (resultflags.HasInstructionSet(InstructionSet.X64_APX_X64)) + resultflags.AddInstructionSet(InstructionSet.X64_APX); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v2_X64)) + resultflags.AddInstructionSet(InstructionSet.X64_AVX10v2); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v2_V512_X64)) + resultflags.AddInstructionSet(InstructionSet.X64_AVX10v2_V512); if (resultflags.HasInstructionSet(InstructionSet.X64_X86Base)) resultflags.AddInstructionSet(InstructionSet.X64_SSE); if (resultflags.HasInstructionSet(InstructionSet.X64_SSE)) @@ -1109,6 +1155,10 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe resultflags.AddInstructionSet(InstructionSet.X64_AVX10v1_V512); if (resultflags.HasInstructionSet(InstructionSet.X64_AVX512VBMI_VL)) resultflags.AddInstructionSet(InstructionSet.X64_AVX10v1_V512); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v1)) + resultflags.AddInstructionSet(InstructionSet.X64_AVX10v2); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v1_V512)) + resultflags.AddInstructionSet(InstructionSet.X64_AVX10v2_V512); if (resultflags.HasInstructionSet(InstructionSet.X64_SSE)) resultflags.AddInstructionSet(InstructionSet.X64_Vector128); if (resultflags.HasInstructionSet(InstructionSet.X64_AVX)) @@ -1224,6 +1274,10 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe resultflags.AddInstructionSet(InstructionSet.X86_AVX10v1_V512); if (resultflags.HasInstructionSet(InstructionSet.X86_AVX512VBMI_VL)) resultflags.AddInstructionSet(InstructionSet.X86_AVX10v1_V512); + if (resultflags.HasInstructionSet(InstructionSet.X86_AVX10v1)) + resultflags.AddInstructionSet(InstructionSet.X86_AVX10v2); + if (resultflags.HasInstructionSet(InstructionSet.X86_AVX10v1_V512)) + resultflags.AddInstructionSet(InstructionSet.X86_AVX10v2_V512); if (resultflags.HasInstructionSet(InstructionSet.X86_SSE)) resultflags.AddInstructionSet(InstructionSet.X86_Vector128); if (resultflags.HasInstructionSet(InstructionSet.X86_AVX)) @@ -1353,6 +1407,8 @@ public static IEnumerable ArchitectureToValidInstructionSets yield return new InstructionSetInfo("vectort256", "VectorT256", InstructionSet.X64_VectorT256, true); yield return new InstructionSetInfo("vectort512", "VectorT512", InstructionSet.X64_VectorT512, true); yield return new InstructionSetInfo("apx", "Apx", InstructionSet.X64_APX, true); + yield return new InstructionSetInfo("avx10v2", "Avx10v2", InstructionSet.X64_AVX10v2, true); + yield return new InstructionSetInfo("avx10v2_v512", "Avx10v2_V512", InstructionSet.X64_AVX10v2_V512, true); break; case TargetArchitecture.X86: @@ -1397,6 +1453,8 @@ public static IEnumerable ArchitectureToValidInstructionSets yield return new InstructionSetInfo("vectort256", "VectorT256", InstructionSet.X86_VectorT256, true); yield return new InstructionSetInfo("vectort512", "VectorT512", InstructionSet.X86_VectorT512, true); yield return new InstructionSetInfo("apx", "Apx", InstructionSet.X86_APX, true); + yield return new InstructionSetInfo("avx10v2", "Avx10v2", InstructionSet.X86_AVX10v2, true); + yield return new InstructionSetInfo("avx10v2_v512", "Avx10v2_V512", InstructionSet.X86_AVX10v2_V512, true); break; } } @@ -1478,6 +1536,12 @@ public void Set64BitInstructionSetVariants(TargetArchitecture architecture) AddInstructionSet(InstructionSet.X64_AVX10v1_X64); if (HasInstructionSet(InstructionSet.X64_AVX10v1_V512)) AddInstructionSet(InstructionSet.X64_AVX10v1_V512_X64); + if (HasInstructionSet(InstructionSet.X64_APX)) + AddInstructionSet(InstructionSet.X64_APX_X64); + if (HasInstructionSet(InstructionSet.X64_AVX10v2)) + AddInstructionSet(InstructionSet.X64_AVX10v2_X64); + if (HasInstructionSet(InstructionSet.X64_AVX10v2_V512)) + AddInstructionSet(InstructionSet.X64_AVX10v2_V512_X64); break; case TargetArchitecture.X86: @@ -1528,6 +1592,9 @@ public void Set64BitInstructionSetVariantsUnconditionally(TargetArchitecture arc AddInstructionSet(InstructionSet.X64_AVX512VBMI_X64); AddInstructionSet(InstructionSet.X64_AVX10v1_X64); AddInstructionSet(InstructionSet.X64_AVX10v1_V512_X64); + AddInstructionSet(InstructionSet.X64_APX_X64); + AddInstructionSet(InstructionSet.X64_AVX10v2_X64); + AddInstructionSet(InstructionSet.X64_AVX10v2_V512_X64); break; case TargetArchitecture.X86: @@ -1556,6 +1623,9 @@ public void Set64BitInstructionSetVariantsUnconditionally(TargetArchitecture arc AddInstructionSet(InstructionSet.X86_AVX512VBMI_X64); AddInstructionSet(InstructionSet.X86_AVX10v1_X64); AddInstructionSet(InstructionSet.X86_AVX10v1_V512_X64); + AddInstructionSet(InstructionSet.X86_APX_X64); + AddInstructionSet(InstructionSet.X86_AVX10v2_X64); + AddInstructionSet(InstructionSet.X86_AVX10v2_V512_X64); break; } } @@ -1858,8 +1928,23 @@ public static InstructionSet LookupPlatformIntrinsicInstructionSet(TargetArchite { return InstructionSet.X64_VectorT512; } case "Apx": + if (nestedTypeName == "X64") + { return InstructionSet.X64_APX_X64; } + else { return InstructionSet.X64_APX; } + case "Avx10v2": + if (nestedTypeName == "X64") + { return InstructionSet.X64_AVX10v2_X64; } + else + if (nestedTypeName == "V512_X64") + { return InstructionSet.X64_AVX10v2_V512_X64; } + else + if (nestedTypeName == "V512") + { return InstructionSet.X64_AVX10v2_V512; } + else + { return InstructionSet.X64_AVX10v2; } + } break; @@ -1981,6 +2066,12 @@ public static InstructionSet LookupPlatformIntrinsicInstructionSet(TargetArchite case "Apx": { return InstructionSet.X86_APX; } + case "Avx10v2": + if (nestedTypeName == "V512") + { return InstructionSet.X86_AVX10v2_V512; } + else + { return InstructionSet.X86_AVX10v2; } + } break; diff --git a/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt b/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt index 550ee6b2bd12d..6278e18f46d03 100644 --- a/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt +++ b/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt @@ -68,6 +68,8 @@ instructionset ,X86 ,VectorT128 , ,39 ,VectorT128 instructionset ,X86 ,VectorT256 , ,40 ,VectorT256 ,vectort256 instructionset ,X86 ,VectorT512 , ,41 ,VectorT512 ,vectort512 instructionset ,X86 ,Apx , ,48 ,APX ,apx +instructionset ,X86 ,Avx10v2 , ,51 ,AVX10v2 ,avx10v2 +instructionset ,X86 ,Avx10v2_V512 , ,52 ,AVX10v2_V512 ,avx10v2_v512 instructionset64bit,X86 ,X86Base instructionset64bit,X86 ,SSE @@ -94,6 +96,9 @@ instructionset64bit,X86 ,AVX512DQ instructionset64bit,X86 ,AVX512VBMI instructionset64bit,X86 ,AVX10v1 instructionset64bit,X86 ,AVX10v1_V512 +instructionset64bit,X86 ,APX +instructionset64bit,X86 ,AVX10v2 +instructionset64bit,X86 ,AVX10v2_V512 vectorinstructionset,X86 ,Vector128 vectorinstructionset,X86 ,Vector256 @@ -164,6 +169,8 @@ implication ,X86 ,AVX10v1_V512 ,AVX512DQ implication ,X86 ,AVX10v1_V512 ,AVX512DQ_VL implication ,X86 ,AVX10v1_V512 ,AVX512VBMI implication ,X86 ,AVX10v1_V512 ,AVX512VBMI_VL +implication ,X86 ,AVX10v2 ,AVX10v1 +implication ,X86 ,AVX10v2_V512 ,AVX10v1_V512 ; These synthetic ISAs need to appear after the core ISAs ; as they depend on the other implications being correct first diff --git a/src/coreclr/vm/codeman.cpp b/src/coreclr/vm/codeman.cpp index a09481acdf6c4..65511caee0cb7 100644 --- a/src/coreclr/vm/codeman.cpp +++ b/src/coreclr/vm/codeman.cpp @@ -1420,6 +1420,17 @@ void EEJitManager::SetCpuInfo() { CPUCompileFlags.Set(InstructionSet_AVX10v1_V512); } + if ((cpuFeatures & XArchIntrinsicConstants_Avx10v2) != 0) + { + if (CLRConfig::GetConfigValue(CLRConfig::EXTERNAL_EnableAVX10v2)) + { + CPUCompileFlags.Set(InstructionSet_AVX10v2); + if((cpuFeatures & XArchIntrinsicConstants_Avx512) != 0) + { + CPUCompileFlags.Set(InstructionSet_AVX10v2_V512); + } + } + } } } #if defined(TARGET_AMD64) diff --git a/src/native/minipal/cpufeatures.c b/src/native/minipal/cpufeatures.c index 3cd30aee7779d..e82cf1b59228b 100644 --- a/src/native/minipal/cpufeatures.c +++ b/src/native/minipal/cpufeatures.c @@ -326,11 +326,15 @@ int minipal_getcpufeatures(void) uint8_t avx10Version = (uint8_t)(cpuidInfo[CPUID_EBX] & 0xFF); if((avx10Version >= 1) && - ((cpuidInfo[CPUID_EBX] & (1 << 16)) != 0) && // Avx10/V128 ((cpuidInfo[CPUID_EBX] & (1 << 17)) != 0)) // Avx10/V256 { result |= XArchIntrinsicConstants_Evex; - result |= XArchIntrinsicConstants_Avx10v1; + result |= XArchIntrinsicConstants_Avx10v1; // Avx10.1 + + if (avx10Version >= 2) // Avx10.2 + { + result |= XArchIntrinsicConstants_Avx10v2; + } // We assume that the Avx10/V512 support can be inferred from // both Avx10v1 and Avx512 being present. diff --git a/src/native/minipal/cpufeatures.h b/src/native/minipal/cpufeatures.h index 101e7ab0a1b61..77e4779a86fe0 100644 --- a/src/native/minipal/cpufeatures.h +++ b/src/native/minipal/cpufeatures.h @@ -32,7 +32,11 @@ enum XArchIntrinsicConstants XArchIntrinsicConstants_Avx10v1 = 0x40000, XArchIntrinsicConstants_Evex = 0x80000, XArchIntrinsicConstants_Apx = 0x100000, +<<<<<<< HEAD XArchIntrinsicConstants_Vpclmulqdq = 0x200000, +======= + XArchIntrinsicConstants_Avx10v2 = 0x200000, +>>>>>>> 40f24a90a65 (Add CPUID for AVX10.2) }; #endif // HOST_X86 || HOST_AMD64 From 020816291d77d873e2a7471feabc3afcb154c811 Mon Sep 17 00:00:00 2001 From: Khushal Modi Date: Tue, 19 Nov 2024 11:54:12 -0800 Subject: [PATCH 2/5] Handle AVX10.2 ISAs in missing places --- .../Common/Compiler/InstructionSetSupport.cs | 4 ++++ .../tools/Common/InstructionSetHelpers.cs | 2 ++ .../Compiler/HardwareIntrinsicHelpers.Aot.cs | 4 +++- src/coreclr/vm/codeman.cpp | 20 ++++++++++--------- 4 files changed, 20 insertions(+), 10 deletions(-) diff --git a/src/coreclr/tools/Common/Compiler/InstructionSetSupport.cs b/src/coreclr/tools/Common/Compiler/InstructionSetSupport.cs index 6afe17d2c1cdc..a1997d4cdf841 100644 --- a/src/coreclr/tools/Common/Compiler/InstructionSetSupport.cs +++ b/src/coreclr/tools/Common/Compiler/InstructionSetSupport.cs @@ -360,6 +360,10 @@ public bool ComputeInstructionSetFlags(int maxVectorTBitWidth, if (_supportedInstructionSets.Contains("vpclmul")) _supportedInstructionSets.Add("vpclmul_v512"); + + // Having AVX10V1-V512 enabled, means having AVX10V2-V512 enabled as well. + if (_supportedInstructionSets.Contains("avx10v1_v512")) + _supportedInstructionSets.Add("avx10v2_v512"); } foreach (string supported in _supportedInstructionSets) diff --git a/src/coreclr/tools/Common/InstructionSetHelpers.cs b/src/coreclr/tools/Common/InstructionSetHelpers.cs index 95811afd7fbcd..d412ee5598881 100644 --- a/src/coreclr/tools/Common/InstructionSetHelpers.cs +++ b/src/coreclr/tools/Common/InstructionSetHelpers.cs @@ -228,6 +228,8 @@ public static InstructionSetSupport ConfigureInstructionSetSupport(string instru optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("avx10v1"); optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("avx10v1_v512"); optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("vpclmul_v512"); + optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("avx10v2"); + optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("avx10v2_v512"); } } else if (targetArchitecture == TargetArchitecture.ARM64) diff --git a/src/coreclr/tools/aot/ILCompiler.Compiler/Compiler/HardwareIntrinsicHelpers.Aot.cs b/src/coreclr/tools/aot/ILCompiler.Compiler/Compiler/HardwareIntrinsicHelpers.Aot.cs index f235483b67f8f..bd4e0a8316557 100644 --- a/src/coreclr/tools/aot/ILCompiler.Compiler/Compiler/HardwareIntrinsicHelpers.Aot.cs +++ b/src/coreclr/tools/aot/ILCompiler.Compiler/Compiler/HardwareIntrinsicHelpers.Aot.cs @@ -52,7 +52,9 @@ public static MethodIL EmitIsSupportedIL(MethodDesc method, FieldDesc isSupporte if (!uint.IsPow2((uint)flag)) { // These are the ISAs managed by multiple-bit flags. - // We need to emit different IL to handle the checks. + // we need to emit different IL to handle the checks. + // For now just Avx10v1_V512 = (Avx10v1 | Avx512) && + // Avx10v2_V512 = (Avx10v2 | Avx512) // (isSupportedField & flag) == flag codeStream.Emit(ILOpcode.ldsfld, emit.NewToken(isSupportedField)); codeStream.EmitLdc(flag); diff --git a/src/coreclr/vm/codeman.cpp b/src/coreclr/vm/codeman.cpp index 65511caee0cb7..2dab2b5edaf3a 100644 --- a/src/coreclr/vm/codeman.cpp +++ b/src/coreclr/vm/codeman.cpp @@ -1420,19 +1420,21 @@ void EEJitManager::SetCpuInfo() { CPUCompileFlags.Set(InstructionSet_AVX10v1_V512); } - if ((cpuFeatures & XArchIntrinsicConstants_Avx10v2) != 0) + } + } + + if ((cpuFeatures & XArchIntrinsicConstants_Avx10v2) != 0) + { + if (CLRConfig::GetConfigValue(CLRConfig::EXTERNAL_EnableAVX10v2)) + { + CPUCompileFlags.Set(InstructionSet_AVX10v2); + if((cpuFeatures & XArchIntrinsicConstants_Avx512) != 0) { - if (CLRConfig::GetConfigValue(CLRConfig::EXTERNAL_EnableAVX10v2)) - { - CPUCompileFlags.Set(InstructionSet_AVX10v2); - if((cpuFeatures & XArchIntrinsicConstants_Avx512) != 0) - { - CPUCompileFlags.Set(InstructionSet_AVX10v2_V512); - } - } + CPUCompileFlags.Set(InstructionSet_AVX10v2_V512); } } } + #if defined(TARGET_AMD64) if ((cpuFeatures & XArchIntrinsicConstants_Apx) != 0) { From 7f112842c4f69d66b399582aa10c057e62ff2cde Mon Sep 17 00:00:00 2001 From: Khushal Modi Date: Tue, 19 Nov 2024 13:07:09 -0800 Subject: [PATCH 3/5] Remove APX_X64 since it is unused --- src/coreclr/inc/corinfoinstructionset.h | 18 +++---------- src/coreclr/inc/jiteeversionguid.h | 10 +++---- src/coreclr/jit/hwintrinsic.cpp | 1 - src/coreclr/scripts/out.txt | Bin 0 -> 68524 bytes .../Compiler/HardwareIntrinsicHelpers.cs | 1 - .../Runtime/ReadyToRunInstructionSetHelper.cs | 2 -- .../JitInterface/CorInfoInstructionSet.cs | 25 +++--------------- .../ThunkGenerator/InstructionSetDesc.txt | 1 - 8 files changed, 13 insertions(+), 45 deletions(-) create mode 100644 src/coreclr/scripts/out.txt diff --git a/src/coreclr/inc/corinfoinstructionset.h b/src/coreclr/inc/corinfoinstructionset.h index adc60cb44806e..a4b6846c3d420 100644 --- a/src/coreclr/inc/corinfoinstructionset.h +++ b/src/coreclr/inc/corinfoinstructionset.h @@ -111,9 +111,8 @@ enum CORINFO_InstructionSet InstructionSet_AVX512VBMI_X64=66, InstructionSet_AVX10v1_X64=67, InstructionSet_AVX10v1_V512_X64=68, - InstructionSet_APX_X64=69, - InstructionSet_AVX10v2_X64=70, - InstructionSet_AVX10v2_V512_X64=71, + InstructionSet_AVX10v2_X64=69, + InstructionSet_AVX10v2_V512_X64=70, #endif // TARGET_AMD64 #ifdef TARGET_X86 InstructionSet_X86Base=1, @@ -184,9 +183,8 @@ enum CORINFO_InstructionSet InstructionSet_AVX512VBMI_X64=66, InstructionSet_AVX10v1_X64=67, InstructionSet_AVX10v1_V512_X64=68, - InstructionSet_APX_X64=69, - InstructionSet_AVX10v2_X64=70, - InstructionSet_AVX10v2_V512_X64=71, + InstructionSet_AVX10v2_X64=69, + InstructionSet_AVX10v2_V512_X64=70, #endif // TARGET_X86 }; @@ -352,8 +350,6 @@ struct CORINFO_InstructionSetFlags AddInstructionSet(InstructionSet_AVX10v1_X64); if (HasInstructionSet(InstructionSet_AVX10v1_V512)) AddInstructionSet(InstructionSet_AVX10v1_V512_X64); - if (HasInstructionSet(InstructionSet_APX)) - AddInstructionSet(InstructionSet_APX_X64); if (HasInstructionSet(InstructionSet_AVX10v2)) AddInstructionSet(InstructionSet_AVX10v2_X64); if (HasInstructionSet(InstructionSet_AVX10v2_V512)) @@ -538,10 +534,6 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512); if (resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512_X64) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512)) resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512_X64); - if (resultflags.HasInstructionSet(InstructionSet_APX) && !resultflags.HasInstructionSet(InstructionSet_APX_X64)) - resultflags.RemoveInstructionSet(InstructionSet_APX); - if (resultflags.HasInstructionSet(InstructionSet_APX_X64) && !resultflags.HasInstructionSet(InstructionSet_APX)) - resultflags.RemoveInstructionSet(InstructionSet_APX_X64); if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVX10v2_X64)) resultflags.RemoveInstructionSet(InstructionSet_AVX10v2); if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_X64) && !resultflags.HasInstructionSet(InstructionSet_AVX10v2)) @@ -984,8 +976,6 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet) return "VectorT512"; case InstructionSet_APX : return "APX"; - case InstructionSet_APX_X64 : - return "APX_X64"; case InstructionSet_AVX10v2 : return "AVX10v2"; case InstructionSet_AVX10v2_X64 : diff --git a/src/coreclr/inc/jiteeversionguid.h b/src/coreclr/inc/jiteeversionguid.h index eefd5dab1d81f..2f0b67174805a 100644 --- a/src/coreclr/inc/jiteeversionguid.h +++ b/src/coreclr/inc/jiteeversionguid.h @@ -43,11 +43,11 @@ typedef const GUID *LPCGUID; #define GUID_DEFINED #endif // !GUID_DEFINED -constexpr GUID JITEEVersionIdentifier = { /* 15b8f677-894e-4671-9dc8-fc4e2c50e269 */ - 0x15b8f677, - 0x894e, - 0x4671, - {0x9d, 0xc8, 0xfc, 0x4e, 0x2c, 0x50, 0xe2, 0x69} +constexpr GUID JITEEVersionIdentifier = { /* 9ed85c09-d33d-4855-80ea-e3b7330e8173 */ + 0x9ed85c09, + 0xd33d, + 0x4855, + {0x80, 0xea, 0xe3, 0xb7, 0x33, 0x0e, 0x81, 0x73} }; ////////////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/src/coreclr/jit/hwintrinsic.cpp b/src/coreclr/jit/hwintrinsic.cpp index 03d459da2d441..e598d774d9dd9 100644 --- a/src/coreclr/jit/hwintrinsic.cpp +++ b/src/coreclr/jit/hwintrinsic.cpp @@ -834,7 +834,6 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = { { NI_Illegal, NI_Illegal }, // AVX512VBMI_X64 { FIRST_NI_AVX10v1_X64, LAST_NI_AVX10v1_X64 }, { NI_Illegal, NI_Illegal }, // AVX10v1_V512_X64 - { NI_Illegal, NI_Illegal }, // APX_X64 { NI_Illegal, NI_Illegal }, // AVX10v2_X64 { NI_Illegal, NI_Illegal }, // AVX10v2_V512_X64 #elif defined (TARGET_ARM64) diff --git a/src/coreclr/scripts/out.txt b/src/coreclr/scripts/out.txt new file mode 100644 index 0000000000000000000000000000000000000000..3eef6d37b76f8a78c8cb4078d4ea48368b6e6b72 GIT binary patch literal 68524 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b/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs @@ -215,7 +215,6 @@ public static int FromInstructionSet(InstructionSet instructionSet) InstructionSet.X64_APX => Apx, InstructionSet.X64_PCLMULQDQ_V256 => Vpclmulqdq, InstructionSet.X64_PCLMULQDQ_V512 => (Vpclmulqdq | Avx512), - InstructionSet.X64_APX_X64 => Apx, InstructionSet.X64_AVX10v2 => Avx10v2, InstructionSet.X64_AVX10v2_X64 => Avx10v2, InstructionSet.X64_AVX10v2_V512 => (Avx10v2 | Avx512), diff --git a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs index 6b16c470cd048..9c4042e255b41 100644 --- a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs +++ b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs @@ -123,7 +123,6 @@ public static class ReadyToRunInstructionSetHelper case InstructionSet.X64_VectorT256: return ReadyToRunInstructionSet.VectorT256; case InstructionSet.X64_VectorT512: return ReadyToRunInstructionSet.VectorT512; case InstructionSet.X64_APX: return ReadyToRunInstructionSet.Apx; - case InstructionSet.X64_APX_X64: return ReadyToRunInstructionSet.Apx; case InstructionSet.X64_AVX10v2: return ReadyToRunInstructionSet.Avx10v2; case InstructionSet.X64_AVX10v2_X64: return ReadyToRunInstructionSet.Avx10v2; case InstructionSet.X64_AVX10v2_V512: return ReadyToRunInstructionSet.Avx10v2_V512; @@ -203,7 +202,6 @@ public static class ReadyToRunInstructionSetHelper case InstructionSet.X86_VectorT256: return ReadyToRunInstructionSet.VectorT256; case InstructionSet.X86_VectorT512: return ReadyToRunInstructionSet.VectorT512; case InstructionSet.X86_APX: return ReadyToRunInstructionSet.Apx; - case InstructionSet.X86_APX_X64: return null; case InstructionSet.X86_AVX10v2: return ReadyToRunInstructionSet.Avx10v2; case InstructionSet.X86_AVX10v2_X64: return null; case InstructionSet.X86_AVX10v2_V512: return ReadyToRunInstructionSet.Avx10v2_V512; diff --git a/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs b/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs index 0174c65d1a70c..18d9c54a11ec4 100644 --- a/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs +++ b/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs @@ -109,7 +109,6 @@ public enum InstructionSet X64_AVX512VBMI_X64 = InstructionSet_X64.AVX512VBMI_X64, X64_AVX10v1_X64 = InstructionSet_X64.AVX10v1_X64, X64_AVX10v1_V512_X64 = InstructionSet_X64.AVX10v1_V512_X64, - X64_APX_X64 = InstructionSet_X64.APX_X64, X64_AVX10v2_X64 = InstructionSet_X64.AVX10v2_X64, X64_AVX10v2_V512_X64 = InstructionSet_X64.AVX10v2_V512_X64, X86_X86Base = InstructionSet_X86.X86Base, @@ -180,7 +179,6 @@ public enum InstructionSet X86_AVX512VBMI_X64 = InstructionSet_X86.AVX512VBMI_X64, X86_AVX10v1_X64 = InstructionSet_X86.AVX10v1_X64, X86_AVX10v1_V512_X64 = InstructionSet_X86.AVX10v1_V512_X64, - X86_APX_X64 = InstructionSet_X86.APX_X64, X86_AVX10v2_X64 = InstructionSet_X86.AVX10v2_X64, X86_AVX10v2_V512_X64 = InstructionSet_X86.AVX10v2_V512_X64, } @@ -287,9 +285,8 @@ public enum InstructionSet_X64 AVX512VBMI_X64 = 66, AVX10v1_X64 = 67, AVX10v1_V512_X64 = 68, - APX_X64 = 69, - AVX10v2_X64 = 70, - AVX10v2_V512_X64 = 71, + AVX10v2_X64 = 69, + AVX10v2_V512_X64 = 70, } public enum InstructionSet_X86 @@ -364,9 +361,8 @@ public enum InstructionSet_X86 AVX512VBMI_X64 = 66, AVX10v1_X64 = 67, AVX10v1_V512_X64 = 68, - APX_X64 = 69, - AVX10v2_X64 = 70, - AVX10v2_V512_X64 = 71, + AVX10v2_X64 = 69, + AVX10v2_V512_X64 = 70, } public unsafe struct InstructionSetFlags : IEnumerable @@ -686,10 +682,6 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target resultflags.AddInstructionSet(InstructionSet.X64_AVX10v1_V512_X64); if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v1_V512_X64)) resultflags.AddInstructionSet(InstructionSet.X64_AVX10v1_V512); - if (resultflags.HasInstructionSet(InstructionSet.X64_APX)) - resultflags.AddInstructionSet(InstructionSet.X64_APX_X64); - if (resultflags.HasInstructionSet(InstructionSet.X64_APX_X64)) - resultflags.AddInstructionSet(InstructionSet.X64_APX); if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v2)) resultflags.AddInstructionSet(InstructionSet.X64_AVX10v2_X64); if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v2_X64)) @@ -1049,8 +1041,6 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe resultflags.AddInstructionSet(InstructionSet.X64_AVX10v1); if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v1_V512_X64)) resultflags.AddInstructionSet(InstructionSet.X64_AVX10v1_V512); - if (resultflags.HasInstructionSet(InstructionSet.X64_APX_X64)) - resultflags.AddInstructionSet(InstructionSet.X64_APX); if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v2_X64)) resultflags.AddInstructionSet(InstructionSet.X64_AVX10v2); if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v2_V512_X64)) @@ -1536,8 +1526,6 @@ public void Set64BitInstructionSetVariants(TargetArchitecture architecture) AddInstructionSet(InstructionSet.X64_AVX10v1_X64); if (HasInstructionSet(InstructionSet.X64_AVX10v1_V512)) AddInstructionSet(InstructionSet.X64_AVX10v1_V512_X64); - if (HasInstructionSet(InstructionSet.X64_APX)) - AddInstructionSet(InstructionSet.X64_APX_X64); if (HasInstructionSet(InstructionSet.X64_AVX10v2)) AddInstructionSet(InstructionSet.X64_AVX10v2_X64); if (HasInstructionSet(InstructionSet.X64_AVX10v2_V512)) @@ -1592,7 +1580,6 @@ public void Set64BitInstructionSetVariantsUnconditionally(TargetArchitecture arc AddInstructionSet(InstructionSet.X64_AVX512VBMI_X64); AddInstructionSet(InstructionSet.X64_AVX10v1_X64); AddInstructionSet(InstructionSet.X64_AVX10v1_V512_X64); - AddInstructionSet(InstructionSet.X64_APX_X64); AddInstructionSet(InstructionSet.X64_AVX10v2_X64); AddInstructionSet(InstructionSet.X64_AVX10v2_V512_X64); break; @@ -1623,7 +1610,6 @@ public void Set64BitInstructionSetVariantsUnconditionally(TargetArchitecture arc AddInstructionSet(InstructionSet.X86_AVX512VBMI_X64); AddInstructionSet(InstructionSet.X86_AVX10v1_X64); AddInstructionSet(InstructionSet.X86_AVX10v1_V512_X64); - AddInstructionSet(InstructionSet.X86_APX_X64); AddInstructionSet(InstructionSet.X86_AVX10v2_X64); AddInstructionSet(InstructionSet.X86_AVX10v2_V512_X64); break; @@ -1928,9 +1914,6 @@ public static InstructionSet LookupPlatformIntrinsicInstructionSet(TargetArchite { return InstructionSet.X64_VectorT512; } case "Apx": - if (nestedTypeName == "X64") - { return InstructionSet.X64_APX_X64; } - else { return InstructionSet.X64_APX; } case "Avx10v2": diff --git a/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt b/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt index 6278e18f46d03..99a15a2cacfe1 100644 --- a/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt +++ b/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt @@ -96,7 +96,6 @@ instructionset64bit,X86 ,AVX512DQ instructionset64bit,X86 ,AVX512VBMI instructionset64bit,X86 ,AVX10v1 instructionset64bit,X86 ,AVX10v1_V512 -instructionset64bit,X86 ,APX instructionset64bit,X86 ,AVX10v2 instructionset64bit,X86 ,AVX10v2_V512 From ac909d289e4e7d070649539076e6a91e508c3949 Mon Sep 17 00:00:00 2001 From: Khushal Modi Date: Wed, 20 Nov 2024 10:32:48 -0800 Subject: [PATCH 4/5] remove log file and change handling for AVX10v2_V512 --- src/coreclr/scripts/out.txt | Bin 68524 -> 0 bytes .../Common/Compiler/InstructionSetSupport.cs | 5 +++-- 2 files changed, 3 insertions(+), 2 deletions(-) delete mode 100644 src/coreclr/scripts/out.txt diff --git a/src/coreclr/scripts/out.txt b/src/coreclr/scripts/out.txt deleted file mode 100644 index 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100644 --- a/src/coreclr/tools/Common/Compiler/InstructionSetSupport.cs +++ b/src/coreclr/tools/Common/Compiler/InstructionSetSupport.cs @@ -361,8 +361,9 @@ public bool ComputeInstructionSetFlags(int maxVectorTBitWidth, if (_supportedInstructionSets.Contains("vpclmul")) _supportedInstructionSets.Add("vpclmul_v512"); - // Having AVX10V1-V512 enabled, means having AVX10V2-V512 enabled as well. - if (_supportedInstructionSets.Contains("avx10v1_v512")) + // Having AVX10V2 and any AVX-512 instruction sets enabled, + // automatically implies AVX10V2-V512 as well. + if (_supportedInstructionSets.Contains("avx10v2")) _supportedInstructionSets.Add("avx10v2_v512"); } From 0eaa7449055de1c0fcabd1437f5fe9298b18a71f Mon Sep 17 00:00:00 2001 From: Khushal Modi Date: Wed, 20 Nov 2024 14:07:18 -0800 Subject: [PATCH 5/5] resolve merge errors --- src/native/minipal/cpufeatures.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/native/minipal/cpufeatures.h b/src/native/minipal/cpufeatures.h index 77e4779a86fe0..1a48dbb92dd60 100644 --- a/src/native/minipal/cpufeatures.h +++ b/src/native/minipal/cpufeatures.h @@ -32,11 +32,8 @@ enum XArchIntrinsicConstants XArchIntrinsicConstants_Avx10v1 = 0x40000, XArchIntrinsicConstants_Evex = 0x80000, XArchIntrinsicConstants_Apx = 0x100000, -<<<<<<< HEAD XArchIntrinsicConstants_Vpclmulqdq = 0x200000, -======= - XArchIntrinsicConstants_Avx10v2 = 0x200000, ->>>>>>> 40f24a90a65 (Add CPUID for AVX10.2) + XArchIntrinsicConstants_Avx10v2 = 0x400000, }; #endif // HOST_X86 || HOST_AMD64