From d6fa3d1dd9d48865eabd0bccb7ff0a6d64217000 Mon Sep 17 00:00:00 2001 From: Tanner Gooding Date: Wed, 21 Apr 2021 08:22:19 -0700 Subject: [PATCH 1/2] Don't have gtAuxiliaryJitType and gtOtherReg share a union --- src/coreclr/jit/gentree.cpp | 4 +++- src/coreclr/jit/gentree.h | 7 ++----- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp index c2f53c00f80d8..eb809383761e3 100644 --- a/src/coreclr/jit/gentree.cpp +++ b/src/coreclr/jit/gentree.cpp @@ -1492,7 +1492,8 @@ bool GenTree::Compare(GenTree* op1, GenTree* op2, bool swapOK) if ((op1->AsHWIntrinsic()->gtHWIntrinsicId != op2->AsHWIntrinsic()->gtHWIntrinsicId) || (op1->AsHWIntrinsic()->GetSimdBaseType() != op2->AsHWIntrinsic()->GetSimdBaseType()) || (op1->AsHWIntrinsic()->GetSimdSize() != op2->AsHWIntrinsic()->GetSimdSize()) || - (op1->AsHWIntrinsic()->GetAuxiliaryType() != op2->AsHWIntrinsic()->GetAuxiliaryType())) + (op1->AsHWIntrinsic()->GetAuxiliaryType() != op2->AsHWIntrinsic()->GetAuxiliaryType()) || + (op1->AsHWIntrinsic()->GetOtherReg() != op2->AsHWIntrinsic()->GetOtherReg())) { return false; } @@ -2163,6 +2164,7 @@ unsigned Compiler::gtHashValue(GenTree* tree) hash += tree->AsHWIntrinsic()->GetSimdBaseType(); hash += tree->AsHWIntrinsic()->GetSimdSize(); hash += tree->AsHWIntrinsic()->GetAuxiliaryType(); + hash += tree->AsHWIntrinsic()->GetOtherReg(); break; #endif // FEATURE_HW_INTRINSICS diff --git a/src/coreclr/jit/gentree.h b/src/coreclr/jit/gentree.h index 22f692d6c745c..4e652d1043ac0 100644 --- a/src/coreclr/jit/gentree.h +++ b/src/coreclr/jit/gentree.h @@ -4849,11 +4849,8 @@ struct GenTreeJitIntrinsic : public GenTreeOp private: ClassLayout* m_layout; - union { - unsigned char gtAuxiliaryJitType; // For intrinsics than need another type (e.g. Avx2.Gather* or SIMD (by - // element)) - regNumberSmall gtOtherReg; // For intrinsics that return 2 registers - }; + unsigned char gtAuxiliaryJitType; // For intrinsics than need another type (e.g. Avx2.Gather* or SIMD (by element)) + regNumberSmall gtOtherReg; // For intrinsics that return 2 registers unsigned char gtSimdBaseJitType; // SIMD vector base JIT type unsigned char gtSimdSize; // SIMD vector size in bytes, use 0 for scalar intrinsics From f683ddba55dbf936315cb64de62ad78f3938a9b5 Mon Sep 17 00:00:00 2001 From: Tanner Gooding Date: Wed, 21 Apr 2021 08:48:22 -0700 Subject: [PATCH 2/2] Applying formatting patch --- src/coreclr/jit/gentree.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/coreclr/jit/gentree.h b/src/coreclr/jit/gentree.h index 4e652d1043ac0..3901c057cc782 100644 --- a/src/coreclr/jit/gentree.h +++ b/src/coreclr/jit/gentree.h @@ -4849,8 +4849,8 @@ struct GenTreeJitIntrinsic : public GenTreeOp private: ClassLayout* m_layout; - unsigned char gtAuxiliaryJitType; // For intrinsics than need another type (e.g. Avx2.Gather* or SIMD (by element)) - regNumberSmall gtOtherReg; // For intrinsics that return 2 registers + unsigned char gtAuxiliaryJitType; // For intrinsics than need another type (e.g. Avx2.Gather* or SIMD (by element)) + regNumberSmall gtOtherReg; // For intrinsics that return 2 registers unsigned char gtSimdBaseJitType; // SIMD vector base JIT type unsigned char gtSimdSize; // SIMD vector size in bytes, use 0 for scalar intrinsics