diff --git a/src/coreclr/jit/assertionprop.cpp b/src/coreclr/jit/assertionprop.cpp
index 3a91b5a2e11bd..de6e06fa883d0 100644
--- a/src/coreclr/jit/assertionprop.cpp
+++ b/src/coreclr/jit/assertionprop.cpp
@@ -3220,6 +3220,7 @@ GenTree* Compiler::optVNConstantPropOnTree(BasicBlock* block, GenTree* tree)
             break;
         }
 
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
         {
             simd32_t value = vnStore->ConstantValue<simd32_t>(vnCns);
@@ -3230,7 +3231,7 @@ GenTree* Compiler::optVNConstantPropOnTree(BasicBlock* block, GenTree* tree)
             conValTree = vecCon;
             break;
         }
-        break;
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
         case TYP_BYREF:
diff --git a/src/coreclr/jit/compiler.h b/src/coreclr/jit/compiler.h
index b7eb5c20d69df..a471138d30112 100644
--- a/src/coreclr/jit/compiler.h
+++ b/src/coreclr/jit/compiler.h
@@ -7638,7 +7638,7 @@ class Compiler
         return ((type == TYP_SIMD16) || (type == TYP_SIMD12));
     }
 #else // !defined(TARGET_AMD64) && !defined(TARGET_ARM64)
-#error("Unknown target architecture for FEATURE_SIMD")
+#error("Unknown target architecture for FEATURE_PARTIAL_SIMD_CALLEE_SAVE")
 #endif // !defined(TARGET_AMD64) && !defined(TARGET_ARM64)
 #endif // FEATURE_PARTIAL_SIMD_CALLEE_SAVE
 
@@ -8511,8 +8511,10 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
                     return NO_CLASS_HANDLE;
                 }
 
+#if defined(TARGET_XARCH)
                 case TYP_SIMD32:
                     break;
+#endif // TARGET_XARCH
 
                 default:
                     unreached();
@@ -8615,8 +8617,10 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
                 return m_simdHandleCache->SIMDVector3Handle;
             case TYP_SIMD16:
                 return m_simdHandleCache->CanonicalSimd16Handle;
+#if defined(TARGET_XARCH)
             case TYP_SIMD32:
                 return m_simdHandleCache->CanonicalSimd32Handle;
+#endif // TARGET_XARCH
             default:
                 unreached();
         }
@@ -8859,10 +8863,12 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
         {
             simdType = TYP_SIMD16;
         }
+#if defined(TARGET_XARCH)
         else if (size == 32)
         {
             simdType = TYP_SIMD32;
         }
+#endif // TARGET_XARCH
         else
         {
             noway_assert(!"Unexpected size for SIMD type");
diff --git a/src/coreclr/jit/emit.cpp b/src/coreclr/jit/emit.cpp
index 1749c6cc20afc..fe2729dc5f57d 100644
--- a/src/coreclr/jit/emit.cpp
+++ b/src/coreclr/jit/emit.cpp
@@ -7892,6 +7892,7 @@ CORINFO_FIELD_HANDLE emitter::emitFltOrDblConst(double constValue, emitAttr attr
     return emitComp->eeFindJitDataOffs(cnum);
 }
 
+#if defined(FEATURE_SIMD)
 //------------------------------------------------------------------------
 // emitSimd8Const: Create a simd8 data section constant.
 //
@@ -7908,7 +7909,6 @@ CORINFO_FIELD_HANDLE emitter::emitSimd8Const(simd8_t constValue)
     // to constant data, not a real static field.
     CLANG_FORMAT_COMMENT_ANCHOR;
 
-#if defined(FEATURE_SIMD)
     unsigned cnsSize  = 8;
     unsigned cnsAlign = cnsSize;
 
@@ -7921,9 +7921,6 @@ CORINFO_FIELD_HANDLE emitter::emitSimd8Const(simd8_t constValue)
 
     UNATIVE_OFFSET cnum = emitDataConst(&constValue, cnsSize, cnsAlign, TYP_SIMD8);
     return emitComp->eeFindJitDataOffs(cnum);
-#else
-    unreached();
-#endif // !FEATURE_SIMD
 }
 
 CORINFO_FIELD_HANDLE emitter::emitSimd16Const(simd16_t constValue)
@@ -7933,7 +7930,6 @@ CORINFO_FIELD_HANDLE emitter::emitSimd16Const(simd16_t constValue)
     // to constant data, not a real static field.
     CLANG_FORMAT_COMMENT_ANCHOR;
 
-#if defined(FEATURE_SIMD)
     unsigned cnsSize  = 16;
     unsigned cnsAlign = cnsSize;
 
@@ -7946,11 +7942,9 @@ CORINFO_FIELD_HANDLE emitter::emitSimd16Const(simd16_t constValue)
 
     UNATIVE_OFFSET cnum = emitDataConst(&constValue, cnsSize, cnsAlign, TYP_SIMD16);
     return emitComp->eeFindJitDataOffs(cnum);
-#else
-    unreached();
-#endif // !FEATURE_SIMD
 }
 
+#if defined(TARGET_XARCH)
 CORINFO_FIELD_HANDLE emitter::emitSimd32Const(simd32_t constValue)
 {
     // Access to inline data is 'abstracted' by a special type of static member
@@ -7958,23 +7952,19 @@ CORINFO_FIELD_HANDLE emitter::emitSimd32Const(simd32_t constValue)
     // to constant data, not a real static field.
     CLANG_FORMAT_COMMENT_ANCHOR;
 
-#if defined(FEATURE_SIMD)
     unsigned cnsSize  = 32;
     unsigned cnsAlign = cnsSize;
 
-#ifdef TARGET_XARCH
     if (emitComp->compCodeOpt() == Compiler::SMALL_CODE)
     {
         cnsAlign = dataSection::MIN_DATA_ALIGN;
     }
-#endif // TARGET_XARCH
 
     UNATIVE_OFFSET cnum = emitDataConst(&constValue, cnsSize, cnsAlign, TYP_SIMD32);
     return emitComp->eeFindJitDataOffs(cnum);
-#else
-    unreached();
-#endif // !FEATURE_SIMD
 }
+#endif // TARGET_XARCH
+#endif // FEATURE_SIMD
 
 /*****************************************************************************
  *
diff --git a/src/coreclr/jit/emit.h b/src/coreclr/jit/emit.h
index 6fdbd8bf5abd9..8e0c64d1b0832 100644
--- a/src/coreclr/jit/emit.h
+++ b/src/coreclr/jit/emit.h
@@ -2058,9 +2058,13 @@ class emitter
 #endif // TARGET_AMD64
 
     CORINFO_FIELD_HANDLE emitFltOrDblConst(double constValue, emitAttr attr);
+#if defined(FEATURE_SIMD)
     CORINFO_FIELD_HANDLE emitSimd8Const(simd8_t constValue);
     CORINFO_FIELD_HANDLE emitSimd16Const(simd16_t constValue);
+#if defined(TARGET_XARCH)
     CORINFO_FIELD_HANDLE emitSimd32Const(simd32_t constValue);
+#endif // TARGET_XARCH
+#endif // FEATURE_SIMD
     regNumber emitInsBinary(instruction ins, emitAttr attr, GenTree* dst, GenTree* src);
     regNumber emitInsTernary(instruction ins, emitAttr attr, GenTree* dst, GenTree* src1, GenTree* src2);
     void emitInsLoadInd(instruction ins, emitAttr attr, regNumber dstReg, GenTreeIndir* mem);
diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp
index 1b25efbb37629..abe3639c56802 100644
--- a/src/coreclr/jit/gentree.cpp
+++ b/src/coreclr/jit/gentree.cpp
@@ -3045,6 +3045,7 @@ unsigned Compiler::gtHashValue(GenTree* tree)
                 switch (vecCon->TypeGet())
                 {
 #if defined(FEATURE_SIMD)
+#if defined(TARGET_XARCH)
                     case TYP_SIMD32:
                     {
                         add = genTreeHashAdd(ulo32(add), vecCon->gtSimd32Val.u32[7]);
@@ -3053,6 +3054,7 @@ unsigned Compiler::gtHashValue(GenTree* tree)
                         add = genTreeHashAdd(ulo32(add), vecCon->gtSimd32Val.u32[4]);
                         FALLTHROUGH;
                     }
+#endif // TARGET_XARCH
 
                     case TYP_SIMD16:
                     {
@@ -7274,13 +7276,17 @@ GenTree* Compiler::gtNewAllBitsSetConNode(var_types type)
         case TYP_SIMD8:
         case TYP_SIMD12:
         case TYP_SIMD16:
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
+#endif // TARGET_XARCH
+        {
             allBitsSet                                 = gtNewVconNode(type);
             allBitsSet->AsVecCon()->gtSimd32Val.i64[0] = -1;
             allBitsSet->AsVecCon()->gtSimd32Val.i64[1] = -1;
             allBitsSet->AsVecCon()->gtSimd32Val.i64[2] = -1;
             allBitsSet->AsVecCon()->gtSimd32Val.i64[3] = -1;
             break;
+        }
 #endif // FEATURE_SIMD
 
         default:
@@ -7315,7 +7321,9 @@ GenTree* Compiler::gtNewZeroConNode(var_types type)
         case TYP_SIMD8:
         case TYP_SIMD12:
         case TYP_SIMD16:
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
+#endif // TARGET_XARCH
         {
             zero                          = gtNewVconNode(type);
             zero->AsVecCon()->gtSimd32Val = {};
@@ -7355,7 +7363,9 @@ GenTree* Compiler::gtNewOneConNode(var_types type, var_types simdBaseType /* = T
         case TYP_SIMD8:
         case TYP_SIMD12:
         case TYP_SIMD16:
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
+#endif // TARGET_XARCH
         {
             GenTreeVecCon* vecCon = gtNewVconNode(type);
 
@@ -11559,6 +11569,7 @@ void Compiler::gtDispConst(GenTree* tree)
                     break;
                 }
 
+#if defined(TARGET_XARCH)
                 case TYP_SIMD32:
                 {
                     simd32_t simdVal = vecCon->gtSimd32Val;
@@ -11566,6 +11577,7 @@ void Compiler::gtDispConst(GenTree* tree)
                            simdVal.u64[2], simdVal.u64[3]);
                     break;
                 }
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
                 default:
diff --git a/src/coreclr/jit/gentree.h b/src/coreclr/jit/gentree.h
index bf2419769e5ea..9161226118cd9 100644
--- a/src/coreclr/jit/gentree.h
+++ b/src/coreclr/jit/gentree.h
@@ -3386,11 +3386,13 @@ struct GenTreeVecCon : public GenTree
                 return (gtSimd16Val.u64[0] == 0xFFFFFFFFFFFFFFFF) && (gtSimd16Val.u64[1] == 0xFFFFFFFFFFFFFFFF);
             }
 
+#if defined(TARGET_XARCH)
             case TYP_SIMD32:
             {
                 return (gtSimd32Val.u64[0] == 0xFFFFFFFFFFFFFFFF) && (gtSimd32Val.u64[1] == 0xFFFFFFFFFFFFFFFF) &&
                        (gtSimd32Val.u64[2] == 0xFFFFFFFFFFFFFFFF) && (gtSimd32Val.u64[3] == 0xFFFFFFFFFFFFFFFF);
             }
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
             default:
@@ -3430,6 +3432,7 @@ struct GenTreeVecCon : public GenTree
                        (left->gtSimd16Val.u64[1] == right->gtSimd16Val.u64[1]);
             }
 
+#if defined(TARGET_XARCH)
             case TYP_SIMD32:
             {
                 return (left->gtSimd32Val.u64[0] == right->gtSimd32Val.u64[0]) &&
@@ -3437,6 +3440,7 @@ struct GenTreeVecCon : public GenTree
                        (left->gtSimd32Val.u64[2] == right->gtSimd32Val.u64[2]) &&
                        (left->gtSimd32Val.u64[3] == right->gtSimd32Val.u64[3]);
             }
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
             default:
@@ -3467,11 +3471,13 @@ struct GenTreeVecCon : public GenTree
                 return (gtSimd16Val.u64[0] == 0x0000000000000000) && (gtSimd16Val.u64[1] == 0x0000000000000000);
             }
 
+#if defined(TARGET_XARCH)
             case TYP_SIMD32:
             {
                 return (gtSimd32Val.u64[0] == 0x0000000000000000) && (gtSimd32Val.u64[1] == 0x0000000000000000) &&
                        (gtSimd32Val.u64[2] == 0x0000000000000000) && (gtSimd32Val.u64[3] == 0x0000000000000000);
             }
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
             default:
diff --git a/src/coreclr/jit/hwintrinsic.cpp b/src/coreclr/jit/hwintrinsic.cpp
index 341f14a460b42..9b8db1759571d 100644
--- a/src/coreclr/jit/hwintrinsic.cpp
+++ b/src/coreclr/jit/hwintrinsic.cpp
@@ -126,7 +126,7 @@ CORINFO_CLASS_HANDLE Compiler::gtGetStructHandleForHWSIMD(var_types simdType, Co
                 assert(!"Didn't find a class handle for simdType");
         }
     }
-#ifdef TARGET_XARCH
+#if defined(TARGET_XARCH)
     else if (simdType == TYP_SIMD32)
     {
         switch (simdBaseJitType)
diff --git a/src/coreclr/jit/importervectorization.cpp b/src/coreclr/jit/importervectorization.cpp
index dc8c685e6915e..da99ed05be826 100644
--- a/src/coreclr/jit/importervectorization.cpp
+++ b/src/coreclr/jit/importervectorization.cpp
@@ -82,7 +82,7 @@ static bool ConvertToLowerCase(WCHAR* input, WCHAR* mask, int length)
 //
 static GenTreeVecCon* CreateConstVector(Compiler* comp, var_types simdType, WCHAR* cns)
 {
-#ifdef TARGET_XARCH
+#if defined(TARGET_XARCH)
     if (simdType == TYP_SIMD32)
     {
         simd32_t       simd32Val = {};
diff --git a/src/coreclr/jit/instr.cpp b/src/coreclr/jit/instr.cpp
index 91e018cbd8ac8..635907a6f77c8 100644
--- a/src/coreclr/jit/instr.cpp
+++ b/src/coreclr/jit/instr.cpp
@@ -802,11 +802,13 @@ CodeGen::OperandDesc CodeGen::genOperandDesc(GenTree* op)
                         return OperandDesc(emit->emitSimd16Const(constValue));
                     }
 
+#if defined(TARGET_XARCH)
                     case TYP_SIMD32:
                     {
                         simd32_t constValue = op->AsVecCon()->gtSimd32Val;
                         return OperandDesc(emit->emitSimd32Const(constValue));
                     }
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
                     default:
diff --git a/src/coreclr/jit/lclvars.cpp b/src/coreclr/jit/lclvars.cpp
index 7cd22c1d9ed6d..5e3fd02434ae5 100644
--- a/src/coreclr/jit/lclvars.cpp
+++ b/src/coreclr/jit/lclvars.cpp
@@ -3792,7 +3792,9 @@ void Compiler::lvaSortByRefCount()
                 case TYP_SIMD8:
                 case TYP_SIMD12:
                 case TYP_SIMD16:
+#if defined(TARGET_XARCH)
                 case TYP_SIMD32:
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
                 case TYP_STRUCT:
                     break;
diff --git a/src/coreclr/jit/lowerarmarch.cpp b/src/coreclr/jit/lowerarmarch.cpp
index ecbfbfdf0a518..c7ce2e4741bef 100644
--- a/src/coreclr/jit/lowerarmarch.cpp
+++ b/src/coreclr/jit/lowerarmarch.cpp
@@ -1085,8 +1085,6 @@ void Lowering::LowerHWIntrinsicFusedMultiplyAddScalar(GenTreeHWIntrinsic* node)
 //
 GenTree* Lowering::LowerHWIntrinsic(GenTreeHWIntrinsic* node)
 {
-    assert(node->TypeGet() != TYP_SIMD32);
-
     if (node->TypeGet() == TYP_SIMD12)
     {
         // GT_HWINTRINSIC node requiring to produce TYP_SIMD12 in fact
diff --git a/src/coreclr/jit/lsra.cpp b/src/coreclr/jit/lsra.cpp
index cc7c52054625b..05d536bb27fbe 100644
--- a/src/coreclr/jit/lsra.cpp
+++ b/src/coreclr/jit/lsra.cpp
@@ -733,7 +733,12 @@ LinearScan::LinearScan(Compiler* theCompiler)
             availableRegs[i] = &availableDoubleRegs;
         }
 #ifdef FEATURE_SIMD
+#if defined(TARGET_XARCH)
         else if ((thisType >= TYP_SIMD8) && (thisType <= TYP_SIMD32))
+#else
+        else if ((thisType >= TYP_SIMD8) && (thisType <= TYP_SIMD16))
+#endif // TARGET_XARCH
+
         {
             availableRegs[i] = &availableDoubleRegs;
         }
@@ -1595,8 +1600,12 @@ bool LinearScan::isRegCandidate(LclVarDsc* varDsc)
         case TYP_SIMD8:
         case TYP_SIMD12:
         case TYP_SIMD16:
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
+#endif // TARGET_XARCH
+        {
             return !varDsc->lvPromoted;
+        }
 #endif // FEATURE_SIMD
 
         case TYP_STRUCT:
diff --git a/src/coreclr/jit/morphblock.cpp b/src/coreclr/jit/morphblock.cpp
index 87670bf634909..deb4322d5997e 100644
--- a/src/coreclr/jit/morphblock.cpp
+++ b/src/coreclr/jit/morphblock.cpp
@@ -596,11 +596,16 @@ void MorphInitBlockHelper::TryInitFieldByField()
             case TYP_SIMD8:
             case TYP_SIMD12:
             case TYP_SIMD16:
+#if defined(TARGET_XARCH)
             case TYP_SIMD32:
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
+            {
                 assert(initPattern == 0);
                 src = m_comp->gtNewZeroConNode(fieldType);
                 break;
+            }
+
             default:
                 unreached();
         }
diff --git a/src/coreclr/jit/optcse.cpp b/src/coreclr/jit/optcse.cpp
index 93e5d0916ed2b..5446301ca38f5 100644
--- a/src/coreclr/jit/optcse.cpp
+++ b/src/coreclr/jit/optcse.cpp
@@ -2655,9 +2655,10 @@ class CSE_Heuristic
                 //
                 int spillSimdRegInProlog = 1;
 
-                // If we have a SIMD32 that is live across a call we have even higher spill costs
-                //
-                if (candidate->Expr()->TypeGet() == TYP_SIMD32)
+// If we have a SIMD32 that is live across a call we have even higher spill costs
+//
+#if defined(TARGET_XARCH)
+                if (candidate->Expr()->TypeIs(TYP_SIMD32))
                 {
                     // Additionally for a simd32 CSE candidate we assume that and second spilled/restore will be needed.
                     // (to hold the upper half of the simd32 register that isn't preserved across the call)
@@ -2669,6 +2670,7 @@ class CSE_Heuristic
                     //
                     cse_use_cost += 2;
                 }
+#endif // TARGET_XARCH
 
                 extra_yes_cost = (BB_UNITY_WEIGHT_UNSIGNED * spillSimdRegInProlog) * 3;
             }
diff --git a/src/coreclr/jit/scopeinfo.cpp b/src/coreclr/jit/scopeinfo.cpp
index 97df205af41bb..de3895dedc9d5 100644
--- a/src/coreclr/jit/scopeinfo.cpp
+++ b/src/coreclr/jit/scopeinfo.cpp
@@ -289,8 +289,10 @@ void CodeGenInterface::siVarLoc::siFillStackVarLoc(
         case TYP_SIMD8:
         case TYP_SIMD12:
         case TYP_SIMD16:
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
-#endif
+#endif // TARGET_XARCH
+#endif // FEATURE_SIMD
 #ifdef TARGET_64BIT
         case TYP_LONG:
         case TYP_DOUBLE:
@@ -423,7 +425,10 @@ void CodeGenInterface::siVarLoc::siFillRegisterVarLoc(
         case TYP_SIMD8:
         case TYP_SIMD12:
         case TYP_SIMD16:
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
+#endif // TARGET_XARCH
+        {
             this->vlType = VLT_REG_FP;
 
             // TODO-AMD64-Bug: ndp\clr\src\inc\corinfo.h has a definition of RegNum that only goes up to R15,
@@ -433,6 +438,7 @@ void CodeGenInterface::siVarLoc::siFillRegisterVarLoc(
             // in eeDispVar() --> getRegName() that regNumber is valid.
             this->vlReg.vlrReg = varDsc->GetRegNum();
             break;
+        }
 #endif // FEATURE_SIMD
 
         default:
diff --git a/src/coreclr/jit/typelist.h b/src/coreclr/jit/typelist.h
index ae804f591dedf..4265c2a0daa82 100644
--- a/src/coreclr/jit/typelist.h
+++ b/src/coreclr/jit/typelist.h
@@ -61,7 +61,9 @@ DEF_TP(LCLBLK  ,"lclBlk"  , TYP_LCLBLK,  TI_ERROR, 0,  0,  0,   1, 4, VTF_ANY) /
 DEF_TP(SIMD8    ,"simd8"  , TYP_SIMD8,   TI_STRUCT, 8, 8,  8,   2, 8, VTF_S|VTF_VEC)
 DEF_TP(SIMD12   ,"simd12" , TYP_SIMD12,  TI_STRUCT,12,16, 16,   4,16, VTF_S|VTF_VEC)
 DEF_TP(SIMD16   ,"simd16" , TYP_SIMD16,  TI_STRUCT,16,16, 16,   4,16, VTF_S|VTF_VEC)
+#if defined(TARGET_XARCH)
 DEF_TP(SIMD32   ,"simd32" , TYP_SIMD32,  TI_STRUCT,32,32, 32,   8,16, VTF_S|VTF_VEC)
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
 DEF_TP(UNKNOWN ,"unknown" ,TYP_UNKNOWN,  TI_ERROR, 0,  0,  0,   0, 0, VTF_ANY)
diff --git a/src/coreclr/jit/utils.cpp b/src/coreclr/jit/utils.cpp
index 93bcf7435c853..5d177ba592be6 100644
--- a/src/coreclr/jit/utils.cpp
+++ b/src/coreclr/jit/utils.cpp
@@ -249,12 +249,12 @@ const char* getRegNameFloat(regNumber reg, var_types type)
 #endif // FEATURE_SIMD
     assert((unsigned)reg < ArrLen(regNamesFloat));
 
-#ifdef FEATURE_SIMD
+#if defined(FEATURE_SIMD) && defined(TARGET_XARCH)
     if (type == TYP_SIMD32)
     {
         return regNamesYMM[reg];
     }
-#endif // FEATURE_SIMD
+#endif // FEATURE_SIMD && TARGET_XARCH
 
     return regNamesFloat[reg];
 #endif
diff --git a/src/coreclr/jit/valuenum.cpp b/src/coreclr/jit/valuenum.cpp
index ae3446d738404..91b1a5b4be9ee 100644
--- a/src/coreclr/jit/valuenum.cpp
+++ b/src/coreclr/jit/valuenum.cpp
@@ -1694,11 +1694,13 @@ ValueNumStore::Chunk::Chunk(CompAllocator alloc, ValueNum* pNextBaseVN, var_type
                     break;
                 }
 
+#if defined(TARGET_XARCH)
                 case TYP_SIMD32:
                 {
                     m_defs = new (alloc) Alloc<TYP_SIMD32>::Type[ChunkSize];
                     break;
                 }
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
                 default:
@@ -1852,10 +1854,12 @@ ValueNum ValueNumStore::VNForSimd16Con(simd16_t cnsVal)
     return VnForConst(cnsVal, GetSimd16CnsMap(), TYP_SIMD16);
 }
 
+#if defined(TARGET_XARCH)
 ValueNum ValueNumStore::VNForSimd32Con(simd32_t cnsVal)
 {
     return VnForConst(cnsVal, GetSimd32CnsMap(), TYP_SIMD32);
 }
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
 ValueNum ValueNumStore::VNForCastOper(var_types castToType, bool srcIsUnsigned)
@@ -1954,10 +1958,12 @@ ValueNum ValueNumStore::VNZeroForType(var_types typ)
             return VNForSimd16Con({});
         }
 
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
         {
             return VNForSimd32Con({});
         }
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
         // These should be unreached.
@@ -2056,6 +2062,7 @@ ValueNum ValueNumStore::VNAllBitsForType(var_types typ)
             return VNForSimd16Con(cnsVal);
         }
 
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
         {
             simd32_t cnsVal;
@@ -2072,6 +2079,7 @@ ValueNum ValueNumStore::VNAllBitsForType(var_types typ)
 
             return VNForSimd32Con(cnsVal);
         }
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
         default:
@@ -2176,10 +2184,12 @@ ValueNum ValueNumStore::VNOneForSimdType(var_types simdType, var_types simdBaseT
             return VNForSimd16Con(simd32Val.v128[0]);
         }
 
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
         {
             return VNForSimd32Con(simd32Val);
         }
+#endif // TARGET_XARCH
 
         default:
         {
@@ -3354,6 +3364,7 @@ simd16_t ValueNumStore::GetConstantSimd16(ValueNum argVN)
     return ConstantValue<simd16_t>(argVN);
 }
 
+#if defined(TARGET_XARCH)
 // Given a simd32 constant value number return its value as a simd32.
 //
 simd32_t ValueNumStore::GetConstantSimd32(ValueNum argVN)
@@ -3363,6 +3374,7 @@ simd32_t ValueNumStore::GetConstantSimd32(ValueNum argVN)
 
     return ConstantValue<simd32_t>(argVN);
 }
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
 // Compute the proper value number when the VNFunc has all constant arguments
@@ -6373,6 +6385,7 @@ simd16_t GetConstantSimd16(ValueNumStore* vns, var_types baseType, ValueNum argV
     return BroadcastConstantToSimd<simd16_t>(vns, baseType, argVN);
 }
 
+#if defined(TARGET_XARCH)
 simd32_t GetConstantSimd32(ValueNumStore* vns, var_types baseType, ValueNum argVN)
 {
     assert(vns->IsVNConstant(argVN));
@@ -6384,6 +6397,7 @@ simd32_t GetConstantSimd32(ValueNumStore* vns, var_types baseType, ValueNum argV
 
     return BroadcastConstantToSimd<simd32_t>(vns, baseType, argVN);
 }
+#endif // TARGET_XARCH
 
 ValueNum EvaluateUnarySimd(
     ValueNumStore* vns, genTreeOps oper, bool scalar, var_types simdType, var_types baseType, ValueNum arg0VN)
@@ -6417,6 +6431,7 @@ ValueNum EvaluateUnarySimd(
             return vns->VNForSimd16Con(result);
         }
 
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
         {
             simd32_t arg0 = GetConstantSimd32(vns, baseType, arg0VN);
@@ -6425,6 +6440,7 @@ ValueNum EvaluateUnarySimd(
             EvaluateUnarySimd<simd32_t>(oper, scalar, baseType, &result, arg0);
             return vns->VNForSimd32Con(result);
         }
+#endif // TARGET_XARCH
 
         default:
         {
@@ -6473,6 +6489,7 @@ ValueNum EvaluateBinarySimd(ValueNumStore* vns,
             return vns->VNForSimd16Con(result);
         }
 
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
         {
             simd32_t arg0 = GetConstantSimd32(vns, baseType, arg0VN);
@@ -6482,6 +6499,7 @@ ValueNum EvaluateBinarySimd(ValueNumStore* vns,
             EvaluateBinarySimd<simd32_t>(oper, scalar, baseType, &result, arg0, arg1);
             return vns->VNForSimd32Con(result);
         }
+#endif // TARGET_XARCH
 
         default:
         {
@@ -6581,10 +6599,12 @@ ValueNum EvaluateSimdGetElement(ValueNumStore* vns, var_types type, var_types ba
             return EvaluateSimdGetElement<simd16_t>(vns, baseType, vns->GetConstantSimd16(arg0VN), arg1);
         }
 
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
         {
             return EvaluateSimdGetElement<simd32_t>(vns, baseType, vns->GetConstantSimd32(arg0VN), arg1);
         }
+#endif // TARGET_XARCH
 
         default:
         {
@@ -8139,6 +8159,7 @@ void ValueNumStore::vnDump(Compiler* comp, ValueNum vn, bool isPtr)
                 break;
             }
 
+#if defined(TARGET_XARCH)
             case TYP_SIMD32:
             {
                 simd32_t cnsVal = GetConstantSimd32(vn);
@@ -8146,6 +8167,7 @@ void ValueNumStore::vnDump(Compiler* comp, ValueNum vn, bool isPtr)
                        cnsVal.u64[2], cnsVal.u64[3]);
                 break;
             }
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
             // These should be unreached.
@@ -9641,9 +9663,11 @@ void Compiler::fgValueNumberTreeConst(GenTree* tree)
             tree->gtVNPair.SetBoth(vnStore->VNForSimd16Con(tree->AsVecCon()->gtSimd16Val));
             break;
 
+#if defined(TARGET_XARCH)
         case TYP_SIMD32:
             tree->gtVNPair.SetBoth(vnStore->VNForSimd32Con(tree->AsVecCon()->gtSimd32Val));
             break;
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
         case TYP_FLOAT:
@@ -10091,8 +10115,8 @@ bool Compiler::fgValueNumberConstLoad(GenTreeIndir* tree)
                         tree->gtVNPair.SetBoth(vnStore->VNForSimd32Con(val));
                         return true;
                     }
-#endif
-#endif
+#endif // TARGET_XARCH
+#endif // FEATURE_SIMD
                     default:
                         assert(!varTypeIsSIMD(tree));
                         break;
diff --git a/src/coreclr/jit/valuenum.h b/src/coreclr/jit/valuenum.h
index b3dcc252a1332..e02b80f6725b0 100644
--- a/src/coreclr/jit/valuenum.h
+++ b/src/coreclr/jit/valuenum.h
@@ -352,7 +352,9 @@ class ValueNumStore
     simd8_t GetConstantSimd8(ValueNum argVN);
     simd12_t GetConstantSimd12(ValueNum argVN);
     simd16_t GetConstantSimd16(ValueNum argVN);
+#if defined(TARGET_XARCH)
     simd32_t GetConstantSimd32(ValueNum argVN);
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
 private:
@@ -434,7 +436,9 @@ class ValueNumStore
     ValueNum VNForSimd8Con(simd8_t cnsVal);
     ValueNum VNForSimd12Con(simd12_t cnsVal);
     ValueNum VNForSimd16Con(simd16_t cnsVal);
+#if defined(TARGET_XARCH)
     ValueNum VNForSimd32Con(simd32_t cnsVal);
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
 #ifdef TARGET_64BIT
@@ -1779,12 +1783,14 @@ struct ValueNumStore::VarTypConv<TYP_SIMD16>
     typedef simd16_t Type;
     typedef simd16_t Lang;
 };
+#if defined(TARGET_XARCH)
 template <>
 struct ValueNumStore::VarTypConv<TYP_SIMD32>
 {
     typedef simd32_t Type;
     typedef simd32_t Lang;
 };
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
 template <>
@@ -1846,12 +1852,14 @@ FORCEINLINE simd16_t ValueNumStore::SafeGetConstantValue<simd16_t>(Chunk* c, uns
     return reinterpret_cast<VarTypConv<TYP_SIMD16>::Lang*>(c->m_defs)[offset];
 }
 
+#if defined(TARGET_XARCH)
 template <>
 FORCEINLINE simd32_t ValueNumStore::SafeGetConstantValue<simd32_t>(Chunk* c, unsigned offset)
 {
     assert(c->m_typ == TYP_SIMD32);
     return reinterpret_cast<VarTypConv<TYP_SIMD32>::Lang*>(c->m_defs)[offset];
 }
+#endif // TARGET_XARCH
 
 template <>
 FORCEINLINE simd8_t ValueNumStore::ConstantValueInternal<simd8_t>(ValueNum vn DEBUGARG(bool coerce))
@@ -1895,6 +1903,7 @@ FORCEINLINE simd16_t ValueNumStore::ConstantValueInternal<simd16_t>(ValueNum vn
     return SafeGetConstantValue<simd16_t>(c, offset);
 }
 
+#if defined(TARGET_XARCH)
 template <>
 FORCEINLINE simd32_t ValueNumStore::ConstantValueInternal<simd32_t>(ValueNum vn DEBUGARG(bool coerce))
 {
@@ -1908,6 +1917,7 @@ FORCEINLINE simd32_t ValueNumStore::ConstantValueInternal<simd32_t>(ValueNum vn
 
     return SafeGetConstantValue<simd32_t>(c, offset);
 }
+#endif // TARGET_XARCH
 #endif // FEATURE_SIMD
 
 // Inline functions.