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nvml.h
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/*
* Copyright 1993-2016 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws. Users and possessors of this source code
* are hereby granted a nonexclusive, royalty-free license to use this code
* in individual and commercial software.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*
* Any use of this source code in individual and commercial software must
* include, in the user documentation and internal comments to the code,
* the above Disclaimer and U.S. Government End Users Notice.
*/
/*
NVML API Reference
The NVIDIA Management Library (NVML) is a C-based programmatic interface for monitoring and
managing various states within NVIDIA Tesla &tm; GPUs. It is intended to be a platform for building
3rd party applications, and is also the underlying library for the NVIDIA-supported nvidia-smi
tool. NVML is thread-safe so it is safe to make simultaneous NVML calls from multiple threads.
API Documentation
Supported platforms:
- Windows: Windows Server 2008 R2 64bit, Windows Server 2012 R2 64bit, Windows 7 64bit, Windows 8 64bit, Windows 10 64bit
- Linux: 32-bit and 64-bit
- Hypervisors: Windows Server 2008R2/2012 Hyper-V 64bit, Citrix XenServer 6.2 SP1+, VMware ESX 5.1/5.5
Supported products:
- Full Support
- All Tesla products, starting with the Fermi architecture
- All Quadro products, starting with the Fermi architecture
- All GRID products, starting with the Kepler architecture
- Selected GeForce Titan products
- Limited Support
- All Geforce products, starting with the Fermi architecture
The NVML library can be found at \%ProgramW6432\%\\"NVIDIA Corporation"\\NVSMI\\ on Windows. It is
not be added to the system path by default. To dynamically link to NVML, add this path to the PATH
environmental variable. To dynamically load NVML, call LoadLibrary with this path.
On Linux the NVML library will be found on the standard library path. For 64 bit Linux, both the 32 bit
and 64 bit NVML libraries will be installed.
Online documentation for this library is available at http://docs.nvidia.com/deploy/nvml-api/index.html
*/
#ifndef __nvml_nvml_h__
#define __nvml_nvml_h__
#ifdef __cplusplus
extern "C" {
#endif
/*
* On Windows, set up methods for DLL export
* define NVML_STATIC_IMPORT when using nvml_loader library
*/
#if defined _WINDOWS
#if !defined NVML_STATIC_IMPORT
#if defined NVML_LIB_EXPORT
#define DECLDIR __declspec(dllexport)
#else
#define DECLDIR __declspec(dllimport)
#endif
#else
#define DECLDIR
#endif
#else
#define DECLDIR
#endif
/**
* NVML API versioning support
*/
#define NVML_API_VERSION 8
#define NVML_API_VERSION_STR "8"
#define nvmlInit nvmlInit_v2
#define nvmlDeviceGetPciInfo nvmlDeviceGetPciInfo_v2
#define nvmlDeviceGetCount nvmlDeviceGetCount_v2
#define nvmlDeviceGetHandleByIndex nvmlDeviceGetHandleByIndex_v2
#define nvmlDeviceGetHandleByPciBusId nvmlDeviceGetHandleByPciBusId_v2
/***************************************************************************************************/
/** @defgroup nvmlDeviceStructs Device Structs
* @{
*/
/***************************************************************************************************/
/**
* Special constant that some fields take when they are not available.
* Used when only part of the struct is not available.
*
* Each structure explicitly states when to check for this value.
*/
#define NVML_VALUE_NOT_AVAILABLE (-1)
typedef struct nvmlDevice_st* nvmlDevice_t;
/**
* Buffer size guaranteed to be large enough for pci bus id
*/
#define NVML_DEVICE_PCI_BUS_ID_BUFFER_SIZE 16
/**
* PCI information about a GPU device.
*/
typedef struct nvmlPciInfo_st
{
char busId[NVML_DEVICE_PCI_BUS_ID_BUFFER_SIZE]; //!< The tuple domain:bus:device.function PCI identifier (& NULL terminator)
unsigned int domain; //!< The PCI domain on which the device's bus resides, 0 to 0xffff
unsigned int bus; //!< The bus on which the device resides, 0 to 0xff
unsigned int device; //!< The device's id on the bus, 0 to 31
unsigned int pciDeviceId; //!< The combined 16-bit device id and 16-bit vendor id
// Added in NVML 2.285 API
unsigned int pciSubSystemId; //!< The 32-bit Sub System Device ID
// NVIDIA reserved for internal use only
unsigned int reserved0;
unsigned int reserved1;
unsigned int reserved2;
unsigned int reserved3;
} nvmlPciInfo_t;
/**
* Detailed ECC error counts for a device.
*
* @deprecated Different GPU families can have different memory error counters
* See \ref nvmlDeviceGetMemoryErrorCounter
*/
typedef struct nvmlEccErrorCounts_st
{
unsigned long long l1Cache; //!< L1 cache errors
unsigned long long l2Cache; //!< L2 cache errors
unsigned long long deviceMemory; //!< Device memory errors
unsigned long long registerFile; //!< Register file errors
} nvmlEccErrorCounts_t;
/**
* Utilization information for a device.
* Each sample period may be between 1 second and 1/6 second, depending on the product being queried.
*/
typedef struct nvmlUtilization_st
{
unsigned int gpu; //!< Percent of time over the past sample period during which one or more kernels was executing on the GPU
unsigned int memory; //!< Percent of time over the past sample period during which global (device) memory was being read or written
} nvmlUtilization_t;
/**
* Memory allocation information for a device.
*/
typedef struct nvmlMemory_st
{
unsigned long long total; //!< Total installed FB memory (in bytes)
unsigned long long free; //!< Unallocated FB memory (in bytes)
unsigned long long used; //!< Allocated FB memory (in bytes). Note that the driver/GPU always sets aside a small amount of memory for bookkeeping
} nvmlMemory_t;
/**
* BAR1 Memory allocation Information for a device
*/
typedef struct nvmlBAR1Memory_st
{
unsigned long long bar1Total; //!< Total BAR1 Memory (in bytes)
unsigned long long bar1Free; //!< Unallocated BAR1 Memory (in bytes)
unsigned long long bar1Used; //!< Allocated Used Memory (in bytes)
}nvmlBAR1Memory_t;
/**
* Information about running compute processes on the GPU
*/
typedef struct nvmlProcessInfo_st
{
unsigned int pid; //!< Process ID
unsigned long long usedGpuMemory; //!< Amount of used GPU memory in bytes.
//! Under WDDM, \ref NVML_VALUE_NOT_AVAILABLE is always reported
//! because Windows KMD manages all the memory and not the NVIDIA driver
} nvmlProcessInfo_t;
/**
* Enum to represent type of bridge chip
*/
typedef enum nvmlBridgeChipType_enum
{
NVML_BRIDGE_CHIP_PLX = 0,
NVML_BRIDGE_CHIP_BRO4 = 1
}nvmlBridgeChipType_t;
/**
* Maximum number of NvLink links supported
*/
#define NVML_NVLINK_MAX_LINKS 6
/**
* Enum to represent the NvLink utilization counter packet units
*/
typedef enum nvmlNvLinkUtilizationCountUnits_enum
{
NVML_NVLINK_COUNTER_UNIT_CYCLES = 0, // count by cycles
NVML_NVLINK_COUNTER_UNIT_PACKETS = 1, // count by packets
NVML_NVLINK_COUNTER_UNIT_BYTES = 2, // count by bytes
// this must be last
NVML_NVLINK_COUNTER_UNIT_COUNT
} nvmlNvLinkUtilizationCountUnits_t;
/**
* Enum to represent the NvLink utilization counter packet types to count
* ** this is ONLY applicable with the units as packets or bytes
* ** as specified in \a nvmlNvLinkUtilizationCountUnits_t
* ** all packet filter descriptions are target GPU centric
* ** these can be "OR'd" together
*/
typedef enum nvmlNvLinkUtilizationCountPktTypes_enum
{
NVML_NVLINK_COUNTER_PKTFILTER_NOP = 0x1, // no operation packets
NVML_NVLINK_COUNTER_PKTFILTER_READ = 0x2, // read packets
NVML_NVLINK_COUNTER_PKTFILTER_WRITE = 0x4, // write packets
NVML_NVLINK_COUNTER_PKTFILTER_RATOM = 0x8, // reduction atomic requests
NVML_NVLINK_COUNTER_PKTFILTER_NRATOM = 0x10, // non-reduction atomic requests
NVML_NVLINK_COUNTER_PKTFILTER_FLUSH = 0x20, // flush requests
NVML_NVLINK_COUNTER_PKTFILTER_RESPDATA = 0x40, // responses with data
NVML_NVLINK_COUNTER_PKTFILTER_RESPNODATA = 0x80, // responses without data
NVML_NVLINK_COUNTER_PKTFILTER_ALL = 0xFF // all packets
} nvmlNvLinkUtilizationCountPktTypes_t;
/**
* Struct to define the NVLINK counter controls
*/
typedef struct nvmlNvLinkUtilizationControl_st
{
nvmlNvLinkUtilizationCountUnits_t units;
nvmlNvLinkUtilizationCountPktTypes_t pktfilter;
} nvmlNvLinkUtilizationControl_t;
/**
* Enum to represent NvLink queryable capabilities
*/
typedef enum nvmlNvLinkCapability_enum
{
NVML_NVLINK_CAP_P2P_SUPPORTED = 0, // P2P over NVLink is supported
NVML_NVLINK_CAP_SYSMEM_ACCESS = 1, // Access to system memory is supported
NVML_NVLINK_CAP_P2P_ATOMICS = 2, // P2P atomics are supported
NVML_NVLINK_CAP_SYSMEM_ATOMICS= 3, // System memory atomics are supported
NVML_NVLINK_CAP_SLI_BRIDGE = 4, // SLI is supported over this link
NVML_NVLINK_CAP_VALID = 5, // Link is supported on this device
// should be last
NVML_NVLINK_CAP_COUNT
} nvmlNvLinkCapability_t;
/**
* Enum to represent NvLink queryable error counters
*/
typedef enum nvmlNvLinkErrorCounter_enum
{
NVML_NVLINK_ERROR_DL_REPLAY = 0, // Data link transmit replay error counter
NVML_NVLINK_ERROR_DL_RECOVERY = 1, // Data link transmit recovery error counter
NVML_NVLINK_ERROR_DL_CRC_FLIT = 2, // Data link receive flow control digit CRC error counter
NVML_NVLINK_ERROR_DL_CRC_DATA = 3, // Data link receive data CRC error counter
// this must be last
NVML_NVLINK_ERROR_COUNT
} nvmlNvLinkErrorCounter_t;
/**
* Represents level relationships within a system between two GPUs
* The enums are spaced to allow for future relationships
*/
typedef enum nvmlGpuLevel_enum
{
NVML_TOPOLOGY_INTERNAL = 0, // e.g. Tesla K80
NVML_TOPOLOGY_SINGLE = 10, // all devices that only need traverse a single PCIe switch
NVML_TOPOLOGY_MULTIPLE = 20, // all devices that need not traverse a host bridge
NVML_TOPOLOGY_HOSTBRIDGE = 30, // all devices that are connected to the same host bridge
NVML_TOPOLOGY_CPU = 40, // all devices that are connected to the same CPU but possibly multiple host bridges
NVML_TOPOLOGY_SYSTEM = 50, // all devices in the system
// there is purposefully no COUNT here because of the need for spacing above
} nvmlGpuTopologyLevel_t;
/* P2P Capability Index Status*/
typedef enum nvmlGpuP2PStatus_enum
{
NVML_P2P_STATUS_OK = 0,
NVML_P2P_STATUS_CHIPSET_NOT_SUPPORED,
NVML_P2P_STATUS_GPU_NOT_SUPPORTED,
NVML_P2P_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED,
NVML_P2P_STATUS_DISABLED_BY_REGKEY,
NVML_P2P_STATUS_NOT_SUPPORTED,
NVML_P2P_STATUS_UNKNOWN
} nvmlGpuP2PStatus_t;
/* P2P Capability Index*/
typedef enum nvmlGpuP2PCapsIndex_enum
{
NVML_P2P_CAPS_INDEX_READ = 0,
NVML_P2P_CAPS_INDEX_WRITE,
NVML_P2P_CAPS_INDEX_NVLINK,
NVML_P2P_CAPS_INDEX_ATOMICS,
NVML_P2P_CAPS_INDEX_PROP,
NVML_P2P_CAPS_INDEX_UNKNOWN
}nvmlGpuP2PCapsIndex_t;
/**
* Maximum limit on Physical Bridges per Board
*/
#define NVML_MAX_PHYSICAL_BRIDGE (128)
/**
* Information about the Bridge Chip Firmware
*/
typedef struct nvmlBridgeChipInfo_st
{
nvmlBridgeChipType_t type; //!< Type of Bridge Chip
unsigned int fwVersion; //!< Firmware Version. 0=Version is unavailable
}nvmlBridgeChipInfo_t;
/**
* This structure stores the complete Hierarchy of the Bridge Chip within the board. The immediate
* bridge is stored at index 0 of bridgeInfoList, parent to immediate bridge is at index 1 and so forth.
*/
typedef struct nvmlBridgeChipHierarchy_st
{
unsigned char bridgeCount; //!< Number of Bridge Chips on the Board
nvmlBridgeChipInfo_t bridgeChipInfo[NVML_MAX_PHYSICAL_BRIDGE]; //!< Hierarchy of Bridge Chips on the board
}nvmlBridgeChipHierarchy_t;
/**
* Represents Type of Sampling Event
*/
typedef enum nvmlSamplingType_enum
{
NVML_TOTAL_POWER_SAMPLES = 0, //!< To represent total power drawn by GPU
NVML_GPU_UTILIZATION_SAMPLES = 1, //!< To represent percent of time during which one or more kernels was executing on the GPU
NVML_MEMORY_UTILIZATION_SAMPLES = 2, //!< To represent percent of time during which global (device) memory was being read or written
NVML_ENC_UTILIZATION_SAMPLES = 3, //!< To represent percent of time during which NVENC remains busy
NVML_DEC_UTILIZATION_SAMPLES = 4, //!< To represent percent of time during which NVDEC remains busy
NVML_PROCESSOR_CLK_SAMPLES = 5, //!< To represent processor clock samples
NVML_MEMORY_CLK_SAMPLES = 6, //!< To represent memory clock samples
// Keep this last
NVML_SAMPLINGTYPE_COUNT
}nvmlSamplingType_t;
/**
* Represents the queryable PCIe utilization counters
*/
typedef enum nvmlPcieUtilCounter_enum
{
NVML_PCIE_UTIL_TX_BYTES = 0, // 1KB granularity
NVML_PCIE_UTIL_RX_BYTES = 1, // 1KB granularity
// Keep this last
NVML_PCIE_UTIL_COUNT
} nvmlPcieUtilCounter_t;
/**
* Represents the type for sample value returned
*/
typedef enum nvmlValueType_enum
{
NVML_VALUE_TYPE_DOUBLE = 0,
NVML_VALUE_TYPE_UNSIGNED_INT = 1,
NVML_VALUE_TYPE_UNSIGNED_LONG = 2,
NVML_VALUE_TYPE_UNSIGNED_LONG_LONG = 3,
NVML_VALUE_TYPE_SIGNED_LONG_LONG = 4,
// Keep this last
NVML_VALUE_TYPE_COUNT
}nvmlValueType_t;
/**
* Union to represent different types of Value
*/
typedef union nvmlValue_st
{
double dVal; //!< If the value is double
unsigned int uiVal; //!< If the value is unsigned int
unsigned long ulVal; //!< If the value is unsigned long
unsigned long long ullVal; //!< If the value is unsigned long long
signed long long sllVal; //!< If the value is signed long long
}nvmlValue_t;
/**
* Information for Sample
*/
typedef struct nvmlSample_st
{
unsigned long long timeStamp; //!< CPU Timestamp in microseconds
nvmlValue_t sampleValue; //!< Sample Value
}nvmlSample_t;
/**
* Represents type of perf policy for which violation times can be queried
*/
typedef enum nvmlPerfPolicyType_enum
{
NVML_PERF_POLICY_POWER = 0, //!< How long did power violations cause the GPU to be below application clocks
NVML_PERF_POLICY_THERMAL = 1, //!< How long did thermal violations cause the GPU to be below application clocks
NVML_PERF_POLICY_SYNC_BOOST = 2, //!< How long did sync boost cause the GPU to be below application clocks
NVML_PERF_POLICY_BOARD_LIMIT = 3, //!< How long did the board limit cause the GPU to be below application clocks
NVML_PERF_POLICY_LOW_UTILIZATION = 4, //!< How long did low utilization cause the GPU to be below application clocks
NVML_PERF_POLICY_RELIABILITY = 5, //!< How long did the board reliability limit cause the GPU to be below application clocks
NVML_PERF_POLICY_TOTAL_APP_CLOCKS = 10, //!< Total time the GPU was held below application clocks by any limiter (0 - 5 above)
NVML_PERF_POLICY_TOTAL_BASE_CLOCKS = 11, //!< Total time the GPU was held below base clocks
// Keep this last
NVML_PERF_POLICY_COUNT
}nvmlPerfPolicyType_t;
/**
* Struct to hold perf policy violation status data
*/
typedef struct nvmlViolationTime_st
{
unsigned long long referenceTime; //!< referenceTime represents CPU timestamp in microseconds
unsigned long long violationTime; //!< violationTime in Nanoseconds
}nvmlViolationTime_t;
/** @} */
/***************************************************************************************************/
/** @defgroup nvmlDeviceEnumvs Device Enums
* @{
*/
/***************************************************************************************************/
/**
* Generic enable/disable enum.
*/
typedef enum nvmlEnableState_enum
{
NVML_FEATURE_DISABLED = 0, //!< Feature disabled
NVML_FEATURE_ENABLED = 1 //!< Feature enabled
} nvmlEnableState_t;
//! Generic flag used to specify the default behavior of some functions. See description of particular functions for details.
#define nvmlFlagDefault 0x00
//! Generic flag used to force some behavior. See description of particular functions for details.
#define nvmlFlagForce 0x01
/**
* * The Brand of the GPU
* */
typedef enum nvmlBrandType_enum
{
NVML_BRAND_UNKNOWN = 0,
NVML_BRAND_QUADRO = 1,
NVML_BRAND_TESLA = 2,
NVML_BRAND_NVS = 3,
NVML_BRAND_GRID = 4,
NVML_BRAND_GEFORCE = 5,
// Keep this last
NVML_BRAND_COUNT
} nvmlBrandType_t;
/**
* Temperature thresholds.
*/
typedef enum nvmlTemperatureThresholds_enum
{
NVML_TEMPERATURE_THRESHOLD_SHUTDOWN = 0, // Temperature at which the GPU will shut down
// for HW protection
NVML_TEMPERATURE_THRESHOLD_SLOWDOWN = 1, // Temperature at which the GPU will begin slowdown
// Keep this last
NVML_TEMPERATURE_THRESHOLD_COUNT
} nvmlTemperatureThresholds_t;
/**
* Temperature sensors.
*/
typedef enum nvmlTemperatureSensors_enum
{
NVML_TEMPERATURE_GPU = 0, //!< Temperature sensor for the GPU die
// Keep this last
NVML_TEMPERATURE_COUNT
} nvmlTemperatureSensors_t;
/**
* Compute mode.
*
* NVML_COMPUTEMODE_EXCLUSIVE_PROCESS was added in CUDA 4.0.
* Earlier CUDA versions supported a single exclusive mode,
* which is equivalent to NVML_COMPUTEMODE_EXCLUSIVE_THREAD in CUDA 4.0 and beyond.
*/
typedef enum nvmlComputeMode_enum
{
NVML_COMPUTEMODE_DEFAULT = 0, //!< Default compute mode -- multiple contexts per device
NVML_COMPUTEMODE_EXCLUSIVE_THREAD = 1, //!< Support Removed
NVML_COMPUTEMODE_PROHIBITED = 2, //!< Compute-prohibited mode -- no contexts per device
NVML_COMPUTEMODE_EXCLUSIVE_PROCESS = 3, //!< Compute-exclusive-process mode -- only one context per device, usable from multiple threads at a time
// Keep this last
NVML_COMPUTEMODE_COUNT
} nvmlComputeMode_t;
/**
* ECC bit types.
*
* @deprecated See \ref nvmlMemoryErrorType_t for a more flexible type
*/
#define nvmlEccBitType_t nvmlMemoryErrorType_t
/**
* Single bit ECC errors
*
* @deprecated Mapped to \ref NVML_MEMORY_ERROR_TYPE_CORRECTED
*/
#define NVML_SINGLE_BIT_ECC NVML_MEMORY_ERROR_TYPE_CORRECTED
/**
* Double bit ECC errors
*
* @deprecated Mapped to \ref NVML_MEMORY_ERROR_TYPE_UNCORRECTED
*/
#define NVML_DOUBLE_BIT_ECC NVML_MEMORY_ERROR_TYPE_UNCORRECTED
/**
* Memory error types
*/
typedef enum nvmlMemoryErrorType_enum
{
/**
* A memory error that was corrected
*
* For ECC errors, these are single bit errors
* For Texture memory, these are errors fixed by resend
*/
NVML_MEMORY_ERROR_TYPE_CORRECTED = 0,
/**
* A memory error that was not corrected
*
* For ECC errors, these are double bit errors
* For Texture memory, these are errors where the resend fails
*/
NVML_MEMORY_ERROR_TYPE_UNCORRECTED = 1,
// Keep this last
NVML_MEMORY_ERROR_TYPE_COUNT //!< Count of memory error types
} nvmlMemoryErrorType_t;
/**
* ECC counter types.
*
* Note: Volatile counts are reset each time the driver loads. On Windows this is once per boot. On Linux this can be more frequent.
* On Linux the driver unloads when no active clients exist. If persistence mode is enabled or there is always a driver
* client active (e.g. X11), then Linux also sees per-boot behavior. If not, volatile counts are reset each time a compute app
* is run.
*/
typedef enum nvmlEccCounterType_enum
{
NVML_VOLATILE_ECC = 0, //!< Volatile counts are reset each time the driver loads.
NVML_AGGREGATE_ECC = 1, //!< Aggregate counts persist across reboots (i.e. for the lifetime of the device)
// Keep this last
NVML_ECC_COUNTER_TYPE_COUNT //!< Count of memory counter types
} nvmlEccCounterType_t;
/**
* Clock types.
*
* All speeds are in Mhz.
*/
typedef enum nvmlClockType_enum
{
NVML_CLOCK_GRAPHICS = 0, //!< Graphics clock domain
NVML_CLOCK_SM = 1, //!< SM clock domain
NVML_CLOCK_MEM = 2, //!< Memory clock domain
NVML_CLOCK_VIDEO = 3, //!< Video encoder/decoder clock domain
// Keep this last
NVML_CLOCK_COUNT //<! Count of clock types
} nvmlClockType_t;
/**
* Clock Ids. These are used in combination with nvmlClockType_t
* to specify a single clock value.
*/
typedef enum nvmlClockId_enum
{
NVML_CLOCK_ID_CURRENT = 0, //!< Current actual clock value
NVML_CLOCK_ID_APP_CLOCK_TARGET = 1, //!< Target application clock
NVML_CLOCK_ID_APP_CLOCK_DEFAULT = 2, //!< Default application clock target
NVML_CLOCK_ID_CUSTOMER_BOOST_MAX = 3, //!< OEM-defined maximum clock rate
//Keep this last
NVML_CLOCK_ID_COUNT //<! Count of Clock Ids.
} nvmlClockId_t;
/**
* Driver models.
*
* Windows only.
*/
typedef enum nvmlDriverModel_enum
{
NVML_DRIVER_WDDM = 0, //!< WDDM driver model -- GPU treated as a display device
NVML_DRIVER_WDM = 1 //!< WDM (TCC) model (recommended) -- GPU treated as a generic device
} nvmlDriverModel_t;
/**
* Allowed PStates.
*/
typedef enum nvmlPStates_enum
{
NVML_PSTATE_0 = 0, //!< Performance state 0 -- Maximum Performance
NVML_PSTATE_1 = 1, //!< Performance state 1
NVML_PSTATE_2 = 2, //!< Performance state 2
NVML_PSTATE_3 = 3, //!< Performance state 3
NVML_PSTATE_4 = 4, //!< Performance state 4
NVML_PSTATE_5 = 5, //!< Performance state 5
NVML_PSTATE_6 = 6, //!< Performance state 6
NVML_PSTATE_7 = 7, //!< Performance state 7
NVML_PSTATE_8 = 8, //!< Performance state 8
NVML_PSTATE_9 = 9, //!< Performance state 9
NVML_PSTATE_10 = 10, //!< Performance state 10
NVML_PSTATE_11 = 11, //!< Performance state 11
NVML_PSTATE_12 = 12, //!< Performance state 12
NVML_PSTATE_13 = 13, //!< Performance state 13
NVML_PSTATE_14 = 14, //!< Performance state 14
NVML_PSTATE_15 = 15, //!< Performance state 15 -- Minimum Performance
NVML_PSTATE_UNKNOWN = 32 //!< Unknown performance state
} nvmlPstates_t;
/**
* GPU Operation Mode
*
* GOM allows to reduce power usage and optimize GPU throughput by disabling GPU features.
*
* Each GOM is designed to meet specific user needs.
*/
typedef enum nvmlGom_enum
{
NVML_GOM_ALL_ON = 0, //!< Everything is enabled and running at full speed
NVML_GOM_COMPUTE = 1, //!< Designed for running only compute tasks. Graphics operations
//!< are not allowed
NVML_GOM_LOW_DP = 2 //!< Designed for running graphics applications that don't require
//!< high bandwidth double precision
} nvmlGpuOperationMode_t;
/**
* Available infoROM objects.
*/
typedef enum nvmlInforomObject_enum
{
NVML_INFOROM_OEM = 0, //!< An object defined by OEM
NVML_INFOROM_ECC = 1, //!< The ECC object determining the level of ECC support
NVML_INFOROM_POWER = 2, //!< The power management object
// Keep this last
NVML_INFOROM_COUNT //!< This counts the number of infoROM objects the driver knows about
} nvmlInforomObject_t;
/**
* Return values for NVML API calls.
*/
typedef enum nvmlReturn_enum
{
NVML_SUCCESS = 0, //!< The operation was successful
NVML_ERROR_UNINITIALIZED = 1, //!< NVML was not first initialized with nvmlInit()
NVML_ERROR_INVALID_ARGUMENT = 2, //!< A supplied argument is invalid
NVML_ERROR_NOT_SUPPORTED = 3, //!< The requested operation is not available on target device
NVML_ERROR_NO_PERMISSION = 4, //!< The current user does not have permission for operation
NVML_ERROR_ALREADY_INITIALIZED = 5, //!< Deprecated: Multiple initializations are now allowed through ref counting
NVML_ERROR_NOT_FOUND = 6, //!< A query to find an object was unsuccessful
NVML_ERROR_INSUFFICIENT_SIZE = 7, //!< An input argument is not large enough
NVML_ERROR_INSUFFICIENT_POWER = 8, //!< A device's external power cables are not properly attached
NVML_ERROR_DRIVER_NOT_LOADED = 9, //!< NVIDIA driver is not loaded
NVML_ERROR_TIMEOUT = 10, //!< User provided timeout passed
NVML_ERROR_IRQ_ISSUE = 11, //!< NVIDIA Kernel detected an interrupt issue with a GPU
NVML_ERROR_LIBRARY_NOT_FOUND = 12, //!< NVML Shared Library couldn't be found or loaded
NVML_ERROR_FUNCTION_NOT_FOUND = 13, //!< Local version of NVML doesn't implement this function
NVML_ERROR_CORRUPTED_INFOROM = 14, //!< infoROM is corrupted
NVML_ERROR_GPU_IS_LOST = 15, //!< The GPU has fallen off the bus or has otherwise become inaccessible
NVML_ERROR_RESET_REQUIRED = 16, //!< The GPU requires a reset before it can be used again
NVML_ERROR_OPERATING_SYSTEM = 17, //!< The GPU control device has been blocked by the operating system/cgroups
NVML_ERROR_LIB_RM_VERSION_MISMATCH = 18, //!< RM detects a driver/library version mismatch
NVML_ERROR_IN_USE = 19, //!< An operation cannot be performed because the GPU is currently in use
NVML_ERROR_MEMORY = 20, //!< Insufficient memory
NVML_ERROR_NO_DATA = 21, //!<No data
NVML_ERROR_VGPU_ECC_NOT_SUPPORTED = 22, //!< The requested vgpu operation is not available on target device, becasue ECC is enabled
NVML_ERROR_UNKNOWN = 999 //!< An internal driver error occurred
} nvmlReturn_t;
/**
* Memory locations
*
* See \ref nvmlDeviceGetMemoryErrorCounter
*/
typedef enum nvmlMemoryLocation_enum
{
NVML_MEMORY_LOCATION_L1_CACHE = 0, //!< GPU L1 Cache
NVML_MEMORY_LOCATION_L2_CACHE = 1, //!< GPU L2 Cache
NVML_MEMORY_LOCATION_DEVICE_MEMORY = 2, //!< GPU Device Memory
NVML_MEMORY_LOCATION_REGISTER_FILE = 3, //!< GPU Register File
NVML_MEMORY_LOCATION_TEXTURE_MEMORY = 4, //!< GPU Texture Memory
NVML_MEMORY_LOCATION_TEXTURE_SHM = 5, //!< Shared memory
NVML_MEMORY_LOCATION_CBU = 6, //!< CBU
// Keep this last
NVML_MEMORY_LOCATION_COUNT //!< This counts the number of memory locations the driver knows about
} nvmlMemoryLocation_t;
/**
* Causes for page retirement
*/
typedef enum nvmlPageRetirementCause_enum
{
NVML_PAGE_RETIREMENT_CAUSE_MULTIPLE_SINGLE_BIT_ECC_ERRORS = 0, //!< Page was retired due to multiple single bit ECC error
NVML_PAGE_RETIREMENT_CAUSE_DOUBLE_BIT_ECC_ERROR = 1, //!< Page was retired due to double bit ECC error
// Keep this last
NVML_PAGE_RETIREMENT_CAUSE_COUNT
} nvmlPageRetirementCause_t;
/**
* API types that allow changes to default permission restrictions
*/
typedef enum nvmlRestrictedAPI_enum
{
NVML_RESTRICTED_API_SET_APPLICATION_CLOCKS = 0, //!< APIs that change application clocks, see nvmlDeviceSetApplicationsClocks
//!< and see nvmlDeviceResetApplicationsClocks
NVML_RESTRICTED_API_SET_AUTO_BOOSTED_CLOCKS = 1, //!< APIs that enable/disable Auto Boosted clocks
//!< see nvmlDeviceSetAutoBoostedClocksEnabled
// Keep this last
NVML_RESTRICTED_API_COUNT
} nvmlRestrictedAPI_t;
/** @} */
/***************************************************************************************************/
/** @defgroup nvmlGridEnums GRID Enums
* @{
*/
/***************************************************************************************************/
/*!
* GPU virtualization mode types.
*/
typedef enum nvmlGpuVirtualizationMode {
NVML_GPU_VIRTUALIZATION_MODE_NONE = 0, //!< Represents Bare Metal GPU
NVML_GPU_VIRTUALIZATION_MODE_PASSTHROUGH = 1, //!< Device is associated with GPU-Passthorugh
NVML_GPU_VIRTUALIZATION_MODE_VGPU = 2, //!< Device is associated with vGPU inside virtual machine.
NVML_GPU_VIRTUALIZATION_MODE_HOST_VGPU = 3, //!< Device is associated with VGX hypervisor in vGPU mode
NVML_GPU_VIRTUALIZATION_MODE_HOST_VSGA = 4, //!< Device is associated with VGX hypervisor in vSGA mode
} nvmlGpuVirtualizationMode_t;
/** @} */
/***************************************************************************************************/
/** @defgroup nvmlFieldValueEnums Field Value Enums
* @{
*/
/***************************************************************************************************/
/**
* Field Identifiers.
*
* All Identifiers pertain to a device. Each ID is only used once and is guaranteed never to change.
*/
#define NVML_FI_DEV_ECC_CURRENT 1 //!< Current ECC mode. 1=Active. 0=Inactive
#define NVML_FI_DEV_ECC_PENDING 2 //!< Pending ECC mode. 1=Active. 0=Inactive
/* ECC Count Totals */
#define NVML_FI_DEV_ECC_SBE_VOL_TOTAL 3 //!< Total single bit volatile ECC errors
#define NVML_FI_DEV_ECC_DBE_VOL_TOTAL 4 //!< Total double bit volatile ECC errors
#define NVML_FI_DEV_ECC_SBE_AGG_TOTAL 5 //!< Total single bit aggregate (persistent) ECC errors
#define NVML_FI_DEV_ECC_DBE_AGG_TOTAL 6 //!< Total double bit aggregate (persistent) ECC errors
/* Individual ECC locations */
#define NVML_FI_DEV_ECC_SBE_VOL_L1 7 //!< L1 cache single bit volatile ECC errors
#define NVML_FI_DEV_ECC_DBE_VOL_L1 8 //!< L1 cache double bit volatile ECC errors
#define NVML_FI_DEV_ECC_SBE_VOL_L2 9 //!< L2 cache single bit volatile ECC errors
#define NVML_FI_DEV_ECC_DBE_VOL_L2 10 //!< L2 cache double bit volatile ECC errors
#define NVML_FI_DEV_ECC_SBE_VOL_DEV 11 //!< Device memory single bit volatile ECC errors
#define NVML_FI_DEV_ECC_DBE_VOL_DEV 12 //!< Device memory double bit volatile ECC errors
#define NVML_FI_DEV_ECC_SBE_VOL_REG 13 //!< Register file single bit volatile ECC errors
#define NVML_FI_DEV_ECC_DBE_VOL_REG 14 //!< Register file double bit volatile ECC errors
#define NVML_FI_DEV_ECC_SBE_VOL_TEX 15 //!< Texture memory single bit volatile ECC errors
#define NVML_FI_DEV_ECC_DBE_VOL_TEX 16 //!< Texture memory double bit volatile ECC errors
#define NVML_FI_DEV_ECC_DBE_VOL_CBU 17 //!< CBU double bit volatile ECC errors
#define NVML_FI_DEV_ECC_SBE_AGG_L1 18 //!< L1 cache single bit aggregate (persistent) ECC errors
#define NVML_FI_DEV_ECC_DBE_AGG_L1 19 //!< L1 cache double bit aggregate (persistent) ECC errors
#define NVML_FI_DEV_ECC_SBE_AGG_L2 20 //!< L2 cache single bit aggregate (persistent) ECC errors
#define NVML_FI_DEV_ECC_DBE_AGG_L2 21 //!< L2 cache double bit aggregate (persistent) ECC errors
#define NVML_FI_DEV_ECC_SBE_AGG_DEV 22 //!< Device memory single bit aggregate (persistent) ECC errors
#define NVML_FI_DEV_ECC_DBE_AGG_DEV 23 //!< Device memory double bit aggregate (persistent) ECC errors
#define NVML_FI_DEV_ECC_SBE_AGG_REG 24 //!< Register File single bit aggregate (persistent) ECC errors
#define NVML_FI_DEV_ECC_DBE_AGG_REG 25 //!< Register File double bit aggregate (persistent) ECC errors
#define NVML_FI_DEV_ECC_SBE_AGG_TEX 26 //!< Texture memory single bit aggregate (persistent) ECC errors
#define NVML_FI_DEV_ECC_DBE_AGG_TEX 27 //!< Texture memory double bit aggregate (persistent) ECC errors
#define NVML_FI_DEV_ECC_DBE_AGG_CBU 28 //!< CBU double bit aggregate ECC errors
/* Page Retirement */
#define NVML_FI_DEV_RETIRED_SBE 29 //!< Number of retired pages because of single bit errors
#define NVML_FI_DEV_RETIRED_DBE 30 //!< Number of retired pages because of double bit errors
#define NVML_FI_DEV_RETIRED_PENDING 31 //!< If any pages are pending retirement. 1=yes. 0=no.
/* NvLink Flit Error Counters */
#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L0 32 //!< NVLink flow control CRC Error Counter for Lane 0
#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L1 33 //!< NVLink flow control CRC Error Counter for Lane 1
#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L2 34 //!< NVLink flow control CRC Error Counter for Lane 2
#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L3 35 //!< NVLink flow control CRC Error Counter for Lane 3
#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L4 36 //!< NVLink flow control CRC Error Counter for Lane 4
#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L5 37 //!< NVLink flow control CRC Error Counter for Lane 5
#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_TOTAL 38 //!< NVLink flow control CRC Error Counter total for all Lanes
/* NvLink CRC Data Error Counters */
#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L0 39 //!< NVLink data CRC Error Counter for Lane 0
#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L1 40 //!< NVLink data CRC Error Counter for Lane 1
#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L2 41 //!< NVLink data CRC Error Counter for Lane 2
#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L3 42 //!< NVLink data CRC Error Counter for Lane 3
#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L4 43 //!< NVLink data CRC Error Counter for Lane 4
#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L5 44 //!< NVLink data CRC Error Counter for Lane 5
#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_TOTAL 45 //!< NvLink data CRC Error Counter total for all Lanes
/* NvLink Replay Error Counters */
#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L0 46 //!< NVLink Replay Error Counter for Lane 0
#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L1 47 //!< NVLink Replay Error Counter for Lane 1
#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L2 48 //!< NVLink Replay Error Counter for Lane 2
#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L3 49 //!< NVLink Replay Error Counter for Lane 3
#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L4 50 //!< NVLink Replay Error Counter for Lane 4
#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L5 51 //!< NVLink Replay Error Counter for Lane 5
#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_TOTAL 52 //!< NVLink Replay Error Counter total for all Lanes
/* NvLink Recovery Error Counters */
#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L0 53 //!< NVLink Recovery Error Counter for Lane 0
#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L1 54 //!< NVLink Recovery Error Counter for Lane 1
#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L2 55 //!< NVLink Recovery Error Counter for Lane 2
#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L3 56 //!< NVLink Recovery Error Counter for Lane 3
#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L4 57 //!< NVLink Recovery Error Counter for Lane 4
#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L5 58 //!< NVLink Recovery Error Counter for Lane 5
#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_TOTAL 59 //!< NVLink Recovery Error Counter total for all Lanes
/* NvLink Bandwidth Counters */
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L0 60 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 0
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L1 61 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 1
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L2 62 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 2
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L3 63 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 3
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L4 64 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 4
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L5 65 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 5
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_TOTAL 66 //!< NVLink Bandwidth Counter Total for Counter Set 0, All Lanes
/* NvLink Bandwidth Counters */
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L0 67 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 0
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L1 68 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 1
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L2 69 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 2
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L3 70 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 3
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L4 71 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 4
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L5 72 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 5
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_TOTAL 73 //!< NVLink Bandwidth Counter Total for Counter Set 1, All Lanes
/* NVML Perf Policy Counters */
#define NVML_FI_DEV_PERF_POLICY_POWER 74 //!< Perf Policy Counter for Power Policy
#define NVML_FI_DEV_PERF_POLICY_THERMAL 75 //!< Perf Policy Counter for Thermal Policy
#define NVML_FI_DEV_PERF_POLICY_SYNC_BOOST 76 //!< Perf Policy Counter for Sync boost Policy
#define NVML_FI_DEV_PERF_POLICY_BOARD_LIMIT 77 //!< Perf Policy Counter for Board Limit
#define NVML_FI_DEV_PERF_POLICY_LOW_UTILIZATION 78 //!< Perf Policy Counter for Low GPU Utilization Policy
#define NVML_FI_DEV_PERF_POLICY_RELIABILITY 79 //!< Perf Policy Counter for Reliability Policy
#define NVML_FI_DEV_PERF_POLICY_TOTAL_APP_CLOCKS 80 //!< Perf Policy Counter for Total App Clock Policy
#define NVML_FI_DEV_PERF_POLICY_TOTAL_BASE_CLOCKS 81 //!< Perf Policy Counter for Total Base Clocks Policy
/* Memory temperatures */
#define NVML_FI_DEV_MEMORY_TEMP 82 //!< Memory temperature for the device
#define NVML_FI_MAX 83 //!< One greater than the largest field ID defined above
/**
* Information for a Field Value Sample
*/
typedef struct nvmlFieldValue_st
{
unsigned int fieldId; //!< ID of the NVML field to retrieve. This must be set before any call that uses this struct. See the constants starting with NVML_FI_ above.
unsigned int unused; //!< Currently unused. This should be initialized to 0 by the caller before any API call
long long timestamp; //!< CPU Timestamp of this value in microseconds since 1970
long long latencyUsec; //!< How long this field value took to update (in usec) within NVML. This may be averaged across several fields that are serviced by the same driver call.
nvmlValueType_t valueType; //!< Type of the value stored in value
nvmlReturn_t nvmlReturn; //!< Return code for retrieving this value. This must be checked before looking at value, as value is undefined if nvmlReturn != NVML_SUCCESS
nvmlValue_t value; //!< Value for this field. This is only valid if nvmlReturn == NVML_SUCCESS
} nvmlFieldValue_t;
/** @} */
/***************************************************************************************************/
/** @defgroup nvmlUnitStructs Unit Structs
* @{
*/
/***************************************************************************************************/
typedef struct nvmlUnit_st* nvmlUnit_t;
/**
* Description of HWBC entry
*/
typedef struct nvmlHwbcEntry_st
{
unsigned int hwbcId;
char firmwareVersion[32];
} nvmlHwbcEntry_t;
/**
* Fan state enum.
*/
typedef enum nvmlFanState_enum
{
NVML_FAN_NORMAL = 0, //!< Fan is working properly
NVML_FAN_FAILED = 1 //!< Fan has failed
} nvmlFanState_t;
/**
* Led color enum.
*/
typedef enum nvmlLedColor_enum
{
NVML_LED_COLOR_GREEN = 0, //!< GREEN, indicates good health
NVML_LED_COLOR_AMBER = 1 //!< AMBER, indicates problem
} nvmlLedColor_t;
/**
* LED states for an S-class unit.
*/
typedef struct nvmlLedState_st
{
char cause[256]; //!< If amber, a text description of the cause
nvmlLedColor_t color; //!< GREEN or AMBER
} nvmlLedState_t;
/**
* Static S-class unit info.
*/
typedef struct nvmlUnitInfo_st
{
char name[96]; //!< Product name
char id[96]; //!< Product identifier
char serial[96]; //!< Product serial number
char firmwareVersion[96]; //!< Firmware version
} nvmlUnitInfo_t;
/**
* Power usage information for an S-class unit.
* The power supply state is a human readable string that equals "Normal" or contains
* a combination of "Abnormal" plus one or more of the following:
*
* - High voltage
* - Fan failure
* - Heatsink temperature
* - Current limit
* - Voltage below UV alarm threshold
* - Low-voltage
* - SI2C remote off command
* - MOD_DISABLE input
* - Short pin transition
*/
typedef struct nvmlPSUInfo_st
{
char state[256]; //!< The power supply state
unsigned int current; //!< PSU current (A)
unsigned int voltage; //!< PSU voltage (V)
unsigned int power; //!< PSU power draw (W)
} nvmlPSUInfo_t;
/**
* Fan speed reading for a single fan in an S-class unit.
*/
typedef struct nvmlUnitFanInfo_st
{
unsigned int speed; //!< Fan speed (RPM)
nvmlFanState_t state; //!< Flag that indicates whether fan is working properly