README.md

Selected circuits

• Circuit: 12-bit signed multiplier
• Selection criteria: pareto optimal sub-set wrt. pwr and wce parameters

Parameters of selected circuits

Circuit name	MAE%	WCE%	EP%	MRE%	MSE	Download
mul12s_2KL	0.00	0.00	0.00	0.00	0	[Verilog] [VerilogPDK45] [C]
mul12s_2KM	0.0000012	0.000006	25.00	0.00047	0.2	[Verilog] [VerilogPDK45] [C]
mul12s_2KN	0.0000072	0.00003	50.00	0.0023	3.8	[Verilog] [VerilogPDK45] [C]
mul12s_2KQ	0.000073	0.00029	81.25	0.021	248	[Verilog] [VerilogPDK45] [C]
mul12s_2K5	0.0031	0.013	90.61	0.25	700070	[Verilog] [VerilogPDK45] [C]
mul12s_2JL	0.0092	0.037	92.17	0.65	48939.302e2	[Verilog] [VerilogPDK45] [C]
mul12s_36A	0.032	0.17	98.39	2.64	48933.638e3	[Verilog] [VerilogPDK45] [C]
mul12s_2NM	0.19	0.77	98.41	12.72	18643.684e5	[Verilog] [VerilogPDK45] [C]

Parameters

References

• V. Mrazek, Z. Vasicek, L. Sekanina, H. Jiang and J. Han, "Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 11, pp. 2572-2576, Nov. 2018. doi: 10.1109/TVLSI.2018.2856362