- Circuit: 8x4-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and mse parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x4u_2UU | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x4u_3XB | 0.012 | 0.049 | 37.50 | 0.33 | 0.75 | [Verilog] [C] |
| mul8x4u_485 | 0.039 | 0.15 | 60.79 | 0.90 | 5.3 | [Verilog] [C] |
| mul8x4u_4ND | 0.11 | 0.44 | 79.39 | 2.56 | 38 | [Verilog] [C] |
| mul8x4u_30N | 0.27 | 1.00 | 86.43 | 5.37 | 209 | [Verilog] [C] |
| mul8x4u_3Y3 | 0.66 | 2.17 | 91.16 | 10.34 | 1164 | [Verilog] [C] |
| mul8x4u_1RU | 1.71 | 6.67 | 92.65 | 22.99 | 7822 | [Verilog] [C] |
| mul8x4u_4Z7 | 3.97 | 18.63 | 93.09 | 39.63 | 43327 | [Verilog] [C] |
| mul8x4u_134 | 9.08 | 34.11 | 93.33 | 67.10 | 230371 | [Verilog] [C] |
| mul8x4u_555 | 23.35 | 93.38 | 93.38 | 100.00 | 16831.062e2 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020