diff --git a/data/chips/STM32G431C6.json b/data/chips/STM32G431C6.json index d6ce40684c..cc8749d990 100644 --- a/data/chips/STM32G431C6.json +++ b/data/chips/STM32G431C6.json @@ -1057,7 +1057,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G431C8.json b/data/chips/STM32G431C8.json index ff0e4b891d..ac517509c2 100644 --- a/data/chips/STM32G431C8.json +++ b/data/chips/STM32G431C8.json @@ -1057,7 +1057,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G431CB.json b/data/chips/STM32G431CB.json index fcebfc1ca6..6b89af6e8e 100644 --- a/data/chips/STM32G431CB.json +++ b/data/chips/STM32G431CB.json @@ -1061,7 +1061,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G431K6.json b/data/chips/STM32G431K6.json index 1b984cdfad..f198ca6701 100644 --- a/data/chips/STM32G431K6.json +++ b/data/chips/STM32G431K6.json @@ -992,7 +992,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G431K8.json b/data/chips/STM32G431K8.json index b4602f0b83..b1930ddf52 100644 --- a/data/chips/STM32G431K8.json +++ b/data/chips/STM32G431K8.json @@ -992,7 +992,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G431KB.json b/data/chips/STM32G431KB.json index 9f75814200..bc67b26676 100644 --- a/data/chips/STM32G431KB.json +++ b/data/chips/STM32G431KB.json @@ -992,7 +992,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G431M6.json b/data/chips/STM32G431M6.json index f695ea0bc5..8d4775d375 100644 --- a/data/chips/STM32G431M6.json +++ b/data/chips/STM32G431M6.json @@ -1120,7 +1120,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G431M8.json b/data/chips/STM32G431M8.json index 2f7ae3584c..6b52d4c2d1 100644 --- a/data/chips/STM32G431M8.json +++ b/data/chips/STM32G431M8.json @@ -1120,7 +1120,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G431MB.json b/data/chips/STM32G431MB.json index eee7b0355e..b1c77864fa 100644 --- a/data/chips/STM32G431MB.json +++ b/data/chips/STM32G431MB.json @@ -1120,7 +1120,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G431R6.json b/data/chips/STM32G431R6.json index d71d190d12..7217244c46 100644 --- a/data/chips/STM32G431R6.json +++ b/data/chips/STM32G431R6.json @@ -1106,7 +1106,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G431R8.json b/data/chips/STM32G431R8.json index e77cb3ca60..e0f78d9995 100644 --- a/data/chips/STM32G431R8.json +++ b/data/chips/STM32G431R8.json @@ -1106,7 +1106,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G431RB.json b/data/chips/STM32G431RB.json index 52cda2ee38..c402b7c8d1 100644 --- a/data/chips/STM32G431RB.json +++ b/data/chips/STM32G431RB.json @@ -1106,7 +1106,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G431V6.json b/data/chips/STM32G431V6.json index 186db53d66..a6b5e479e2 100644 --- a/data/chips/STM32G431V6.json +++ b/data/chips/STM32G431V6.json @@ -1120,7 +1120,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G431V8.json b/data/chips/STM32G431V8.json index ec5218ad18..93bcb8a8f4 100644 --- a/data/chips/STM32G431V8.json +++ b/data/chips/STM32G431V8.json @@ -1120,7 +1120,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G431VB.json b/data/chips/STM32G431VB.json index 528561efdd..e46d9470c6 100644 --- a/data/chips/STM32G431VB.json +++ b/data/chips/STM32G431VB.json @@ -1120,7 +1120,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G441CB.json b/data/chips/STM32G441CB.json index 2c34911a2b..56e857dc4d 100644 --- a/data/chips/STM32G441CB.json +++ b/data/chips/STM32G441CB.json @@ -1094,7 +1094,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G441KB.json b/data/chips/STM32G441KB.json index 35d4f76828..a42ce0b92f 100644 --- a/data/chips/STM32G441KB.json +++ b/data/chips/STM32G441KB.json @@ -1025,7 +1025,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G441MB.json b/data/chips/STM32G441MB.json index 09494d7d08..56c1bafbfa 100644 --- a/data/chips/STM32G441MB.json +++ b/data/chips/STM32G441MB.json @@ -1153,7 +1153,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G441RB.json b/data/chips/STM32G441RB.json index 171c61ec66..dbb101dab5 100644 --- a/data/chips/STM32G441RB.json +++ b/data/chips/STM32G441RB.json @@ -1139,7 +1139,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G441VB.json b/data/chips/STM32G441VB.json index e2153e4d28..cb3656e160 100644 --- a/data/chips/STM32G441VB.json +++ b/data/chips/STM32G441VB.json @@ -1153,7 +1153,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c2", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G471CC.json b/data/chips/STM32G471CC.json index a45fb14e43..176fda10c6 100644 --- a/data/chips/STM32G471CC.json +++ b/data/chips/STM32G471CC.json @@ -984,7 +984,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G471CE.json b/data/chips/STM32G471CE.json index 3e3e8c7c27..ee0757fc23 100644 --- a/data/chips/STM32G471CE.json +++ b/data/chips/STM32G471CE.json @@ -984,7 +984,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G471MC.json b/data/chips/STM32G471MC.json index 89f942be12..ad0718a71d 100644 --- a/data/chips/STM32G471MC.json +++ b/data/chips/STM32G471MC.json @@ -1083,7 +1083,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G471ME.json b/data/chips/STM32G471ME.json index 33a01878d9..5a37b59ed5 100644 --- a/data/chips/STM32G471ME.json +++ b/data/chips/STM32G471ME.json @@ -1087,7 +1087,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G471QC.json b/data/chips/STM32G471QC.json index 62cf7df74f..8a77141db1 100644 --- a/data/chips/STM32G471QC.json +++ b/data/chips/STM32G471QC.json @@ -1100,7 +1100,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G471QE.json b/data/chips/STM32G471QE.json index 309bb5074b..b7884400c3 100644 --- a/data/chips/STM32G471QE.json +++ b/data/chips/STM32G471QE.json @@ -1100,7 +1100,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G471RC.json b/data/chips/STM32G471RC.json index c3b56134f3..1c5b7e5715 100644 --- a/data/chips/STM32G471RC.json +++ b/data/chips/STM32G471RC.json @@ -1029,7 +1029,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G471RE.json b/data/chips/STM32G471RE.json index 7a5323d117..0666314fd9 100644 --- a/data/chips/STM32G471RE.json +++ b/data/chips/STM32G471RE.json @@ -1029,7 +1029,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G471VC.json b/data/chips/STM32G471VC.json index 965f9c21e4..22bce855b4 100644 --- a/data/chips/STM32G471VC.json +++ b/data/chips/STM32G471VC.json @@ -1103,7 +1103,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G471VE.json b/data/chips/STM32G471VE.json index 168e698e59..8a3b4321e1 100644 --- a/data/chips/STM32G471VE.json +++ b/data/chips/STM32G471VE.json @@ -1103,7 +1103,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473CB.json b/data/chips/STM32G473CB.json index bb7d6209bf..fdb2fd1101 100644 --- a/data/chips/STM32G473CB.json +++ b/data/chips/STM32G473CB.json @@ -1520,7 +1520,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473CC.json b/data/chips/STM32G473CC.json index 00b00ea8c3..2869f163a8 100644 --- a/data/chips/STM32G473CC.json +++ b/data/chips/STM32G473CC.json @@ -1520,7 +1520,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473CE.json b/data/chips/STM32G473CE.json index 06daf68e90..aa48016221 100644 --- a/data/chips/STM32G473CE.json +++ b/data/chips/STM32G473CE.json @@ -1520,7 +1520,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473MB.json b/data/chips/STM32G473MB.json index 6e5ada96a9..bf3f6f426b 100644 --- a/data/chips/STM32G473MB.json +++ b/data/chips/STM32G473MB.json @@ -1709,7 +1709,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473MC.json b/data/chips/STM32G473MC.json index 5bd3a07595..5139688296 100644 --- a/data/chips/STM32G473MC.json +++ b/data/chips/STM32G473MC.json @@ -1709,7 +1709,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473ME.json b/data/chips/STM32G473ME.json index 899d10fd87..0471469f75 100644 --- a/data/chips/STM32G473ME.json +++ b/data/chips/STM32G473ME.json @@ -1713,7 +1713,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473PB.json b/data/chips/STM32G473PB.json index d0914378e6..b4935d214c 100644 --- a/data/chips/STM32G473PB.json +++ b/data/chips/STM32G473PB.json @@ -1760,7 +1760,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473PC.json b/data/chips/STM32G473PC.json index aac104ea49..d555957a1e 100644 --- a/data/chips/STM32G473PC.json +++ b/data/chips/STM32G473PC.json @@ -1760,7 +1760,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473PE.json b/data/chips/STM32G473PE.json index 531b91cab8..46cc21f182 100644 --- a/data/chips/STM32G473PE.json +++ b/data/chips/STM32G473PE.json @@ -1760,7 +1760,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473QB.json b/data/chips/STM32G473QB.json index 206b4b5be4..069fd18fe3 100644 --- a/data/chips/STM32G473QB.json +++ b/data/chips/STM32G473QB.json @@ -1766,7 +1766,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473QC.json b/data/chips/STM32G473QC.json index 94cfa6b168..80cedcd66b 100644 --- a/data/chips/STM32G473QC.json +++ b/data/chips/STM32G473QC.json @@ -1766,7 +1766,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473QE.json b/data/chips/STM32G473QE.json index 4c2df230dd..41675fd324 100644 --- a/data/chips/STM32G473QE.json +++ b/data/chips/STM32G473QE.json @@ -1766,7 +1766,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473RB.json b/data/chips/STM32G473RB.json index 2c3f6c8b98..66b358612a 100644 --- a/data/chips/STM32G473RB.json +++ b/data/chips/STM32G473RB.json @@ -1575,7 +1575,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473RC.json b/data/chips/STM32G473RC.json index e009c55d25..323bbb7547 100644 --- a/data/chips/STM32G473RC.json +++ b/data/chips/STM32G473RC.json @@ -1575,7 +1575,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473RE.json b/data/chips/STM32G473RE.json index 5c807f411f..ec552c7135 100644 --- a/data/chips/STM32G473RE.json +++ b/data/chips/STM32G473RE.json @@ -1575,7 +1575,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473VB.json b/data/chips/STM32G473VB.json index 3db3ccc255..7c26027533 100644 --- a/data/chips/STM32G473VB.json +++ b/data/chips/STM32G473VB.json @@ -1765,7 +1765,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473VC.json b/data/chips/STM32G473VC.json index adcf234a3a..bbc6211532 100644 --- a/data/chips/STM32G473VC.json +++ b/data/chips/STM32G473VC.json @@ -1765,7 +1765,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G473VE.json b/data/chips/STM32G473VE.json index ab5a44c4be..7474028091 100644 --- a/data/chips/STM32G473VE.json +++ b/data/chips/STM32G473VE.json @@ -1765,7 +1765,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474CB.json b/data/chips/STM32G474CB.json index c2fedc1a92..a6020b22e6 100644 --- a/data/chips/STM32G474CB.json +++ b/data/chips/STM32G474CB.json @@ -1532,7 +1532,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474CC.json b/data/chips/STM32G474CC.json index b81706e317..e7dec88d0d 100644 --- a/data/chips/STM32G474CC.json +++ b/data/chips/STM32G474CC.json @@ -1532,7 +1532,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474CE.json b/data/chips/STM32G474CE.json index 82f74aa912..c869c01a7d 100644 --- a/data/chips/STM32G474CE.json +++ b/data/chips/STM32G474CE.json @@ -1532,7 +1532,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474MB.json b/data/chips/STM32G474MB.json index 93bfd987e3..e725d0b9d0 100644 --- a/data/chips/STM32G474MB.json +++ b/data/chips/STM32G474MB.json @@ -1721,7 +1721,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474MC.json b/data/chips/STM32G474MC.json index fbe6f8c946..8608285fb6 100644 --- a/data/chips/STM32G474MC.json +++ b/data/chips/STM32G474MC.json @@ -1721,7 +1721,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474ME.json b/data/chips/STM32G474ME.json index 8587d81365..4e0f73908a 100644 --- a/data/chips/STM32G474ME.json +++ b/data/chips/STM32G474ME.json @@ -1725,7 +1725,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474PB.json b/data/chips/STM32G474PB.json index 12b7da1b5e..903430c384 100644 --- a/data/chips/STM32G474PB.json +++ b/data/chips/STM32G474PB.json @@ -1760,7 +1760,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474PC.json b/data/chips/STM32G474PC.json index c609d7bf26..f851b649cf 100644 --- a/data/chips/STM32G474PC.json +++ b/data/chips/STM32G474PC.json @@ -1760,7 +1760,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474PE.json b/data/chips/STM32G474PE.json index 9372221cb9..7567e5a975 100644 --- a/data/chips/STM32G474PE.json +++ b/data/chips/STM32G474PE.json @@ -1760,7 +1760,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474QB.json b/data/chips/STM32G474QB.json index e31f5150e9..cb820fe64a 100644 --- a/data/chips/STM32G474QB.json +++ b/data/chips/STM32G474QB.json @@ -1778,7 +1778,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474QC.json b/data/chips/STM32G474QC.json index 9dc4d6d14d..aec0f3c79b 100644 --- a/data/chips/STM32G474QC.json +++ b/data/chips/STM32G474QC.json @@ -1778,7 +1778,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474QE.json b/data/chips/STM32G474QE.json index a6949634ba..ae13b6b95d 100644 --- a/data/chips/STM32G474QE.json +++ b/data/chips/STM32G474QE.json @@ -1778,7 +1778,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474RB.json b/data/chips/STM32G474RB.json index ca7e6f4a42..33ae23cdd8 100644 --- a/data/chips/STM32G474RB.json +++ b/data/chips/STM32G474RB.json @@ -1587,7 +1587,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474RC.json b/data/chips/STM32G474RC.json index 204366f099..947f99f7ac 100644 --- a/data/chips/STM32G474RC.json +++ b/data/chips/STM32G474RC.json @@ -1587,7 +1587,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474RE.json b/data/chips/STM32G474RE.json index 81730f57c0..72b4706c30 100644 --- a/data/chips/STM32G474RE.json +++ b/data/chips/STM32G474RE.json @@ -1587,7 +1587,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474VB.json b/data/chips/STM32G474VB.json index 63f560daa8..cb16274e54 100644 --- a/data/chips/STM32G474VB.json +++ b/data/chips/STM32G474VB.json @@ -1777,7 +1777,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474VC.json b/data/chips/STM32G474VC.json index a92204a390..a29cc41265 100644 --- a/data/chips/STM32G474VC.json +++ b/data/chips/STM32G474VC.json @@ -1777,7 +1777,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G474VE.json b/data/chips/STM32G474VE.json index 96c0632eba..9cd15630d5 100644 --- a/data/chips/STM32G474VE.json +++ b/data/chips/STM32G474VE.json @@ -1777,7 +1777,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G483CE.json b/data/chips/STM32G483CE.json index 1f9ab022c8..1e8a3718b3 100644 --- a/data/chips/STM32G483CE.json +++ b/data/chips/STM32G483CE.json @@ -1559,7 +1559,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G483ME.json b/data/chips/STM32G483ME.json index e019daa503..5a88abc5b5 100644 --- a/data/chips/STM32G483ME.json +++ b/data/chips/STM32G483ME.json @@ -1752,7 +1752,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G483PE.json b/data/chips/STM32G483PE.json index 550572af08..7a3b112387 100644 --- a/data/chips/STM32G483PE.json +++ b/data/chips/STM32G483PE.json @@ -1799,7 +1799,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G483QE.json b/data/chips/STM32G483QE.json index 998ed124a0..e541e7a7c4 100644 --- a/data/chips/STM32G483QE.json +++ b/data/chips/STM32G483QE.json @@ -1805,7 +1805,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G483RE.json b/data/chips/STM32G483RE.json index fae15517db..2dd844090f 100644 --- a/data/chips/STM32G483RE.json +++ b/data/chips/STM32G483RE.json @@ -1614,7 +1614,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G483VE.json b/data/chips/STM32G483VE.json index e7a79c18f0..f0a0aef8f2 100644 --- a/data/chips/STM32G483VE.json +++ b/data/chips/STM32G483VE.json @@ -1804,7 +1804,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G484CE.json b/data/chips/STM32G484CE.json index 7b098906ae..e8b2c22b84 100644 --- a/data/chips/STM32G484CE.json +++ b/data/chips/STM32G484CE.json @@ -1565,7 +1565,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G484ME.json b/data/chips/STM32G484ME.json index 255737d232..666004ea67 100644 --- a/data/chips/STM32G484ME.json +++ b/data/chips/STM32G484ME.json @@ -1758,7 +1758,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G484PE.json b/data/chips/STM32G484PE.json index 59c19a013d..c19146c298 100644 --- a/data/chips/STM32G484PE.json +++ b/data/chips/STM32G484PE.json @@ -1799,7 +1799,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G484QE.json b/data/chips/STM32G484QE.json index 82460fbf8f..3a35fff2ce 100644 --- a/data/chips/STM32G484QE.json +++ b/data/chips/STM32G484QE.json @@ -1811,7 +1811,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G484RE.json b/data/chips/STM32G484RE.json index 343ae3d357..5e37669eee 100644 --- a/data/chips/STM32G484RE.json +++ b/data/chips/STM32G484RE.json @@ -1620,7 +1620,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G484VE.json b/data/chips/STM32G484VE.json index 8330663c3d..1a5d366307 100644 --- a/data/chips/STM32G484VE.json +++ b/data/chips/STM32G484VE.json @@ -1810,7 +1810,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c3", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G491CC.json b/data/chips/STM32G491CC.json index add68e41eb..b088778eb5 100644 --- a/data/chips/STM32G491CC.json +++ b/data/chips/STM32G491CC.json @@ -1177,7 +1177,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c4", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G491CE.json b/data/chips/STM32G491CE.json index ae49647bb7..45e0f5a935 100644 --- a/data/chips/STM32G491CE.json +++ b/data/chips/STM32G491CE.json @@ -1177,7 +1177,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c4", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G491KC.json b/data/chips/STM32G491KC.json index 77a885c293..12f2d247bc 100644 --- a/data/chips/STM32G491KC.json +++ b/data/chips/STM32G491KC.json @@ -1090,7 +1090,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c4", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G491KE.json b/data/chips/STM32G491KE.json index 4a72979db5..37bf336eb9 100644 --- a/data/chips/STM32G491KE.json +++ b/data/chips/STM32G491KE.json @@ -1090,7 +1090,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c4", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G491MC.json b/data/chips/STM32G491MC.json index 0bb4a1aa13..749d512ad1 100644 --- a/data/chips/STM32G491MC.json +++ b/data/chips/STM32G491MC.json @@ -1276,7 +1276,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c4", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G491ME.json b/data/chips/STM32G491ME.json index c30acbadea..c4e39eeff4 100644 --- a/data/chips/STM32G491ME.json +++ b/data/chips/STM32G491ME.json @@ -1276,7 +1276,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c4", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G491RC.json b/data/chips/STM32G491RC.json index f9ba1c45bf..adb68e2c17 100644 --- a/data/chips/STM32G491RC.json +++ b/data/chips/STM32G491RC.json @@ -1226,7 +1226,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c4", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G491RE.json b/data/chips/STM32G491RE.json index 2eca1493b9..a3817d1915 100644 --- a/data/chips/STM32G491RE.json +++ b/data/chips/STM32G491RE.json @@ -1230,7 +1230,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c4", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G491VC.json b/data/chips/STM32G491VC.json index 824c580a74..5b52c703f3 100644 --- a/data/chips/STM32G491VC.json +++ b/data/chips/STM32G491VC.json @@ -1288,7 +1288,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c4", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G491VE.json b/data/chips/STM32G491VE.json index 62f8bf1466..696be28dd0 100644 --- a/data/chips/STM32G491VE.json +++ b/data/chips/STM32G491VE.json @@ -1288,7 +1288,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c4", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G4A1CE.json b/data/chips/STM32G4A1CE.json index b0bdf2e86b..d405a6b4f6 100644 --- a/data/chips/STM32G4A1CE.json +++ b/data/chips/STM32G4A1CE.json @@ -1216,7 +1216,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c4", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G4A1KE.json b/data/chips/STM32G4A1KE.json index 9c3dff2021..8d3f3974a3 100644 --- a/data/chips/STM32G4A1KE.json +++ b/data/chips/STM32G4A1KE.json @@ -1129,7 +1129,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c4", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G4A1ME.json b/data/chips/STM32G4A1ME.json index 1773558260..8e61d04481 100644 --- a/data/chips/STM32G4A1ME.json +++ b/data/chips/STM32G4A1ME.json @@ -1315,7 +1315,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c4", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G4A1RE.json b/data/chips/STM32G4A1RE.json index a6f4e4b14e..a92aa50a64 100644 --- a/data/chips/STM32G4A1RE.json +++ b/data/chips/STM32G4A1RE.json @@ -1269,7 +1269,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c4", "block": "FLASH" }, "rcc": { diff --git a/data/chips/STM32G4A1VE.json b/data/chips/STM32G4A1VE.json index b2e6483c2c..02793d10b4 100644 --- a/data/chips/STM32G4A1VE.json +++ b/data/chips/STM32G4A1VE.json @@ -1327,7 +1327,7 @@ "address": 1073881088, "registers": { "kind": "flash", - "version": "g4", + "version": "g4c4", "block": "FLASH" }, "rcc": { diff --git a/data/registers/flash_g4.json b/data/registers/flash_g4c2.json similarity index 100% rename from data/registers/flash_g4.json rename to data/registers/flash_g4c2.json diff --git a/data/registers/flash_g4c3.json b/data/registers/flash_g4c3.json new file mode 100644 index 0000000000..d169070b8e --- /dev/null +++ b/data/registers/flash_g4c3.json @@ -0,0 +1,634 @@ +{ + "block/FLASH": { + "description": "Flash", + "items": [ + { + "name": "ACR", + "description": "Access control register", + "byte_offset": 0, + "fieldset": "ACR" + }, + { + "name": "PDKEYR", + "description": "Power down key register", + "byte_offset": 4, + "access": "Write" + }, + { + "name": "KEYR", + "description": "Flash key register", + "byte_offset": 8, + "access": "Write" + }, + { + "name": "OPTKEYR", + "description": "Option byte key register", + "byte_offset": 12, + "access": "Write" + }, + { + "name": "SR", + "description": "Status register", + "byte_offset": 16, + "fieldset": "SR" + }, + { + "name": "CR", + "description": "Flash control register", + "byte_offset": 20, + "fieldset": "CR" + }, + { + "name": "ECCR", + "description": "Flash ECC register", + "byte_offset": 24, + "fieldset": "ECCR" + }, + { + "name": "OPTR", + "description": "Flash option register", + "byte_offset": 32, + "fieldset": "OPTR" + }, + { + "name": "PCROP1SR", + "description": "Flash Bank 1 PCROP Start address register", + "byte_offset": 36, + "fieldset": "PCROP1SR" + }, + { + "name": "PCROP1ER", + "description": "Flash Bank 1 PCROP End address register", + "byte_offset": 40, + "fieldset": "PCROP1ER" + }, + { + "name": "WRP1AR", + "description": "Flash Bank 1 WRP area A address register", + "byte_offset": 44, + "fieldset": "WRP1AR" + }, + { + "name": "WRP1BR", + "description": "Flash Bank 1 WRP area B address register", + "byte_offset": 48, + "fieldset": "WRP1BR" + }, + { + "name": "SEC1R", + "description": "securable area bank1 register", + "byte_offset": 112, + "fieldset": "SEC1R" + } + ] + }, + "fieldset/ACR": { + "description": "Access control register", + "fields": [ + { + "name": "LATENCY", + "description": "Latency", + "bit_offset": 0, + "bit_size": 4, + "enum": "LATENCY" + }, + { + "name": "PRFTEN", + "description": "Prefetch enable", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "ICEN", + "description": "Instruction cache enable", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "DCEN", + "description": "Data cache enable", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "ICRST", + "description": "Instruction cache reset", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "DCRST", + "description": "Data cache reset", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "RUN_PD", + "description": "Flash Power-down mode during Low-power run mode", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "SLEEP_PD", + "description": "Flash Power-down mode during Low-power sleep mode", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "DBG_SWEN", + "description": "Debug software enable", + "bit_offset": 18, + "bit_size": 1 + } + ] + }, + "fieldset/CR": { + "description": "Flash control register", + "fields": [ + { + "name": "PG", + "description": "Programming", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "PER", + "description": "Page erase", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "MER1", + "description": "Bank 1 Mass erase", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "PNB", + "description": "Page number", + "bit_offset": 3, + "bit_size": 7 + }, + { + "name": "MER2", + "description": "Bank 2 Mass erase", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "STRT", + "description": "Start", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "OPTSTRT", + "description": "Options modification start", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "FSTPG", + "description": "Fast programming", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "EOPIE", + "description": "End of operation interrupt enable", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "RDERRIE", + "description": "PCROP read error interrupt enable", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "OBL_LAUNCH", + "description": "Force the option byte loading", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "SEC_PROT1", + "description": "Securable memory area protection enable", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "OPTLOCK", + "description": "Options Lock", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "LOCK", + "description": "FLASH_CR Lock", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/ECCR": { + "description": "Flash ECC register", + "fields": [ + { + "name": "ADDR_ECC", + "description": "ECC fail address", + "bit_offset": 0, + "bit_size": 19 + }, + { + "name": "BK_ECC", + "description": "ECC fail for Corrected ECC Error or Double ECC Error in info block", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "SYSF_ECC", + "description": "ECC fail for Corrected ECC Error or Double ECC Error in info block", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ECCIE", + "description": "ECC correction interrupt enable", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ECCC2", + "description": "ECC correction", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ECCD2", + "description": "ECC2 detection", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "ECCC", + "description": "ECC correction", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "ECCD", + "description": "ECC detection", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/OPTR": { + "description": "Flash option register", + "fields": [ + { + "name": "RDP", + "description": "Read protection level", + "bit_offset": 0, + "bit_size": 8, + "enum": "RDP" + }, + { + "name": "BOR_LEV", + "description": "BOR reset Level", + "bit_offset": 8, + "bit_size": 3 + }, + { + "name": "nRST_STOP", + "description": "nRST_STOP", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "nRST_STDBY", + "description": "nRST_STDBY", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "nRST_SHDW", + "description": "nRST_SHDW", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "IDWG_SW", + "description": "Independent watchdog selection", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "IWDG_STOP", + "description": "Independent watchdog counter freeze in Stop mode", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "IWDG_STDBY", + "description": "Independent watchdog counter freeze in Standby mode", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "WWDG_SW", + "description": "Window watchdog selection", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "BFB2", + "description": "Dual bank boot", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "DBANK", + "description": "Dual bank memory mode", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "nBOOT1", + "description": "Boot configuration", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "SRAM2_PE", + "description": "SRAM2 parity check enable", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "SRAM2_RST", + "description": "SRAM2 Erase when system reset", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "nSWBOOT0", + "description": "nSWBOOT0", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "nBOOT0", + "description": "nBOOT0 option bit", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "NRST_MODE", + "description": "NRST_MODE", + "bit_offset": 28, + "bit_size": 2, + "enum": "NRST_MODE" + }, + { + "name": "IRHEN", + "description": "Internal reset holder enable bit", + "bit_offset": 30, + "bit_size": 1 + } + ] + }, + "fieldset/PCROP1ER": { + "description": "Flash Bank 1 PCROP End address register", + "fields": [ + { + "name": "PCROP1_END", + "description": "Bank 1 PCROP area end offset", + "bit_offset": 0, + "bit_size": 15 + }, + { + "name": "PCROP_RDP", + "description": "PCROP area preserved when RDP level decreased", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/PCROP1SR": { + "description": "Flash Bank 1 PCROP Start address register", + "fields": [ + { + "name": "PCROP1_STRT", + "description": "Bank 1 PCROP area start offset", + "bit_offset": 0, + "bit_size": 15 + } + ] + }, + "fieldset/SEC1R": { + "description": "securable area bank1 register", + "fields": [ + { + "name": "SEC_SIZE1", + "description": "SEC_SIZE1", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "BOOT_LOCK", + "description": "used to force boot from user area", + "bit_offset": 16, + "bit_size": 1 + } + ] + }, + "fieldset/SR": { + "description": "Status register", + "fields": [ + { + "name": "EOP", + "description": "End of operation", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "OPERR", + "description": "Operation error", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "PROGERR", + "description": "Programming error", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "WRPERR", + "description": "Write protected error", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PGAERR", + "description": "Programming alignment error", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "SIZERR", + "description": "Size error", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "PGSERR", + "description": "Programming sequence error", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "MISERR", + "description": "Fast programming data miss error", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FASTERR", + "description": "Fast programming error", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "RDERR", + "description": "PCROP read error", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "OPTVERR", + "description": "Option validity error", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "BSY", + "description": "Busy", + "bit_offset": 16, + "bit_size": 1 + } + ] + }, + "fieldset/WRP1AR": { + "description": "Flash Bank 1 WRP area A address register", + "fields": [ + { + "name": "WRP1A_STRT", + "description": "Bank 1 WRP first area start offset", + "bit_offset": 0, + "bit_size": 7 + }, + { + "name": "WRP1A_END", + "description": "Bank 1 WRP first area A end offset", + "bit_offset": 16, + "bit_size": 7 + } + ] + }, + "fieldset/WRP1BR": { + "description": "Flash Bank 1 WRP area B address register", + "fields": [ + { + "name": "WRP1B_STRT", + "description": "Bank 1 WRP second area B end offset", + "bit_offset": 0, + "bit_size": 7 + }, + { + "name": "WRP1B_END", + "description": "Bank 1 WRP second area B start offset", + "bit_offset": 16, + "bit_size": 7 + } + ] + }, + "enum/LATENCY": { + "bit_size": 4, + "variants": [ + { + "name": "WS0", + "description": "Zero wait states", + "value": 0 + }, + { + "name": "WS1", + "description": "One wait state", + "value": 1 + }, + { + "name": "WS2", + "description": "Two wait states", + "value": 2 + }, + { + "name": "WS3", + "description": "Three wait states", + "value": 3 + }, + { + "name": "WS4", + "description": "Four wait states", + "value": 4 + } + ] + }, + "enum/NRST_MODE": { + "bit_size": 2, + "variants": [ + { + "name": "INPUT_ONLY", + "description": "Reset pin is in reset input mode only", + "value": 1 + }, + { + "name": "GPIO", + "description": "Reset pin is in GPIO mode only", + "value": 2 + }, + { + "name": "INPUT_OUTPUT", + "description": "Reset pin is in reset input and output mode", + "value": 3 + } + ] + }, + "enum/RDP": { + "bit_size": 8, + "variants": [ + { + "name": "LEVEL_0", + "description": "Read protection not active", + "value": 170 + }, + { + "name": "LEVEL_1", + "description": "Memories read protection active", + "value": 187 + }, + { + "name": "LEVEL_2", + "description": "Chip read protection active", + "value": 204 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/flash_g4c4.json b/data/registers/flash_g4c4.json new file mode 100644 index 0000000000..bddffc9d6e --- /dev/null +++ b/data/registers/flash_g4c4.json @@ -0,0 +1,622 @@ +{ + "block/FLASH": { + "description": "Flash", + "items": [ + { + "name": "ACR", + "description": "Access control register", + "byte_offset": 0, + "fieldset": "ACR" + }, + { + "name": "PDKEYR", + "description": "Power down key register", + "byte_offset": 4, + "access": "Write" + }, + { + "name": "KEYR", + "description": "Flash key register", + "byte_offset": 8, + "access": "Write" + }, + { + "name": "OPTKEYR", + "description": "Option byte key register", + "byte_offset": 12, + "access": "Write" + }, + { + "name": "SR", + "description": "Status register", + "byte_offset": 16, + "fieldset": "SR" + }, + { + "name": "CR", + "description": "Flash control register", + "byte_offset": 20, + "fieldset": "CR" + }, + { + "name": "ECCR", + "description": "Flash ECC register", + "byte_offset": 24, + "fieldset": "ECCR" + }, + { + "name": "OPTR", + "description": "Flash option register", + "byte_offset": 32, + "fieldset": "OPTR" + }, + { + "name": "PCROP1SR", + "description": "Flash Bank 1 PCROP Start address register", + "byte_offset": 36, + "fieldset": "PCROP1SR" + }, + { + "name": "PCROP1ER", + "description": "Flash Bank 1 PCROP End address register", + "byte_offset": 40, + "fieldset": "PCROP1ER" + }, + { + "name": "WRP1AR", + "description": "Flash Bank 1 WRP area A address register", + "byte_offset": 44, + "fieldset": "WRP1AR" + }, + { + "name": "WRP1BR", + "description": "Flash Bank 1 WRP area B address register", + "byte_offset": 48, + "fieldset": "WRP1BR" + }, + { + "name": "SEC1R", + "description": "securable area bank1 register", + "byte_offset": 112, + "fieldset": "SEC1R" + } + ] + }, + "fieldset/ACR": { + "description": "Access control register", + "fields": [ + { + "name": "LATENCY", + "description": "Latency", + "bit_offset": 0, + "bit_size": 4, + "enum": "LATENCY" + }, + { + "name": "PRFTEN", + "description": "Prefetch enable", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "ICEN", + "description": "Instruction cache enable", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "DCEN", + "description": "Data cache enable", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "ICRST", + "description": "Instruction cache reset", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "DCRST", + "description": "Data cache reset", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "RUN_PD", + "description": "Flash Power-down mode during Low-power run mode", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "SLEEP_PD", + "description": "Flash Power-down mode during Low-power sleep mode", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "DBG_SWEN", + "description": "Debug software enable", + "bit_offset": 18, + "bit_size": 1 + } + ] + }, + "fieldset/CR": { + "description": "Flash control register", + "fields": [ + { + "name": "PG", + "description": "Programming", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "PER", + "description": "Page erase", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "MER1", + "description": "Bank 1 Mass erase", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "PNB", + "description": "Page number", + "bit_offset": 3, + "bit_size": 7 + }, + { + "name": "STRT", + "description": "Start", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "OPTSTRT", + "description": "Options modification start", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "FSTPG", + "description": "Fast programming", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "EOPIE", + "description": "End of operation interrupt enable", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "RDERRIE", + "description": "PCROP read error interrupt enable", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "OBL_LAUNCH", + "description": "Force the option byte loading", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "SEC_PROT1", + "description": "Securable memory area protection enable", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "OPTLOCK", + "description": "Options Lock", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "LOCK", + "description": "FLASH_CR Lock", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/ECCR": { + "description": "Flash ECC register", + "fields": [ + { + "name": "ADDR_ECC", + "description": "ECC fail address", + "bit_offset": 0, + "bit_size": 19 + }, + { + "name": "BK_ECC", + "description": "ECC fail for Corrected ECC Error or Double ECC Error in info block", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "SYSF_ECC", + "description": "ECC fail for Corrected ECC Error or Double ECC Error in info block", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ECCIE", + "description": "ECC correction interrupt enable", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ECCC2", + "description": "ECC correction", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ECCD2", + "description": "ECC2 detection", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "ECCC", + "description": "ECC correction", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "ECCD", + "description": "ECC detection", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/OPTR": { + "description": "Flash option register", + "fields": [ + { + "name": "RDP", + "description": "Read protection level", + "bit_offset": 0, + "bit_size": 8, + "enum": "RDP" + }, + { + "name": "BOR_LEV", + "description": "BOR reset Level", + "bit_offset": 8, + "bit_size": 3 + }, + { + "name": "nRST_STOP", + "description": "nRST_STOP", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "nRST_STDBY", + "description": "nRST_STDBY", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "nRST_SHDW", + "description": "nRST_SHDW", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "IDWG_SW", + "description": "Independent watchdog selection", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "IWDG_STOP", + "description": "Independent watchdog counter freeze in Stop mode", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "IWDG_STDBY", + "description": "Independent watchdog counter freeze in Standby mode", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "WWDG_SW", + "description": "Window watchdog selection", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "PB4_PUPEN", + "description": "PB4 pull-up enable", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "nBOOT1", + "description": "Boot configuration", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "SRAM2_PE", + "description": "SRAM2 parity check enable", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "SRAM2_RST", + "description": "SRAM2 Erase when system reset", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "nSWBOOT0", + "description": "nSWBOOT0", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "nBOOT0", + "description": "nBOOT0 option bit", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "NRST_MODE", + "description": "NRST_MODE", + "bit_offset": 28, + "bit_size": 2, + "enum": "NRST_MODE" + }, + { + "name": "IRHEN", + "description": "Internal reset holder enable bit", + "bit_offset": 30, + "bit_size": 1 + } + ] + }, + "fieldset/PCROP1ER": { + "description": "Flash Bank 1 PCROP End address register", + "fields": [ + { + "name": "PCROP1_END", + "description": "Bank 1 PCROP area end offset", + "bit_offset": 0, + "bit_size": 15 + }, + { + "name": "PCROP_RDP", + "description": "PCROP area preserved when RDP level decreased", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/PCROP1SR": { + "description": "Flash Bank 1 PCROP Start address register", + "fields": [ + { + "name": "PCROP1_STRT", + "description": "Bank 1 PCROP area start offset", + "bit_offset": 0, + "bit_size": 15 + } + ] + }, + "fieldset/SEC1R": { + "description": "securable area bank1 register", + "fields": [ + { + "name": "SEC_SIZE1", + "description": "SEC_SIZE1", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "BOOT_LOCK", + "description": "used to force boot from user area", + "bit_offset": 16, + "bit_size": 1 + } + ] + }, + "fieldset/SR": { + "description": "Status register", + "fields": [ + { + "name": "EOP", + "description": "End of operation", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "OPERR", + "description": "Operation error", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "PROGERR", + "description": "Programming error", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "WRPERR", + "description": "Write protected error", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PGAERR", + "description": "Programming alignment error", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "SIZERR", + "description": "Size error", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "PGSERR", + "description": "Programming sequence error", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "MISERR", + "description": "Fast programming data miss error", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FASTERR", + "description": "Fast programming error", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "RDERR", + "description": "PCROP read error", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "OPTVERR", + "description": "Option validity error", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "BSY", + "description": "Busy", + "bit_offset": 16, + "bit_size": 1 + } + ] + }, + "fieldset/WRP1AR": { + "description": "Flash Bank 1 WRP area A address register", + "fields": [ + { + "name": "WRP1A_STRT", + "description": "Bank 1 WRP first area start offset", + "bit_offset": 0, + "bit_size": 7 + }, + { + "name": "WRP1A_END", + "description": "Bank 1 WRP first area A end offset", + "bit_offset": 16, + "bit_size": 7 + } + ] + }, + "fieldset/WRP1BR": { + "description": "Flash Bank 1 WRP area B address register", + "fields": [ + { + "name": "WRP1B_STRT", + "description": "Bank 1 WRP second area B end offset", + "bit_offset": 0, + "bit_size": 7 + }, + { + "name": "WRP1B_END", + "description": "Bank 1 WRP second area B start offset", + "bit_offset": 16, + "bit_size": 7 + } + ] + }, + "enum/LATENCY": { + "bit_size": 4, + "variants": [ + { + "name": "WS0", + "description": "Zero wait states", + "value": 0 + }, + { + "name": "WS1", + "description": "One wait state", + "value": 1 + }, + { + "name": "WS2", + "description": "Two wait states", + "value": 2 + }, + { + "name": "WS3", + "description": "Three wait states", + "value": 3 + }, + { + "name": "WS4", + "description": "Four wait states", + "value": 4 + } + ] + }, + "enum/NRST_MODE": { + "bit_size": 2, + "variants": [ + { + "name": "INPUT_ONLY", + "description": "Reset pin is in reset input mode only", + "value": 1 + }, + { + "name": "GPIO", + "description": "Reset pin is in GPIO mode only", + "value": 2 + }, + { + "name": "INPUT_OUTPUT", + "description": "Reset pin is in reset input and output mode", + "value": 3 + } + ] + }, + "enum/RDP": { + "bit_size": 8, + "variants": [ + { + "name": "LEVEL_0", + "description": "Read protection not active", + "value": 170 + }, + { + "name": "LEVEL_1", + "description": "Memories read protection active", + "value": 187 + }, + { + "name": "LEVEL_2", + "description": "Chip read protection active", + "value": 204 + } + ] + } +} \ No newline at end of file diff --git a/stm32-metapac/src/chips/metadata_0318.rs b/stm32-metapac/src/chips/metadata_0318.rs index a561c9619e..88d65fc51c 100644 --- a/stm32-metapac/src/chips/metadata_0318.rs +++ b/stm32-metapac/src/chips/metadata_0318.rs @@ -902,7 +902,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c2", block: "FLASH", ir: &flash::REGISTERS, }), @@ -4721,7 +4721,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c2.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0319.rs b/stm32-metapac/src/chips/metadata_0319.rs index 4d64ad56fc..c57482dfbc 100644 --- a/stm32-metapac/src/chips/metadata_0319.rs +++ b/stm32-metapac/src/chips/metadata_0319.rs @@ -827,7 +827,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c2", block: "FLASH", ir: &flash::REGISTERS, }), @@ -4181,7 +4181,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c2.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0320.rs b/stm32-metapac/src/chips/metadata_0320.rs index b00523b586..aabca70a5b 100644 --- a/stm32-metapac/src/chips/metadata_0320.rs +++ b/stm32-metapac/src/chips/metadata_0320.rs @@ -982,7 +982,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c2", block: "FLASH", ir: &flash::REGISTERS, }), @@ -5191,7 +5191,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c2.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0321.rs b/stm32-metapac/src/chips/metadata_0321.rs index bcd16f17ba..1cb41e71de 100644 --- a/stm32-metapac/src/chips/metadata_0321.rs +++ b/stm32-metapac/src/chips/metadata_0321.rs @@ -962,7 +962,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c2", block: "FLASH", ir: &flash::REGISTERS, }), @@ -5061,7 +5061,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c2.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0322.rs b/stm32-metapac/src/chips/metadata_0322.rs index a3803c7def..24474a4254 100644 --- a/stm32-metapac/src/chips/metadata_0322.rs +++ b/stm32-metapac/src/chips/metadata_0322.rs @@ -982,7 +982,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c2", block: "FLASH", ir: &flash::REGISTERS, }), @@ -5446,7 +5446,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c2.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0323.rs b/stm32-metapac/src/chips/metadata_0323.rs index 248ded8c00..3e45e31662 100644 --- a/stm32-metapac/src/chips/metadata_0323.rs +++ b/stm32-metapac/src/chips/metadata_0323.rs @@ -946,7 +946,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c2", block: "FLASH", ir: &flash::REGISTERS, }), @@ -4771,7 +4771,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c2.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0324.rs b/stm32-metapac/src/chips/metadata_0324.rs index 02843e5f57..388e5f1ab4 100644 --- a/stm32-metapac/src/chips/metadata_0324.rs +++ b/stm32-metapac/src/chips/metadata_0324.rs @@ -871,7 +871,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c2", block: "FLASH", ir: &flash::REGISTERS, }), @@ -4231,7 +4231,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c2.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0325.rs b/stm32-metapac/src/chips/metadata_0325.rs index 2e5858cdfb..6ce5f8e050 100644 --- a/stm32-metapac/src/chips/metadata_0325.rs +++ b/stm32-metapac/src/chips/metadata_0325.rs @@ -1026,7 +1026,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c2", block: "FLASH", ir: &flash::REGISTERS, }), @@ -5241,7 +5241,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c2.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0326.rs b/stm32-metapac/src/chips/metadata_0326.rs index 7921b9cab0..b16456dcba 100644 --- a/stm32-metapac/src/chips/metadata_0326.rs +++ b/stm32-metapac/src/chips/metadata_0326.rs @@ -1006,7 +1006,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c2", block: "FLASH", ir: &flash::REGISTERS, }), @@ -5111,7 +5111,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c2.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0327.rs b/stm32-metapac/src/chips/metadata_0327.rs index 5c8a69020d..ca5e67a636 100644 --- a/stm32-metapac/src/chips/metadata_0327.rs +++ b/stm32-metapac/src/chips/metadata_0327.rs @@ -1026,7 +1026,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c2", block: "FLASH", ir: &flash::REGISTERS, }), @@ -5496,7 +5496,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c2.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0328.rs b/stm32-metapac/src/chips/metadata_0328.rs index c751dd2c53..a822c84af4 100644 --- a/stm32-metapac/src/chips/metadata_0328.rs +++ b/stm32-metapac/src/chips/metadata_0328.rs @@ -1045,7 +1045,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -5250,7 +5250,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0329.rs b/stm32-metapac/src/chips/metadata_0329.rs index a00e8aa77d..ceb916e922 100644 --- a/stm32-metapac/src/chips/metadata_0329.rs +++ b/stm32-metapac/src/chips/metadata_0329.rs @@ -1170,7 +1170,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -5907,7 +5907,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0330.rs b/stm32-metapac/src/chips/metadata_0330.rs index 59a26ebce8..e2b0dbba56 100644 --- a/stm32-metapac/src/chips/metadata_0330.rs +++ b/stm32-metapac/src/chips/metadata_0330.rs @@ -1190,7 +1190,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -6542,7 +6542,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0331.rs b/stm32-metapac/src/chips/metadata_0331.rs index 8b9ccc7744..e185d83aff 100644 --- a/stm32-metapac/src/chips/metadata_0331.rs +++ b/stm32-metapac/src/chips/metadata_0331.rs @@ -1105,7 +1105,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -5622,7 +5622,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0332.rs b/stm32-metapac/src/chips/metadata_0332.rs index 65cedf4507..611a110b31 100644 --- a/stm32-metapac/src/chips/metadata_0332.rs +++ b/stm32-metapac/src/chips/metadata_0332.rs @@ -1185,7 +1185,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -6282,7 +6282,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0333.rs b/stm32-metapac/src/chips/metadata_0333.rs index bcff062420..7800c63788 100644 --- a/stm32-metapac/src/chips/metadata_0333.rs +++ b/stm32-metapac/src/chips/metadata_0333.rs @@ -1408,7 +1408,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -5992,7 +5992,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0334.rs b/stm32-metapac/src/chips/metadata_0334.rs index e1b4bbd2df..ab7e0c788d 100644 --- a/stm32-metapac/src/chips/metadata_0334.rs +++ b/stm32-metapac/src/chips/metadata_0334.rs @@ -1643,7 +1643,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -6824,7 +6824,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0335.rs b/stm32-metapac/src/chips/metadata_0335.rs index 69fe0308c9..37a3e0cdb7 100644 --- a/stm32-metapac/src/chips/metadata_0335.rs +++ b/stm32-metapac/src/chips/metadata_0335.rs @@ -1713,7 +1713,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -7834,7 +7834,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0336.rs b/stm32-metapac/src/chips/metadata_0336.rs index 2ccb39a50a..035cb93d94 100644 --- a/stm32-metapac/src/chips/metadata_0336.rs +++ b/stm32-metapac/src/chips/metadata_0336.rs @@ -1713,7 +1713,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -7944,7 +7944,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0337.rs b/stm32-metapac/src/chips/metadata_0337.rs index a9460e600e..38059c5a80 100644 --- a/stm32-metapac/src/chips/metadata_0337.rs +++ b/stm32-metapac/src/chips/metadata_0337.rs @@ -1478,7 +1478,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -6389,7 +6389,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0338.rs b/stm32-metapac/src/chips/metadata_0338.rs index 91ff40d240..4fa96ab46a 100644 --- a/stm32-metapac/src/chips/metadata_0338.rs +++ b/stm32-metapac/src/chips/metadata_0338.rs @@ -1708,7 +1708,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -7559,7 +7559,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0339.rs b/stm32-metapac/src/chips/metadata_0339.rs index 1739df0ae3..9f19352d90 100644 --- a/stm32-metapac/src/chips/metadata_0339.rs +++ b/stm32-metapac/src/chips/metadata_0339.rs @@ -1408,7 +1408,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -6274,7 +6274,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0340.rs b/stm32-metapac/src/chips/metadata_0340.rs index 625581b224..5aa13e8764 100644 --- a/stm32-metapac/src/chips/metadata_0340.rs +++ b/stm32-metapac/src/chips/metadata_0340.rs @@ -1643,7 +1643,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -7136,7 +7136,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0341.rs b/stm32-metapac/src/chips/metadata_0341.rs index 27edb2d441..bc22481e59 100644 --- a/stm32-metapac/src/chips/metadata_0341.rs +++ b/stm32-metapac/src/chips/metadata_0341.rs @@ -1713,7 +1713,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -8146,7 +8146,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0342.rs b/stm32-metapac/src/chips/metadata_0342.rs index 99dbf3e125..b78c15bddc 100644 --- a/stm32-metapac/src/chips/metadata_0342.rs +++ b/stm32-metapac/src/chips/metadata_0342.rs @@ -1713,7 +1713,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -8256,7 +8256,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0343.rs b/stm32-metapac/src/chips/metadata_0343.rs index baa9214f4f..24a8577404 100644 --- a/stm32-metapac/src/chips/metadata_0343.rs +++ b/stm32-metapac/src/chips/metadata_0343.rs @@ -1478,7 +1478,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -6701,7 +6701,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0344.rs b/stm32-metapac/src/chips/metadata_0344.rs index 2e9d350c13..489f2f6ad4 100644 --- a/stm32-metapac/src/chips/metadata_0344.rs +++ b/stm32-metapac/src/chips/metadata_0344.rs @@ -1708,7 +1708,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -7871,7 +7871,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0345.rs b/stm32-metapac/src/chips/metadata_0345.rs index be4f215ffe..98852e1238 100644 --- a/stm32-metapac/src/chips/metadata_0345.rs +++ b/stm32-metapac/src/chips/metadata_0345.rs @@ -1452,7 +1452,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -6042,7 +6042,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0346.rs b/stm32-metapac/src/chips/metadata_0346.rs index 8c5d3f6ac1..207dbb2ec3 100644 --- a/stm32-metapac/src/chips/metadata_0346.rs +++ b/stm32-metapac/src/chips/metadata_0346.rs @@ -1687,7 +1687,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -6874,7 +6874,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0347.rs b/stm32-metapac/src/chips/metadata_0347.rs index 3b66fef103..a384c93279 100644 --- a/stm32-metapac/src/chips/metadata_0347.rs +++ b/stm32-metapac/src/chips/metadata_0347.rs @@ -1757,7 +1757,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -7884,7 +7884,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0348.rs b/stm32-metapac/src/chips/metadata_0348.rs index 60051210e5..2959ef3fd7 100644 --- a/stm32-metapac/src/chips/metadata_0348.rs +++ b/stm32-metapac/src/chips/metadata_0348.rs @@ -1757,7 +1757,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -7994,7 +7994,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0349.rs b/stm32-metapac/src/chips/metadata_0349.rs index 8fc3c11dfe..410ecc1df9 100644 --- a/stm32-metapac/src/chips/metadata_0349.rs +++ b/stm32-metapac/src/chips/metadata_0349.rs @@ -1522,7 +1522,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -6439,7 +6439,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0350.rs b/stm32-metapac/src/chips/metadata_0350.rs index 782df65ddb..124fdfd0e7 100644 --- a/stm32-metapac/src/chips/metadata_0350.rs +++ b/stm32-metapac/src/chips/metadata_0350.rs @@ -1752,7 +1752,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -7609,7 +7609,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0351.rs b/stm32-metapac/src/chips/metadata_0351.rs index 69795c0b6e..18e0f41ff1 100644 --- a/stm32-metapac/src/chips/metadata_0351.rs +++ b/stm32-metapac/src/chips/metadata_0351.rs @@ -1452,7 +1452,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -6324,7 +6324,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0352.rs b/stm32-metapac/src/chips/metadata_0352.rs index c12abc983f..930c3f4ebc 100644 --- a/stm32-metapac/src/chips/metadata_0352.rs +++ b/stm32-metapac/src/chips/metadata_0352.rs @@ -1687,7 +1687,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -7186,7 +7186,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0353.rs b/stm32-metapac/src/chips/metadata_0353.rs index ee80c4d383..9cc60bf0ee 100644 --- a/stm32-metapac/src/chips/metadata_0353.rs +++ b/stm32-metapac/src/chips/metadata_0353.rs @@ -1757,7 +1757,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -8196,7 +8196,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0354.rs b/stm32-metapac/src/chips/metadata_0354.rs index bd8a462552..76100f967e 100644 --- a/stm32-metapac/src/chips/metadata_0354.rs +++ b/stm32-metapac/src/chips/metadata_0354.rs @@ -1757,7 +1757,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -8306,7 +8306,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0355.rs b/stm32-metapac/src/chips/metadata_0355.rs index 419b9a1090..cc9771544a 100644 --- a/stm32-metapac/src/chips/metadata_0355.rs +++ b/stm32-metapac/src/chips/metadata_0355.rs @@ -1522,7 +1522,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -6751,7 +6751,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0356.rs b/stm32-metapac/src/chips/metadata_0356.rs index 1204217de0..9af6a9a246 100644 --- a/stm32-metapac/src/chips/metadata_0356.rs +++ b/stm32-metapac/src/chips/metadata_0356.rs @@ -1752,7 +1752,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c3", block: "FLASH", ir: &flash::REGISTERS, }), @@ -7921,7 +7921,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c3.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0357.rs b/stm32-metapac/src/chips/metadata_0357.rs index 40fa87a0a0..5542aec1f6 100644 --- a/stm32-metapac/src/chips/metadata_0357.rs +++ b/stm32-metapac/src/chips/metadata_0357.rs @@ -1045,7 +1045,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c4", block: "FLASH", ir: &flash::REGISTERS, }), @@ -5189,7 +5189,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c4.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0358.rs b/stm32-metapac/src/chips/metadata_0358.rs index 84968b9c77..9b82f8565a 100644 --- a/stm32-metapac/src/chips/metadata_0358.rs +++ b/stm32-metapac/src/chips/metadata_0358.rs @@ -948,7 +948,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c4", block: "FLASH", ir: &flash::REGISTERS, }), @@ -4555,7 +4555,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c4.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0359.rs b/stm32-metapac/src/chips/metadata_0359.rs index e3a5e54d31..14ee8f4d44 100644 --- a/stm32-metapac/src/chips/metadata_0359.rs +++ b/stm32-metapac/src/chips/metadata_0359.rs @@ -1165,7 +1165,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c4", block: "FLASH", ir: &flash::REGISTERS, }), @@ -5834,7 +5834,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c4.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0360.rs b/stm32-metapac/src/chips/metadata_0360.rs index 438c1240dd..71b418fd6d 100644 --- a/stm32-metapac/src/chips/metadata_0360.rs +++ b/stm32-metapac/src/chips/metadata_0360.rs @@ -1105,7 +1105,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c4", block: "FLASH", ir: &flash::REGISTERS, }), @@ -5624,7 +5624,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c4.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0361.rs b/stm32-metapac/src/chips/metadata_0361.rs index c24343b80d..8ac61fd95c 100644 --- a/stm32-metapac/src/chips/metadata_0361.rs +++ b/stm32-metapac/src/chips/metadata_0361.rs @@ -1185,7 +1185,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c4", block: "FLASH", ir: &flash::REGISTERS, }), @@ -6199,7 +6199,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c4.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0362.rs b/stm32-metapac/src/chips/metadata_0362.rs index fa7b547ea9..7470153688 100644 --- a/stm32-metapac/src/chips/metadata_0362.rs +++ b/stm32-metapac/src/chips/metadata_0362.rs @@ -1089,7 +1089,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c4", block: "FLASH", ir: &flash::REGISTERS, }), @@ -5239,7 +5239,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c4.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0363.rs b/stm32-metapac/src/chips/metadata_0363.rs index 49dc31259e..b99fb2da1f 100644 --- a/stm32-metapac/src/chips/metadata_0363.rs +++ b/stm32-metapac/src/chips/metadata_0363.rs @@ -992,7 +992,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c4", block: "FLASH", ir: &flash::REGISTERS, }), @@ -4605,7 +4605,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c4.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0364.rs b/stm32-metapac/src/chips/metadata_0364.rs index 2f1c119ad6..3fc0b54eda 100644 --- a/stm32-metapac/src/chips/metadata_0364.rs +++ b/stm32-metapac/src/chips/metadata_0364.rs @@ -1209,7 +1209,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c4", block: "FLASH", ir: &flash::REGISTERS, }), @@ -5884,7 +5884,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c4.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0365.rs b/stm32-metapac/src/chips/metadata_0365.rs index 3ce4b2c43f..5ad3201f73 100644 --- a/stm32-metapac/src/chips/metadata_0365.rs +++ b/stm32-metapac/src/chips/metadata_0365.rs @@ -1149,7 +1149,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c4", block: "FLASH", ir: &flash::REGISTERS, }), @@ -5674,7 +5674,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c4.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/metadata_0366.rs b/stm32-metapac/src/chips/metadata_0366.rs index 901f0afba0..ff1966e529 100644 --- a/stm32-metapac/src/chips/metadata_0366.rs +++ b/stm32-metapac/src/chips/metadata_0366.rs @@ -1229,7 +1229,7 @@ pub(crate) static PERIPHERALS: &[Peripheral] = &[ address: 0x40022000, registers: Some(PeripheralRegisters { kind: "flash", - version: "g4", + version: "g4c4", block: "FLASH", ir: &flash::REGISTERS, }), @@ -6249,7 +6249,7 @@ pub mod dmamux; pub mod exti; #[path = "../registers/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../registers/flash_g4.rs"] +#[path = "../registers/flash_g4c4.rs"] pub mod flash; #[path = "../registers/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g431c6/pac.rs b/stm32-metapac/src/chips/stm32g431c6/pac.rs index bb7f3aea31..a5e7839b52 100644 --- a/stm32-metapac/src/chips/stm32g431c6/pac.rs +++ b/stm32-metapac/src/chips/stm32g431c6/pac.rs @@ -465,7 +465,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g431c8/pac.rs b/stm32-metapac/src/chips/stm32g431c8/pac.rs index d481fca72c..5733e8547b 100644 --- a/stm32-metapac/src/chips/stm32g431c8/pac.rs +++ b/stm32-metapac/src/chips/stm32g431c8/pac.rs @@ -465,7 +465,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g431cb/pac.rs b/stm32-metapac/src/chips/stm32g431cb/pac.rs index 5825b723db..f410300fe2 100644 --- a/stm32-metapac/src/chips/stm32g431cb/pac.rs +++ b/stm32-metapac/src/chips/stm32g431cb/pac.rs @@ -465,7 +465,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g431k6/pac.rs b/stm32-metapac/src/chips/stm32g431k6/pac.rs index 81cee98a92..c7186533ff 100644 --- a/stm32-metapac/src/chips/stm32g431k6/pac.rs +++ b/stm32-metapac/src/chips/stm32g431k6/pac.rs @@ -464,7 +464,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g431k8/pac.rs b/stm32-metapac/src/chips/stm32g431k8/pac.rs index 6eadfa9392..63b361c6a7 100644 --- a/stm32-metapac/src/chips/stm32g431k8/pac.rs +++ b/stm32-metapac/src/chips/stm32g431k8/pac.rs @@ -464,7 +464,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g431kb/pac.rs b/stm32-metapac/src/chips/stm32g431kb/pac.rs index 257638493e..bc7faa4ab4 100644 --- a/stm32-metapac/src/chips/stm32g431kb/pac.rs +++ b/stm32-metapac/src/chips/stm32g431kb/pac.rs @@ -464,7 +464,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g431m6/pac.rs b/stm32-metapac/src/chips/stm32g431m6/pac.rs index 785dda3229..ed5cea4a1a 100644 --- a/stm32-metapac/src/chips/stm32g431m6/pac.rs +++ b/stm32-metapac/src/chips/stm32g431m6/pac.rs @@ -466,7 +466,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g431m8/pac.rs b/stm32-metapac/src/chips/stm32g431m8/pac.rs index e8b9e5707e..60983dc0d0 100644 --- a/stm32-metapac/src/chips/stm32g431m8/pac.rs +++ b/stm32-metapac/src/chips/stm32g431m8/pac.rs @@ -466,7 +466,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g431mb/pac.rs b/stm32-metapac/src/chips/stm32g431mb/pac.rs index e818d6af06..ff0c80a267 100644 --- a/stm32-metapac/src/chips/stm32g431mb/pac.rs +++ b/stm32-metapac/src/chips/stm32g431mb/pac.rs @@ -466,7 +466,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g431r6/pac.rs b/stm32-metapac/src/chips/stm32g431r6/pac.rs index 785dda3229..ed5cea4a1a 100644 --- a/stm32-metapac/src/chips/stm32g431r6/pac.rs +++ b/stm32-metapac/src/chips/stm32g431r6/pac.rs @@ -466,7 +466,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g431r8/pac.rs b/stm32-metapac/src/chips/stm32g431r8/pac.rs index e8b9e5707e..60983dc0d0 100644 --- a/stm32-metapac/src/chips/stm32g431r8/pac.rs +++ b/stm32-metapac/src/chips/stm32g431r8/pac.rs @@ -466,7 +466,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g431rb/pac.rs b/stm32-metapac/src/chips/stm32g431rb/pac.rs index e818d6af06..ff0c80a267 100644 --- a/stm32-metapac/src/chips/stm32g431rb/pac.rs +++ b/stm32-metapac/src/chips/stm32g431rb/pac.rs @@ -466,7 +466,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g431v6/pac.rs b/stm32-metapac/src/chips/stm32g431v6/pac.rs index 785dda3229..ed5cea4a1a 100644 --- a/stm32-metapac/src/chips/stm32g431v6/pac.rs +++ b/stm32-metapac/src/chips/stm32g431v6/pac.rs @@ -466,7 +466,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g431v8/pac.rs b/stm32-metapac/src/chips/stm32g431v8/pac.rs index e8b9e5707e..60983dc0d0 100644 --- a/stm32-metapac/src/chips/stm32g431v8/pac.rs +++ b/stm32-metapac/src/chips/stm32g431v8/pac.rs @@ -466,7 +466,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g431vb/pac.rs b/stm32-metapac/src/chips/stm32g431vb/pac.rs index e818d6af06..ff0c80a267 100644 --- a/stm32-metapac/src/chips/stm32g431vb/pac.rs +++ b/stm32-metapac/src/chips/stm32g431vb/pac.rs @@ -466,7 +466,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g441cb/pac.rs b/stm32-metapac/src/chips/stm32g441cb/pac.rs index 3dbf9a0e08..56743435c7 100644 --- a/stm32-metapac/src/chips/stm32g441cb/pac.rs +++ b/stm32-metapac/src/chips/stm32g441cb/pac.rs @@ -471,7 +471,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g441kb/pac.rs b/stm32-metapac/src/chips/stm32g441kb/pac.rs index 3e4789c2f2..963622842f 100644 --- a/stm32-metapac/src/chips/stm32g441kb/pac.rs +++ b/stm32-metapac/src/chips/stm32g441kb/pac.rs @@ -470,7 +470,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g441mb/pac.rs b/stm32-metapac/src/chips/stm32g441mb/pac.rs index e0c3908aed..6bec907b5a 100644 --- a/stm32-metapac/src/chips/stm32g441mb/pac.rs +++ b/stm32-metapac/src/chips/stm32g441mb/pac.rs @@ -472,7 +472,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g441rb/pac.rs b/stm32-metapac/src/chips/stm32g441rb/pac.rs index e0c3908aed..6bec907b5a 100644 --- a/stm32-metapac/src/chips/stm32g441rb/pac.rs +++ b/stm32-metapac/src/chips/stm32g441rb/pac.rs @@ -472,7 +472,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g441vb/pac.rs b/stm32-metapac/src/chips/stm32g441vb/pac.rs index e0c3908aed..6bec907b5a 100644 --- a/stm32-metapac/src/chips/stm32g441vb/pac.rs +++ b/stm32-metapac/src/chips/stm32g441vb/pac.rs @@ -472,7 +472,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c2.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g471cc/pac.rs b/stm32-metapac/src/chips/stm32g471cc/pac.rs index ec5d82ed04..8103dff962 100644 --- a/stm32-metapac/src/chips/stm32g471cc/pac.rs +++ b/stm32-metapac/src/chips/stm32g471cc/pac.rs @@ -530,7 +530,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g471ce/pac.rs b/stm32-metapac/src/chips/stm32g471ce/pac.rs index 1d0c37a122..8efbe0edbf 100644 --- a/stm32-metapac/src/chips/stm32g471ce/pac.rs +++ b/stm32-metapac/src/chips/stm32g471ce/pac.rs @@ -530,7 +530,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g471mc/pac.rs b/stm32-metapac/src/chips/stm32g471mc/pac.rs index ad3e4cad98..cdc12e85aa 100644 --- a/stm32-metapac/src/chips/stm32g471mc/pac.rs +++ b/stm32-metapac/src/chips/stm32g471mc/pac.rs @@ -532,7 +532,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g471me/pac.rs b/stm32-metapac/src/chips/stm32g471me/pac.rs index cefcad08f1..a83be474c3 100644 --- a/stm32-metapac/src/chips/stm32g471me/pac.rs +++ b/stm32-metapac/src/chips/stm32g471me/pac.rs @@ -532,7 +532,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g471qc/pac.rs b/stm32-metapac/src/chips/stm32g471qc/pac.rs index ad3e4cad98..cdc12e85aa 100644 --- a/stm32-metapac/src/chips/stm32g471qc/pac.rs +++ b/stm32-metapac/src/chips/stm32g471qc/pac.rs @@ -532,7 +532,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g471qe/pac.rs b/stm32-metapac/src/chips/stm32g471qe/pac.rs index cefcad08f1..a83be474c3 100644 --- a/stm32-metapac/src/chips/stm32g471qe/pac.rs +++ b/stm32-metapac/src/chips/stm32g471qe/pac.rs @@ -532,7 +532,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g471rc/pac.rs b/stm32-metapac/src/chips/stm32g471rc/pac.rs index d2d5d688a4..0384f101f1 100644 --- a/stm32-metapac/src/chips/stm32g471rc/pac.rs +++ b/stm32-metapac/src/chips/stm32g471rc/pac.rs @@ -531,7 +531,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g471re/pac.rs b/stm32-metapac/src/chips/stm32g471re/pac.rs index dbcf66a179..b98402a80e 100644 --- a/stm32-metapac/src/chips/stm32g471re/pac.rs +++ b/stm32-metapac/src/chips/stm32g471re/pac.rs @@ -531,7 +531,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g471vc/pac.rs b/stm32-metapac/src/chips/stm32g471vc/pac.rs index ad3e4cad98..cdc12e85aa 100644 --- a/stm32-metapac/src/chips/stm32g471vc/pac.rs +++ b/stm32-metapac/src/chips/stm32g471vc/pac.rs @@ -532,7 +532,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g471ve/pac.rs b/stm32-metapac/src/chips/stm32g471ve/pac.rs index cefcad08f1..a83be474c3 100644 --- a/stm32-metapac/src/chips/stm32g471ve/pac.rs +++ b/stm32-metapac/src/chips/stm32g471ve/pac.rs @@ -532,7 +532,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473cb/pac.rs b/stm32-metapac/src/chips/stm32g473cb/pac.rs index f95b50b484..63a4c4445b 100644 --- a/stm32-metapac/src/chips/stm32g473cb/pac.rs +++ b/stm32-metapac/src/chips/stm32g473cb/pac.rs @@ -564,7 +564,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473cc/pac.rs b/stm32-metapac/src/chips/stm32g473cc/pac.rs index 2bf23a89b9..f667a7fe99 100644 --- a/stm32-metapac/src/chips/stm32g473cc/pac.rs +++ b/stm32-metapac/src/chips/stm32g473cc/pac.rs @@ -564,7 +564,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473ce/pac.rs b/stm32-metapac/src/chips/stm32g473ce/pac.rs index 3e2f28d406..920a9c042e 100644 --- a/stm32-metapac/src/chips/stm32g473ce/pac.rs +++ b/stm32-metapac/src/chips/stm32g473ce/pac.rs @@ -564,7 +564,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473mb/pac.rs b/stm32-metapac/src/chips/stm32g473mb/pac.rs index 3f91118fc8..4dd8308ca2 100644 --- a/stm32-metapac/src/chips/stm32g473mb/pac.rs +++ b/stm32-metapac/src/chips/stm32g473mb/pac.rs @@ -566,7 +566,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473mc/pac.rs b/stm32-metapac/src/chips/stm32g473mc/pac.rs index 5113c89e69..56344cc273 100644 --- a/stm32-metapac/src/chips/stm32g473mc/pac.rs +++ b/stm32-metapac/src/chips/stm32g473mc/pac.rs @@ -566,7 +566,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473me/pac.rs b/stm32-metapac/src/chips/stm32g473me/pac.rs index bcfe271f5c..425e343ad9 100644 --- a/stm32-metapac/src/chips/stm32g473me/pac.rs +++ b/stm32-metapac/src/chips/stm32g473me/pac.rs @@ -566,7 +566,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473pb/pac.rs b/stm32-metapac/src/chips/stm32g473pb/pac.rs index 6982e43993..bef4b00788 100644 --- a/stm32-metapac/src/chips/stm32g473pb/pac.rs +++ b/stm32-metapac/src/chips/stm32g473pb/pac.rs @@ -567,7 +567,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473pc/pac.rs b/stm32-metapac/src/chips/stm32g473pc/pac.rs index 91c599c948..c9b2c1e913 100644 --- a/stm32-metapac/src/chips/stm32g473pc/pac.rs +++ b/stm32-metapac/src/chips/stm32g473pc/pac.rs @@ -567,7 +567,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473pe/pac.rs b/stm32-metapac/src/chips/stm32g473pe/pac.rs index fffd33d069..1a7da83d91 100644 --- a/stm32-metapac/src/chips/stm32g473pe/pac.rs +++ b/stm32-metapac/src/chips/stm32g473pe/pac.rs @@ -567,7 +567,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473qb/pac.rs b/stm32-metapac/src/chips/stm32g473qb/pac.rs index 6982e43993..bef4b00788 100644 --- a/stm32-metapac/src/chips/stm32g473qb/pac.rs +++ b/stm32-metapac/src/chips/stm32g473qb/pac.rs @@ -567,7 +567,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473qc/pac.rs b/stm32-metapac/src/chips/stm32g473qc/pac.rs index 91c599c948..c9b2c1e913 100644 --- a/stm32-metapac/src/chips/stm32g473qc/pac.rs +++ b/stm32-metapac/src/chips/stm32g473qc/pac.rs @@ -567,7 +567,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473qe/pac.rs b/stm32-metapac/src/chips/stm32g473qe/pac.rs index fffd33d069..1a7da83d91 100644 --- a/stm32-metapac/src/chips/stm32g473qe/pac.rs +++ b/stm32-metapac/src/chips/stm32g473qe/pac.rs @@ -567,7 +567,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473rb/pac.rs b/stm32-metapac/src/chips/stm32g473rb/pac.rs index 58ee9924f7..ddffd0ab16 100644 --- a/stm32-metapac/src/chips/stm32g473rb/pac.rs +++ b/stm32-metapac/src/chips/stm32g473rb/pac.rs @@ -565,7 +565,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473rc/pac.rs b/stm32-metapac/src/chips/stm32g473rc/pac.rs index 048e6d9fe4..e5338aadac 100644 --- a/stm32-metapac/src/chips/stm32g473rc/pac.rs +++ b/stm32-metapac/src/chips/stm32g473rc/pac.rs @@ -565,7 +565,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473re/pac.rs b/stm32-metapac/src/chips/stm32g473re/pac.rs index 39f3cfafc4..c175d5b027 100644 --- a/stm32-metapac/src/chips/stm32g473re/pac.rs +++ b/stm32-metapac/src/chips/stm32g473re/pac.rs @@ -565,7 +565,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473vb/pac.rs b/stm32-metapac/src/chips/stm32g473vb/pac.rs index 6982e43993..bef4b00788 100644 --- a/stm32-metapac/src/chips/stm32g473vb/pac.rs +++ b/stm32-metapac/src/chips/stm32g473vb/pac.rs @@ -567,7 +567,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473vc/pac.rs b/stm32-metapac/src/chips/stm32g473vc/pac.rs index 91c599c948..c9b2c1e913 100644 --- a/stm32-metapac/src/chips/stm32g473vc/pac.rs +++ b/stm32-metapac/src/chips/stm32g473vc/pac.rs @@ -567,7 +567,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g473ve/pac.rs b/stm32-metapac/src/chips/stm32g473ve/pac.rs index fffd33d069..1a7da83d91 100644 --- a/stm32-metapac/src/chips/stm32g473ve/pac.rs +++ b/stm32-metapac/src/chips/stm32g473ve/pac.rs @@ -567,7 +567,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474cb/pac.rs b/stm32-metapac/src/chips/stm32g474cb/pac.rs index 5054b82af4..174e91c5da 100644 --- a/stm32-metapac/src/chips/stm32g474cb/pac.rs +++ b/stm32-metapac/src/chips/stm32g474cb/pac.rs @@ -591,7 +591,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474cc/pac.rs b/stm32-metapac/src/chips/stm32g474cc/pac.rs index dce446de9a..85f610ff44 100644 --- a/stm32-metapac/src/chips/stm32g474cc/pac.rs +++ b/stm32-metapac/src/chips/stm32g474cc/pac.rs @@ -591,7 +591,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474ce/pac.rs b/stm32-metapac/src/chips/stm32g474ce/pac.rs index 438239050a..6436684623 100644 --- a/stm32-metapac/src/chips/stm32g474ce/pac.rs +++ b/stm32-metapac/src/chips/stm32g474ce/pac.rs @@ -591,7 +591,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474mb/pac.rs b/stm32-metapac/src/chips/stm32g474mb/pac.rs index 14b77aafe8..2ff9a6b955 100644 --- a/stm32-metapac/src/chips/stm32g474mb/pac.rs +++ b/stm32-metapac/src/chips/stm32g474mb/pac.rs @@ -593,7 +593,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474mc/pac.rs b/stm32-metapac/src/chips/stm32g474mc/pac.rs index 2f4ed81cfd..36bcf7870b 100644 --- a/stm32-metapac/src/chips/stm32g474mc/pac.rs +++ b/stm32-metapac/src/chips/stm32g474mc/pac.rs @@ -593,7 +593,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474me/pac.rs b/stm32-metapac/src/chips/stm32g474me/pac.rs index c1b8b41ae6..1770632783 100644 --- a/stm32-metapac/src/chips/stm32g474me/pac.rs +++ b/stm32-metapac/src/chips/stm32g474me/pac.rs @@ -593,7 +593,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474pb/pac.rs b/stm32-metapac/src/chips/stm32g474pb/pac.rs index 204b4b15e4..d136f9fc31 100644 --- a/stm32-metapac/src/chips/stm32g474pb/pac.rs +++ b/stm32-metapac/src/chips/stm32g474pb/pac.rs @@ -594,7 +594,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474pc/pac.rs b/stm32-metapac/src/chips/stm32g474pc/pac.rs index 26c2ed87af..d1a3f1b2dc 100644 --- a/stm32-metapac/src/chips/stm32g474pc/pac.rs +++ b/stm32-metapac/src/chips/stm32g474pc/pac.rs @@ -594,7 +594,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474pe/pac.rs b/stm32-metapac/src/chips/stm32g474pe/pac.rs index 3f8803da97..3548642967 100644 --- a/stm32-metapac/src/chips/stm32g474pe/pac.rs +++ b/stm32-metapac/src/chips/stm32g474pe/pac.rs @@ -594,7 +594,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474qb/pac.rs b/stm32-metapac/src/chips/stm32g474qb/pac.rs index 204b4b15e4..d136f9fc31 100644 --- a/stm32-metapac/src/chips/stm32g474qb/pac.rs +++ b/stm32-metapac/src/chips/stm32g474qb/pac.rs @@ -594,7 +594,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474qc/pac.rs b/stm32-metapac/src/chips/stm32g474qc/pac.rs index 26c2ed87af..d1a3f1b2dc 100644 --- a/stm32-metapac/src/chips/stm32g474qc/pac.rs +++ b/stm32-metapac/src/chips/stm32g474qc/pac.rs @@ -594,7 +594,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474qe/pac.rs b/stm32-metapac/src/chips/stm32g474qe/pac.rs index 3f8803da97..3548642967 100644 --- a/stm32-metapac/src/chips/stm32g474qe/pac.rs +++ b/stm32-metapac/src/chips/stm32g474qe/pac.rs @@ -594,7 +594,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474rb/pac.rs b/stm32-metapac/src/chips/stm32g474rb/pac.rs index a79752ea46..73f45aca6c 100644 --- a/stm32-metapac/src/chips/stm32g474rb/pac.rs +++ b/stm32-metapac/src/chips/stm32g474rb/pac.rs @@ -592,7 +592,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474rc/pac.rs b/stm32-metapac/src/chips/stm32g474rc/pac.rs index e6d15974f3..448174e94e 100644 --- a/stm32-metapac/src/chips/stm32g474rc/pac.rs +++ b/stm32-metapac/src/chips/stm32g474rc/pac.rs @@ -592,7 +592,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474re/pac.rs b/stm32-metapac/src/chips/stm32g474re/pac.rs index 5842bae968..aba37e7438 100644 --- a/stm32-metapac/src/chips/stm32g474re/pac.rs +++ b/stm32-metapac/src/chips/stm32g474re/pac.rs @@ -592,7 +592,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474vb/pac.rs b/stm32-metapac/src/chips/stm32g474vb/pac.rs index 204b4b15e4..d136f9fc31 100644 --- a/stm32-metapac/src/chips/stm32g474vb/pac.rs +++ b/stm32-metapac/src/chips/stm32g474vb/pac.rs @@ -594,7 +594,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474vc/pac.rs b/stm32-metapac/src/chips/stm32g474vc/pac.rs index 26c2ed87af..d1a3f1b2dc 100644 --- a/stm32-metapac/src/chips/stm32g474vc/pac.rs +++ b/stm32-metapac/src/chips/stm32g474vc/pac.rs @@ -594,7 +594,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g474ve/pac.rs b/stm32-metapac/src/chips/stm32g474ve/pac.rs index 3f8803da97..3548642967 100644 --- a/stm32-metapac/src/chips/stm32g474ve/pac.rs +++ b/stm32-metapac/src/chips/stm32g474ve/pac.rs @@ -594,7 +594,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g483ce/pac.rs b/stm32-metapac/src/chips/stm32g483ce/pac.rs index 0b76388554..a9ebcd51ff 100644 --- a/stm32-metapac/src/chips/stm32g483ce/pac.rs +++ b/stm32-metapac/src/chips/stm32g483ce/pac.rs @@ -570,7 +570,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g483me/pac.rs b/stm32-metapac/src/chips/stm32g483me/pac.rs index 79a7bc85ca..4b8f0ec4e5 100644 --- a/stm32-metapac/src/chips/stm32g483me/pac.rs +++ b/stm32-metapac/src/chips/stm32g483me/pac.rs @@ -572,7 +572,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g483pe/pac.rs b/stm32-metapac/src/chips/stm32g483pe/pac.rs index 5d1e498203..30d633fdc0 100644 --- a/stm32-metapac/src/chips/stm32g483pe/pac.rs +++ b/stm32-metapac/src/chips/stm32g483pe/pac.rs @@ -573,7 +573,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g483qe/pac.rs b/stm32-metapac/src/chips/stm32g483qe/pac.rs index 5d1e498203..30d633fdc0 100644 --- a/stm32-metapac/src/chips/stm32g483qe/pac.rs +++ b/stm32-metapac/src/chips/stm32g483qe/pac.rs @@ -573,7 +573,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g483re/pac.rs b/stm32-metapac/src/chips/stm32g483re/pac.rs index 982c624974..732c0b4f77 100644 --- a/stm32-metapac/src/chips/stm32g483re/pac.rs +++ b/stm32-metapac/src/chips/stm32g483re/pac.rs @@ -571,7 +571,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g483ve/pac.rs b/stm32-metapac/src/chips/stm32g483ve/pac.rs index 5d1e498203..30d633fdc0 100644 --- a/stm32-metapac/src/chips/stm32g483ve/pac.rs +++ b/stm32-metapac/src/chips/stm32g483ve/pac.rs @@ -573,7 +573,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g484ce/pac.rs b/stm32-metapac/src/chips/stm32g484ce/pac.rs index 2802f0485b..a750ed8164 100644 --- a/stm32-metapac/src/chips/stm32g484ce/pac.rs +++ b/stm32-metapac/src/chips/stm32g484ce/pac.rs @@ -597,7 +597,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g484me/pac.rs b/stm32-metapac/src/chips/stm32g484me/pac.rs index d2314b3aaa..18b9749952 100644 --- a/stm32-metapac/src/chips/stm32g484me/pac.rs +++ b/stm32-metapac/src/chips/stm32g484me/pac.rs @@ -599,7 +599,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g484pe/pac.rs b/stm32-metapac/src/chips/stm32g484pe/pac.rs index 5909d9c07c..c933edc913 100644 --- a/stm32-metapac/src/chips/stm32g484pe/pac.rs +++ b/stm32-metapac/src/chips/stm32g484pe/pac.rs @@ -600,7 +600,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g484qe/pac.rs b/stm32-metapac/src/chips/stm32g484qe/pac.rs index 5909d9c07c..c933edc913 100644 --- a/stm32-metapac/src/chips/stm32g484qe/pac.rs +++ b/stm32-metapac/src/chips/stm32g484qe/pac.rs @@ -600,7 +600,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g484re/pac.rs b/stm32-metapac/src/chips/stm32g484re/pac.rs index a861ffd550..ae0b349194 100644 --- a/stm32-metapac/src/chips/stm32g484re/pac.rs +++ b/stm32-metapac/src/chips/stm32g484re/pac.rs @@ -598,7 +598,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g484ve/pac.rs b/stm32-metapac/src/chips/stm32g484ve/pac.rs index 5909d9c07c..c933edc913 100644 --- a/stm32-metapac/src/chips/stm32g484ve/pac.rs +++ b/stm32-metapac/src/chips/stm32g484ve/pac.rs @@ -600,7 +600,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c3.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g491cc/pac.rs b/stm32-metapac/src/chips/stm32g491cc/pac.rs index 8fb45cbbbb..2dee4e287f 100644 --- a/stm32-metapac/src/chips/stm32g491cc/pac.rs +++ b/stm32-metapac/src/chips/stm32g491cc/pac.rs @@ -520,7 +520,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c4.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g491ce/pac.rs b/stm32-metapac/src/chips/stm32g491ce/pac.rs index 7a6ec783cb..dd5451ffb7 100644 --- a/stm32-metapac/src/chips/stm32g491ce/pac.rs +++ b/stm32-metapac/src/chips/stm32g491ce/pac.rs @@ -520,7 +520,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c4.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g491kc/pac.rs b/stm32-metapac/src/chips/stm32g491kc/pac.rs index 66b93e3dea..103de7537a 100644 --- a/stm32-metapac/src/chips/stm32g491kc/pac.rs +++ b/stm32-metapac/src/chips/stm32g491kc/pac.rs @@ -519,7 +519,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c4.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g491ke/pac.rs b/stm32-metapac/src/chips/stm32g491ke/pac.rs index 63cf34729c..d141097e42 100644 --- a/stm32-metapac/src/chips/stm32g491ke/pac.rs +++ b/stm32-metapac/src/chips/stm32g491ke/pac.rs @@ -519,7 +519,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c4.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g491mc/pac.rs b/stm32-metapac/src/chips/stm32g491mc/pac.rs index 1f63a2fd44..7e1076a48d 100644 --- a/stm32-metapac/src/chips/stm32g491mc/pac.rs +++ b/stm32-metapac/src/chips/stm32g491mc/pac.rs @@ -522,7 +522,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c4.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g491me/pac.rs b/stm32-metapac/src/chips/stm32g491me/pac.rs index 4167c196bd..4180b1c783 100644 --- a/stm32-metapac/src/chips/stm32g491me/pac.rs +++ b/stm32-metapac/src/chips/stm32g491me/pac.rs @@ -522,7 +522,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c4.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g491rc/pac.rs b/stm32-metapac/src/chips/stm32g491rc/pac.rs index 1f63a2fd44..7e1076a48d 100644 --- a/stm32-metapac/src/chips/stm32g491rc/pac.rs +++ b/stm32-metapac/src/chips/stm32g491rc/pac.rs @@ -522,7 +522,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c4.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g491re/pac.rs b/stm32-metapac/src/chips/stm32g491re/pac.rs index 4167c196bd..4180b1c783 100644 --- a/stm32-metapac/src/chips/stm32g491re/pac.rs +++ b/stm32-metapac/src/chips/stm32g491re/pac.rs @@ -522,7 +522,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c4.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g491vc/pac.rs b/stm32-metapac/src/chips/stm32g491vc/pac.rs index 1f63a2fd44..7e1076a48d 100644 --- a/stm32-metapac/src/chips/stm32g491vc/pac.rs +++ b/stm32-metapac/src/chips/stm32g491vc/pac.rs @@ -522,7 +522,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c4.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g491ve/pac.rs b/stm32-metapac/src/chips/stm32g491ve/pac.rs index 4167c196bd..4180b1c783 100644 --- a/stm32-metapac/src/chips/stm32g491ve/pac.rs +++ b/stm32-metapac/src/chips/stm32g491ve/pac.rs @@ -522,7 +522,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c4.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g4a1ce/pac.rs b/stm32-metapac/src/chips/stm32g4a1ce/pac.rs index 13dbb29ddd..da44681919 100644 --- a/stm32-metapac/src/chips/stm32g4a1ce/pac.rs +++ b/stm32-metapac/src/chips/stm32g4a1ce/pac.rs @@ -526,7 +526,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c4.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g4a1ke/pac.rs b/stm32-metapac/src/chips/stm32g4a1ke/pac.rs index e0bf67c45c..5e90ee9096 100644 --- a/stm32-metapac/src/chips/stm32g4a1ke/pac.rs +++ b/stm32-metapac/src/chips/stm32g4a1ke/pac.rs @@ -525,7 +525,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c4.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g4a1me/pac.rs b/stm32-metapac/src/chips/stm32g4a1me/pac.rs index 582f229ee5..6db74c8a63 100644 --- a/stm32-metapac/src/chips/stm32g4a1me/pac.rs +++ b/stm32-metapac/src/chips/stm32g4a1me/pac.rs @@ -528,7 +528,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c4.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g4a1re/pac.rs b/stm32-metapac/src/chips/stm32g4a1re/pac.rs index 582f229ee5..6db74c8a63 100644 --- a/stm32-metapac/src/chips/stm32g4a1re/pac.rs +++ b/stm32-metapac/src/chips/stm32g4a1re/pac.rs @@ -528,7 +528,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c4.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/chips/stm32g4a1ve/pac.rs b/stm32-metapac/src/chips/stm32g4a1ve/pac.rs index 582f229ee5..6db74c8a63 100644 --- a/stm32-metapac/src/chips/stm32g4a1ve/pac.rs +++ b/stm32-metapac/src/chips/stm32g4a1ve/pac.rs @@ -528,7 +528,7 @@ pub mod dmamux; pub mod exti; #[path = "../../peripherals/fdcanram_v1.rs"] pub mod fdcanram; -#[path = "../../peripherals/flash_g4.rs"] +#[path = "../../peripherals/flash_g4c4.rs"] pub mod flash; #[path = "../../peripherals/fmac_v1.rs"] pub mod fmac; diff --git a/stm32-metapac/src/peripherals/flash_g4.rs b/stm32-metapac/src/peripherals/flash_g4c2.rs similarity index 100% rename from stm32-metapac/src/peripherals/flash_g4.rs rename to stm32-metapac/src/peripherals/flash_g4c2.rs diff --git a/stm32-metapac/src/peripherals/flash_g4c3.rs b/stm32-metapac/src/peripherals/flash_g4c3.rs new file mode 100644 index 0000000000..7039058c08 --- /dev/null +++ b/stm32-metapac/src/peripherals/flash_g4c3.rs @@ -0,0 +1,1103 @@ +#![allow(clippy::missing_safety_doc)] +#![allow(clippy::identity_op)] +#![allow(clippy::unnecessary_cast)] +#![allow(clippy::erasing_op)] + +#[doc = "Flash"] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Flash { + ptr: *mut u8, +} +unsafe impl Send for Flash {} +unsafe impl Sync for Flash {} +impl Flash { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Access control register"] + #[inline(always)] + pub const fn acr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "Power down key register"] + #[inline(always)] + pub const fn pdkeyr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "Flash key register"] + #[inline(always)] + pub const fn keyr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "Option byte key register"] + #[inline(always)] + pub const fn optkeyr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } + #[doc = "Status register"] + #[inline(always)] + pub const fn sr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } + } + #[doc = "Flash control register"] + #[inline(always)] + pub const fn cr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } + } + #[doc = "Flash ECC register"] + #[inline(always)] + pub const fn eccr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } + } + #[doc = "Flash option register"] + #[inline(always)] + pub const fn optr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } + } + #[doc = "Flash Bank 1 PCROP Start address register"] + #[inline(always)] + pub const fn pcrop1sr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } + } + #[doc = "Flash Bank 1 PCROP End address register"] + #[inline(always)] + pub const fn pcrop1er(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } + } + #[doc = "Flash Bank 1 WRP area A address register"] + #[inline(always)] + pub const fn wrp1ar(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } + } + #[doc = "Flash Bank 1 WRP area B address register"] + #[inline(always)] + pub const fn wrp1br(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } + } + #[doc = "securable area bank1 register"] + #[inline(always)] + pub const fn sec1r(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) } + } +} +pub mod regs { + #[doc = "Access control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Acr(pub u32); + impl Acr { + #[doc = "Latency"] + #[inline(always)] + pub const fn latency(&self) -> super::vals::Latency { + let val = (self.0 >> 0usize) & 0x0f; + super::vals::Latency::from_bits(val as u8) + } + #[doc = "Latency"] + #[inline(always)] + pub fn set_latency(&mut self, val: super::vals::Latency) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize); + } + #[doc = "Prefetch enable"] + #[inline(always)] + pub const fn prften(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Prefetch enable"] + #[inline(always)] + pub fn set_prften(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Instruction cache enable"] + #[inline(always)] + pub const fn icen(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Instruction cache enable"] + #[inline(always)] + pub fn set_icen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Data cache enable"] + #[inline(always)] + pub const fn dcen(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Data cache enable"] + #[inline(always)] + pub fn set_dcen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Instruction cache reset"] + #[inline(always)] + pub const fn icrst(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Instruction cache reset"] + #[inline(always)] + pub fn set_icrst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Data cache reset"] + #[inline(always)] + pub const fn dcrst(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Data cache reset"] + #[inline(always)] + pub fn set_dcrst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Flash Power-down mode during Low-power run mode"] + #[inline(always)] + pub const fn run_pd(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Flash Power-down mode during Low-power run mode"] + #[inline(always)] + pub fn set_run_pd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Flash Power-down mode during Low-power sleep mode"] + #[inline(always)] + pub const fn sleep_pd(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Flash Power-down mode during Low-power sleep mode"] + #[inline(always)] + pub fn set_sleep_pd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Debug software enable"] + #[inline(always)] + pub const fn dbg_swen(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Debug software enable"] + #[inline(always)] + pub fn set_dbg_swen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + } + impl Default for Acr { + #[inline(always)] + fn default() -> Acr { + Acr(0) + } + } + #[doc = "Flash control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Programming"] + #[inline(always)] + pub const fn pg(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Programming"] + #[inline(always)] + pub fn set_pg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Page erase"] + #[inline(always)] + pub const fn per(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Page erase"] + #[inline(always)] + pub fn set_per(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Bank 1 Mass erase"] + #[inline(always)] + pub const fn mer1(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Bank 1 Mass erase"] + #[inline(always)] + pub fn set_mer1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Page number"] + #[inline(always)] + pub const fn pnb(&self) -> u8 { + let val = (self.0 >> 3usize) & 0x7f; + val as u8 + } + #[doc = "Page number"] + #[inline(always)] + pub fn set_pnb(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 3usize)) | (((val as u32) & 0x7f) << 3usize); + } + #[doc = "Bank 2 Mass erase"] + #[inline(always)] + pub const fn mer2(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Bank 2 Mass erase"] + #[inline(always)] + pub fn set_mer2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "Start"] + #[inline(always)] + pub const fn strt(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Start"] + #[inline(always)] + pub fn set_strt(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Options modification start"] + #[inline(always)] + pub const fn optstrt(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Options modification start"] + #[inline(always)] + pub fn set_optstrt(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Fast programming"] + #[inline(always)] + pub const fn fstpg(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Fast programming"] + #[inline(always)] + pub fn set_fstpg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "End of operation interrupt enable"] + #[inline(always)] + pub const fn eopie(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "End of operation interrupt enable"] + #[inline(always)] + pub fn set_eopie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "Error interrupt enable"] + #[inline(always)] + pub const fn errie(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + #[inline(always)] + pub fn set_errie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "PCROP read error interrupt enable"] + #[inline(always)] + pub const fn rderrie(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "PCROP read error interrupt enable"] + #[inline(always)] + pub fn set_rderrie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "Force the option byte loading"] + #[inline(always)] + pub const fn obl_launch(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "Force the option byte loading"] + #[inline(always)] + pub fn set_obl_launch(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } + #[doc = "Securable memory area protection enable"] + #[inline(always)] + pub const fn sec_prot1(&self) -> bool { + let val = (self.0 >> 28usize) & 0x01; + val != 0 + } + #[doc = "Securable memory area protection enable"] + #[inline(always)] + pub fn set_sec_prot1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + } + #[doc = "Options Lock"] + #[inline(always)] + pub const fn optlock(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; + val != 0 + } + #[doc = "Options Lock"] + #[inline(always)] + pub fn set_optlock(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + } + #[doc = "FLASH_CR Lock"] + #[inline(always)] + pub const fn lock(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "FLASH_CR Lock"] + #[inline(always)] + pub fn set_lock(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } + } + impl Default for Cr { + #[inline(always)] + fn default() -> Cr { + Cr(0) + } + } + #[doc = "Flash ECC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Eccr(pub u32); + impl Eccr { + #[doc = "ECC fail address"] + #[inline(always)] + pub const fn addr_ecc(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x0007_ffff; + val as u32 + } + #[doc = "ECC fail address"] + #[inline(always)] + pub fn set_addr_ecc(&mut self, val: u32) { + self.0 = (self.0 & !(0x0007_ffff << 0usize)) | (((val as u32) & 0x0007_ffff) << 0usize); + } + #[doc = "ECC fail for Corrected ECC Error or Double ECC Error in info block"] + #[inline(always)] + pub const fn bk_ecc(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "ECC fail for Corrected ECC Error or Double ECC Error in info block"] + #[inline(always)] + pub fn set_bk_ecc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "ECC fail for Corrected ECC Error or Double ECC Error in info block"] + #[inline(always)] + pub const fn sysf_ecc(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "ECC fail for Corrected ECC Error or Double ECC Error in info block"] + #[inline(always)] + pub fn set_sysf_ecc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "ECC correction interrupt enable"] + #[inline(always)] + pub const fn eccie(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "ECC correction interrupt enable"] + #[inline(always)] + pub fn set_eccie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "ECC correction"] + #[inline(always)] + pub const fn eccc2(&self) -> bool { + let val = (self.0 >> 28usize) & 0x01; + val != 0 + } + #[doc = "ECC correction"] + #[inline(always)] + pub fn set_eccc2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + } + #[doc = "ECC2 detection"] + #[inline(always)] + pub const fn eccd2(&self) -> bool { + let val = (self.0 >> 29usize) & 0x01; + val != 0 + } + #[doc = "ECC2 detection"] + #[inline(always)] + pub fn set_eccd2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); + } + #[doc = "ECC correction"] + #[inline(always)] + pub const fn eccc(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; + val != 0 + } + #[doc = "ECC correction"] + #[inline(always)] + pub fn set_eccc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + } + #[doc = "ECC detection"] + #[inline(always)] + pub const fn eccd(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "ECC detection"] + #[inline(always)] + pub fn set_eccd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } + } + impl Default for Eccr { + #[inline(always)] + fn default() -> Eccr { + Eccr(0) + } + } + #[doc = "Flash option register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Optr(pub u32); + impl Optr { + #[doc = "Read protection level"] + #[inline(always)] + pub const fn rdp(&self) -> super::vals::Rdp { + let val = (self.0 >> 0usize) & 0xff; + super::vals::Rdp::from_bits(val as u8) + } + #[doc = "Read protection level"] + #[inline(always)] + pub fn set_rdp(&mut self, val: super::vals::Rdp) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); + } + #[doc = "BOR reset Level"] + #[inline(always)] + pub const fn bor_lev(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x07; + val as u8 + } + #[doc = "BOR reset Level"] + #[inline(always)] + pub fn set_bor_lev(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u32) & 0x07) << 8usize); + } + #[doc = "nRST_STOP"] + #[inline(always)] + pub const fn n_rst_stop(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "nRST_STOP"] + #[inline(always)] + pub fn set_n_rst_stop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "nRST_STDBY"] + #[inline(always)] + pub const fn n_rst_stdby(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "nRST_STDBY"] + #[inline(always)] + pub fn set_n_rst_stdby(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "nRST_SHDW"] + #[inline(always)] + pub const fn n_rst_shdw(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "nRST_SHDW"] + #[inline(always)] + pub fn set_n_rst_shdw(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Independent watchdog selection"] + #[inline(always)] + pub const fn idwg_sw(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Independent watchdog selection"] + #[inline(always)] + pub fn set_idwg_sw(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Independent watchdog counter freeze in Stop mode"] + #[inline(always)] + pub const fn iwdg_stop(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Independent watchdog counter freeze in Stop mode"] + #[inline(always)] + pub fn set_iwdg_stop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Independent watchdog counter freeze in Standby mode"] + #[inline(always)] + pub const fn iwdg_stdby(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Independent watchdog counter freeze in Standby mode"] + #[inline(always)] + pub fn set_iwdg_stdby(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Window watchdog selection"] + #[inline(always)] + pub const fn wwdg_sw(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Window watchdog selection"] + #[inline(always)] + pub fn set_wwdg_sw(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "Dual bank boot"] + #[inline(always)] + pub const fn bfb2(&self) -> bool { + let val = (self.0 >> 20usize) & 0x01; + val != 0 + } + #[doc = "Dual bank boot"] + #[inline(always)] + pub fn set_bfb2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); + } + #[doc = "Dual bank memory mode"] + #[inline(always)] + pub const fn dbank(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "Dual bank memory mode"] + #[inline(always)] + pub fn set_dbank(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "Boot configuration"] + #[inline(always)] + pub const fn n_boot1(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Boot configuration"] + #[inline(always)] + pub fn set_n_boot1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "SRAM2 parity check enable"] + #[inline(always)] + pub const fn sram2_pe(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 parity check enable"] + #[inline(always)] + pub fn set_sram2_pe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "SRAM2 Erase when system reset"] + #[inline(always)] + pub const fn sram2_rst(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 Erase when system reset"] + #[inline(always)] + pub fn set_sram2_rst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "nSWBOOT0"] + #[inline(always)] + pub const fn n_swboot0(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "nSWBOOT0"] + #[inline(always)] + pub fn set_n_swboot0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "nBOOT0 option bit"] + #[inline(always)] + pub const fn n_boot0(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "nBOOT0 option bit"] + #[inline(always)] + pub fn set_n_boot0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } + #[doc = "NRST_MODE"] + #[inline(always)] + pub const fn nrst_mode(&self) -> super::vals::NrstMode { + let val = (self.0 >> 28usize) & 0x03; + super::vals::NrstMode::from_bits(val as u8) + } + #[doc = "NRST_MODE"] + #[inline(always)] + pub fn set_nrst_mode(&mut self, val: super::vals::NrstMode) { + self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); + } + #[doc = "Internal reset holder enable bit"] + #[inline(always)] + pub const fn irhen(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; + val != 0 + } + #[doc = "Internal reset holder enable bit"] + #[inline(always)] + pub fn set_irhen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + } + } + impl Default for Optr { + #[inline(always)] + fn default() -> Optr { + Optr(0) + } + } + #[doc = "Flash Bank 1 PCROP End address register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pcrop1er(pub u32); + impl Pcrop1er { + #[doc = "Bank 1 PCROP area end offset"] + #[inline(always)] + pub const fn pcrop1_end(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x7fff; + val as u16 + } + #[doc = "Bank 1 PCROP area end offset"] + #[inline(always)] + pub fn set_pcrop1_end(&mut self, val: u16) { + self.0 = (self.0 & !(0x7fff << 0usize)) | (((val as u32) & 0x7fff) << 0usize); + } + #[doc = "PCROP area preserved when RDP level decreased"] + #[inline(always)] + pub const fn pcrop_rdp(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "PCROP area preserved when RDP level decreased"] + #[inline(always)] + pub fn set_pcrop_rdp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } + } + impl Default for Pcrop1er { + #[inline(always)] + fn default() -> Pcrop1er { + Pcrop1er(0) + } + } + #[doc = "Flash Bank 1 PCROP Start address register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pcrop1sr(pub u32); + impl Pcrop1sr { + #[doc = "Bank 1 PCROP area start offset"] + #[inline(always)] + pub const fn pcrop1_strt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x7fff; + val as u16 + } + #[doc = "Bank 1 PCROP area start offset"] + #[inline(always)] + pub fn set_pcrop1_strt(&mut self, val: u16) { + self.0 = (self.0 & !(0x7fff << 0usize)) | (((val as u32) & 0x7fff) << 0usize); + } + } + impl Default for Pcrop1sr { + #[inline(always)] + fn default() -> Pcrop1sr { + Pcrop1sr(0) + } + } + #[doc = "securable area bank1 register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sec1r(pub u32); + impl Sec1r { + #[doc = "SEC_SIZE1"] + #[inline(always)] + pub const fn sec_size1(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "SEC_SIZE1"] + #[inline(always)] + pub fn set_sec_size1(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "used to force boot from user area"] + #[inline(always)] + pub const fn boot_lock(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "used to force boot from user area"] + #[inline(always)] + pub fn set_boot_lock(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Sec1r { + #[inline(always)] + fn default() -> Sec1r { + Sec1r(0) + } + } + #[doc = "Status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "End of operation"] + #[inline(always)] + pub const fn eop(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "End of operation"] + #[inline(always)] + pub fn set_eop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Operation error"] + #[inline(always)] + pub const fn operr(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Operation error"] + #[inline(always)] + pub fn set_operr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Programming error"] + #[inline(always)] + pub const fn progerr(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Programming error"] + #[inline(always)] + pub fn set_progerr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Write protected error"] + #[inline(always)] + pub const fn wrperr(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Write protected error"] + #[inline(always)] + pub fn set_wrperr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Programming alignment error"] + #[inline(always)] + pub const fn pgaerr(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Programming alignment error"] + #[inline(always)] + pub fn set_pgaerr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Size error"] + #[inline(always)] + pub const fn sizerr(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Size error"] + #[inline(always)] + pub fn set_sizerr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Programming sequence error"] + #[inline(always)] + pub const fn pgserr(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Programming sequence error"] + #[inline(always)] + pub fn set_pgserr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Fast programming data miss error"] + #[inline(always)] + pub const fn miserr(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Fast programming data miss error"] + #[inline(always)] + pub fn set_miserr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Fast programming error"] + #[inline(always)] + pub const fn fasterr(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Fast programming error"] + #[inline(always)] + pub fn set_fasterr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "PCROP read error"] + #[inline(always)] + pub const fn rderr(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "PCROP read error"] + #[inline(always)] + pub fn set_rderr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Option validity error"] + #[inline(always)] + pub const fn optverr(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Option validity error"] + #[inline(always)] + pub fn set_optverr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "Busy"] + #[inline(always)] + pub const fn bsy(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Busy"] + #[inline(always)] + pub fn set_bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Sr { + #[inline(always)] + fn default() -> Sr { + Sr(0) + } + } + #[doc = "Flash Bank 1 WRP area A address register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Wrp1ar(pub u32); + impl Wrp1ar { + #[doc = "Bank 1 WRP first area start offset"] + #[inline(always)] + pub const fn wrp1a_strt(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x7f; + val as u8 + } + #[doc = "Bank 1 WRP first area start offset"] + #[inline(always)] + pub fn set_wrp1a_strt(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize); + } + #[doc = "Bank 1 WRP first area A end offset"] + #[inline(always)] + pub const fn wrp1a_end(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x7f; + val as u8 + } + #[doc = "Bank 1 WRP first area A end offset"] + #[inline(always)] + pub fn set_wrp1a_end(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize); + } + } + impl Default for Wrp1ar { + #[inline(always)] + fn default() -> Wrp1ar { + Wrp1ar(0) + } + } + #[doc = "Flash Bank 1 WRP area B address register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Wrp1br(pub u32); + impl Wrp1br { + #[doc = "Bank 1 WRP second area B end offset"] + #[inline(always)] + pub const fn wrp1b_strt(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x7f; + val as u8 + } + #[doc = "Bank 1 WRP second area B end offset"] + #[inline(always)] + pub fn set_wrp1b_strt(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize); + } + #[doc = "Bank 1 WRP second area B start offset"] + #[inline(always)] + pub const fn wrp1b_end(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x7f; + val as u8 + } + #[doc = "Bank 1 WRP second area B start offset"] + #[inline(always)] + pub fn set_wrp1b_end(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize); + } + } + impl Default for Wrp1br { + #[inline(always)] + fn default() -> Wrp1br { + Wrp1br(0) + } + } +} +pub mod vals { + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Latency { + #[doc = "Zero wait states"] + WS0 = 0x0, + #[doc = "One wait state"] + WS1 = 0x01, + #[doc = "Two wait states"] + WS2 = 0x02, + #[doc = "Three wait states"] + WS3 = 0x03, + #[doc = "Four wait states"] + WS4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, + _RESERVED_8 = 0x08, + _RESERVED_9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, + } + impl Latency { + #[inline(always)] + pub const fn from_bits(val: u8) -> Latency { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Latency { + #[inline(always)] + fn from(val: u8) -> Latency { + Latency::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Latency) -> u8 { + Latency::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum NrstMode { + _RESERVED_0 = 0x0, + #[doc = "Reset pin is in reset input mode only"] + INPUT_ONLY = 0x01, + #[doc = "Reset pin is in GPIO mode only"] + GPIO = 0x02, + #[doc = "Reset pin is in reset input and output mode"] + INPUT_OUTPUT = 0x03, + } + impl NrstMode { + #[inline(always)] + pub const fn from_bits(val: u8) -> NrstMode { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for NrstMode { + #[inline(always)] + fn from(val: u8) -> NrstMode { + NrstMode::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: NrstMode) -> u8 { + NrstMode::to_bits(val) + } + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rdp(pub u8); + impl Rdp { + #[doc = "Read protection not active"] + pub const LEVEL_0: Self = Self(0xaa); + #[doc = "Memories read protection active"] + pub const LEVEL_1: Self = Self(0xbb); + #[doc = "Chip read protection active"] + pub const LEVEL_2: Self = Self(0xcc); + } + impl Rdp { + pub const fn from_bits(val: u8) -> Rdp { + Self(val & 0xff) + } + pub const fn to_bits(self) -> u8 { + self.0 + } + } + impl From for Rdp { + #[inline(always)] + fn from(val: u8) -> Rdp { + Rdp::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Rdp) -> u8 { + Rdp::to_bits(val) + } + } +} diff --git a/stm32-metapac/src/peripherals/flash_g4c4.rs b/stm32-metapac/src/peripherals/flash_g4c4.rs new file mode 100644 index 0000000000..595de447de --- /dev/null +++ b/stm32-metapac/src/peripherals/flash_g4c4.rs @@ -0,0 +1,1081 @@ +#![allow(clippy::missing_safety_doc)] +#![allow(clippy::identity_op)] +#![allow(clippy::unnecessary_cast)] +#![allow(clippy::erasing_op)] + +#[doc = "Flash"] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Flash { + ptr: *mut u8, +} +unsafe impl Send for Flash {} +unsafe impl Sync for Flash {} +impl Flash { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Access control register"] + #[inline(always)] + pub const fn acr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "Power down key register"] + #[inline(always)] + pub const fn pdkeyr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "Flash key register"] + #[inline(always)] + pub const fn keyr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "Option byte key register"] + #[inline(always)] + pub const fn optkeyr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } + #[doc = "Status register"] + #[inline(always)] + pub const fn sr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } + } + #[doc = "Flash control register"] + #[inline(always)] + pub const fn cr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } + } + #[doc = "Flash ECC register"] + #[inline(always)] + pub const fn eccr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } + } + #[doc = "Flash option register"] + #[inline(always)] + pub const fn optr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } + } + #[doc = "Flash Bank 1 PCROP Start address register"] + #[inline(always)] + pub const fn pcrop1sr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } + } + #[doc = "Flash Bank 1 PCROP End address register"] + #[inline(always)] + pub const fn pcrop1er(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } + } + #[doc = "Flash Bank 1 WRP area A address register"] + #[inline(always)] + pub const fn wrp1ar(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } + } + #[doc = "Flash Bank 1 WRP area B address register"] + #[inline(always)] + pub const fn wrp1br(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } + } + #[doc = "securable area bank1 register"] + #[inline(always)] + pub const fn sec1r(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) } + } +} +pub mod regs { + #[doc = "Access control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Acr(pub u32); + impl Acr { + #[doc = "Latency"] + #[inline(always)] + pub const fn latency(&self) -> super::vals::Latency { + let val = (self.0 >> 0usize) & 0x0f; + super::vals::Latency::from_bits(val as u8) + } + #[doc = "Latency"] + #[inline(always)] + pub fn set_latency(&mut self, val: super::vals::Latency) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize); + } + #[doc = "Prefetch enable"] + #[inline(always)] + pub const fn prften(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Prefetch enable"] + #[inline(always)] + pub fn set_prften(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Instruction cache enable"] + #[inline(always)] + pub const fn icen(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Instruction cache enable"] + #[inline(always)] + pub fn set_icen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Data cache enable"] + #[inline(always)] + pub const fn dcen(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Data cache enable"] + #[inline(always)] + pub fn set_dcen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Instruction cache reset"] + #[inline(always)] + pub const fn icrst(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Instruction cache reset"] + #[inline(always)] + pub fn set_icrst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Data cache reset"] + #[inline(always)] + pub const fn dcrst(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Data cache reset"] + #[inline(always)] + pub fn set_dcrst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Flash Power-down mode during Low-power run mode"] + #[inline(always)] + pub const fn run_pd(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Flash Power-down mode during Low-power run mode"] + #[inline(always)] + pub fn set_run_pd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Flash Power-down mode during Low-power sleep mode"] + #[inline(always)] + pub const fn sleep_pd(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Flash Power-down mode during Low-power sleep mode"] + #[inline(always)] + pub fn set_sleep_pd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Debug software enable"] + #[inline(always)] + pub const fn dbg_swen(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Debug software enable"] + #[inline(always)] + pub fn set_dbg_swen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + } + impl Default for Acr { + #[inline(always)] + fn default() -> Acr { + Acr(0) + } + } + #[doc = "Flash control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Programming"] + #[inline(always)] + pub const fn pg(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Programming"] + #[inline(always)] + pub fn set_pg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Page erase"] + #[inline(always)] + pub const fn per(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Page erase"] + #[inline(always)] + pub fn set_per(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Bank 1 Mass erase"] + #[inline(always)] + pub const fn mer1(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Bank 1 Mass erase"] + #[inline(always)] + pub fn set_mer1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Page number"] + #[inline(always)] + pub const fn pnb(&self) -> u8 { + let val = (self.0 >> 3usize) & 0x7f; + val as u8 + } + #[doc = "Page number"] + #[inline(always)] + pub fn set_pnb(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 3usize)) | (((val as u32) & 0x7f) << 3usize); + } + #[doc = "Start"] + #[inline(always)] + pub const fn strt(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Start"] + #[inline(always)] + pub fn set_strt(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Options modification start"] + #[inline(always)] + pub const fn optstrt(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Options modification start"] + #[inline(always)] + pub fn set_optstrt(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Fast programming"] + #[inline(always)] + pub const fn fstpg(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Fast programming"] + #[inline(always)] + pub fn set_fstpg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "End of operation interrupt enable"] + #[inline(always)] + pub const fn eopie(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "End of operation interrupt enable"] + #[inline(always)] + pub fn set_eopie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "Error interrupt enable"] + #[inline(always)] + pub const fn errie(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + #[inline(always)] + pub fn set_errie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "PCROP read error interrupt enable"] + #[inline(always)] + pub const fn rderrie(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "PCROP read error interrupt enable"] + #[inline(always)] + pub fn set_rderrie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "Force the option byte loading"] + #[inline(always)] + pub const fn obl_launch(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "Force the option byte loading"] + #[inline(always)] + pub fn set_obl_launch(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } + #[doc = "Securable memory area protection enable"] + #[inline(always)] + pub const fn sec_prot1(&self) -> bool { + let val = (self.0 >> 28usize) & 0x01; + val != 0 + } + #[doc = "Securable memory area protection enable"] + #[inline(always)] + pub fn set_sec_prot1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + } + #[doc = "Options Lock"] + #[inline(always)] + pub const fn optlock(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; + val != 0 + } + #[doc = "Options Lock"] + #[inline(always)] + pub fn set_optlock(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + } + #[doc = "FLASH_CR Lock"] + #[inline(always)] + pub const fn lock(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "FLASH_CR Lock"] + #[inline(always)] + pub fn set_lock(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } + } + impl Default for Cr { + #[inline(always)] + fn default() -> Cr { + Cr(0) + } + } + #[doc = "Flash ECC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Eccr(pub u32); + impl Eccr { + #[doc = "ECC fail address"] + #[inline(always)] + pub const fn addr_ecc(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x0007_ffff; + val as u32 + } + #[doc = "ECC fail address"] + #[inline(always)] + pub fn set_addr_ecc(&mut self, val: u32) { + self.0 = (self.0 & !(0x0007_ffff << 0usize)) | (((val as u32) & 0x0007_ffff) << 0usize); + } + #[doc = "ECC fail for Corrected ECC Error or Double ECC Error in info block"] + #[inline(always)] + pub const fn bk_ecc(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "ECC fail for Corrected ECC Error or Double ECC Error in info block"] + #[inline(always)] + pub fn set_bk_ecc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "ECC fail for Corrected ECC Error or Double ECC Error in info block"] + #[inline(always)] + pub const fn sysf_ecc(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "ECC fail for Corrected ECC Error or Double ECC Error in info block"] + #[inline(always)] + pub fn set_sysf_ecc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "ECC correction interrupt enable"] + #[inline(always)] + pub const fn eccie(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "ECC correction interrupt enable"] + #[inline(always)] + pub fn set_eccie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "ECC correction"] + #[inline(always)] + pub const fn eccc2(&self) -> bool { + let val = (self.0 >> 28usize) & 0x01; + val != 0 + } + #[doc = "ECC correction"] + #[inline(always)] + pub fn set_eccc2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + } + #[doc = "ECC2 detection"] + #[inline(always)] + pub const fn eccd2(&self) -> bool { + let val = (self.0 >> 29usize) & 0x01; + val != 0 + } + #[doc = "ECC2 detection"] + #[inline(always)] + pub fn set_eccd2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); + } + #[doc = "ECC correction"] + #[inline(always)] + pub const fn eccc(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; + val != 0 + } + #[doc = "ECC correction"] + #[inline(always)] + pub fn set_eccc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + } + #[doc = "ECC detection"] + #[inline(always)] + pub const fn eccd(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "ECC detection"] + #[inline(always)] + pub fn set_eccd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } + } + impl Default for Eccr { + #[inline(always)] + fn default() -> Eccr { + Eccr(0) + } + } + #[doc = "Flash option register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Optr(pub u32); + impl Optr { + #[doc = "Read protection level"] + #[inline(always)] + pub const fn rdp(&self) -> super::vals::Rdp { + let val = (self.0 >> 0usize) & 0xff; + super::vals::Rdp::from_bits(val as u8) + } + #[doc = "Read protection level"] + #[inline(always)] + pub fn set_rdp(&mut self, val: super::vals::Rdp) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); + } + #[doc = "BOR reset Level"] + #[inline(always)] + pub const fn bor_lev(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x07; + val as u8 + } + #[doc = "BOR reset Level"] + #[inline(always)] + pub fn set_bor_lev(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u32) & 0x07) << 8usize); + } + #[doc = "nRST_STOP"] + #[inline(always)] + pub const fn n_rst_stop(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "nRST_STOP"] + #[inline(always)] + pub fn set_n_rst_stop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "nRST_STDBY"] + #[inline(always)] + pub const fn n_rst_stdby(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "nRST_STDBY"] + #[inline(always)] + pub fn set_n_rst_stdby(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "nRST_SHDW"] + #[inline(always)] + pub const fn n_rst_shdw(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "nRST_SHDW"] + #[inline(always)] + pub fn set_n_rst_shdw(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Independent watchdog selection"] + #[inline(always)] + pub const fn idwg_sw(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Independent watchdog selection"] + #[inline(always)] + pub fn set_idwg_sw(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Independent watchdog counter freeze in Stop mode"] + #[inline(always)] + pub const fn iwdg_stop(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Independent watchdog counter freeze in Stop mode"] + #[inline(always)] + pub fn set_iwdg_stop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Independent watchdog counter freeze in Standby mode"] + #[inline(always)] + pub const fn iwdg_stdby(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Independent watchdog counter freeze in Standby mode"] + #[inline(always)] + pub fn set_iwdg_stdby(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Window watchdog selection"] + #[inline(always)] + pub const fn wwdg_sw(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Window watchdog selection"] + #[inline(always)] + pub fn set_wwdg_sw(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "PB4 pull-up enable"] + #[inline(always)] + pub const fn pb4_pupen(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "PB4 pull-up enable"] + #[inline(always)] + pub fn set_pb4_pupen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "Boot configuration"] + #[inline(always)] + pub const fn n_boot1(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Boot configuration"] + #[inline(always)] + pub fn set_n_boot1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "SRAM2 parity check enable"] + #[inline(always)] + pub const fn sram2_pe(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 parity check enable"] + #[inline(always)] + pub fn set_sram2_pe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "SRAM2 Erase when system reset"] + #[inline(always)] + pub const fn sram2_rst(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 Erase when system reset"] + #[inline(always)] + pub fn set_sram2_rst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "nSWBOOT0"] + #[inline(always)] + pub const fn n_swboot0(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "nSWBOOT0"] + #[inline(always)] + pub fn set_n_swboot0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "nBOOT0 option bit"] + #[inline(always)] + pub const fn n_boot0(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "nBOOT0 option bit"] + #[inline(always)] + pub fn set_n_boot0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } + #[doc = "NRST_MODE"] + #[inline(always)] + pub const fn nrst_mode(&self) -> super::vals::NrstMode { + let val = (self.0 >> 28usize) & 0x03; + super::vals::NrstMode::from_bits(val as u8) + } + #[doc = "NRST_MODE"] + #[inline(always)] + pub fn set_nrst_mode(&mut self, val: super::vals::NrstMode) { + self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); + } + #[doc = "Internal reset holder enable bit"] + #[inline(always)] + pub const fn irhen(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; + val != 0 + } + #[doc = "Internal reset holder enable bit"] + #[inline(always)] + pub fn set_irhen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + } + } + impl Default for Optr { + #[inline(always)] + fn default() -> Optr { + Optr(0) + } + } + #[doc = "Flash Bank 1 PCROP End address register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pcrop1er(pub u32); + impl Pcrop1er { + #[doc = "Bank 1 PCROP area end offset"] + #[inline(always)] + pub const fn pcrop1_end(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x7fff; + val as u16 + } + #[doc = "Bank 1 PCROP area end offset"] + #[inline(always)] + pub fn set_pcrop1_end(&mut self, val: u16) { + self.0 = (self.0 & !(0x7fff << 0usize)) | (((val as u32) & 0x7fff) << 0usize); + } + #[doc = "PCROP area preserved when RDP level decreased"] + #[inline(always)] + pub const fn pcrop_rdp(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "PCROP area preserved when RDP level decreased"] + #[inline(always)] + pub fn set_pcrop_rdp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } + } + impl Default for Pcrop1er { + #[inline(always)] + fn default() -> Pcrop1er { + Pcrop1er(0) + } + } + #[doc = "Flash Bank 1 PCROP Start address register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pcrop1sr(pub u32); + impl Pcrop1sr { + #[doc = "Bank 1 PCROP area start offset"] + #[inline(always)] + pub const fn pcrop1_strt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x7fff; + val as u16 + } + #[doc = "Bank 1 PCROP area start offset"] + #[inline(always)] + pub fn set_pcrop1_strt(&mut self, val: u16) { + self.0 = (self.0 & !(0x7fff << 0usize)) | (((val as u32) & 0x7fff) << 0usize); + } + } + impl Default for Pcrop1sr { + #[inline(always)] + fn default() -> Pcrop1sr { + Pcrop1sr(0) + } + } + #[doc = "securable area bank1 register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sec1r(pub u32); + impl Sec1r { + #[doc = "SEC_SIZE1"] + #[inline(always)] + pub const fn sec_size1(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "SEC_SIZE1"] + #[inline(always)] + pub fn set_sec_size1(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "used to force boot from user area"] + #[inline(always)] + pub const fn boot_lock(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "used to force boot from user area"] + #[inline(always)] + pub fn set_boot_lock(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Sec1r { + #[inline(always)] + fn default() -> Sec1r { + Sec1r(0) + } + } + #[doc = "Status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "End of operation"] + #[inline(always)] + pub const fn eop(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "End of operation"] + #[inline(always)] + pub fn set_eop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Operation error"] + #[inline(always)] + pub const fn operr(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Operation error"] + #[inline(always)] + pub fn set_operr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Programming error"] + #[inline(always)] + pub const fn progerr(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Programming error"] + #[inline(always)] + pub fn set_progerr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Write protected error"] + #[inline(always)] + pub const fn wrperr(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Write protected error"] + #[inline(always)] + pub fn set_wrperr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Programming alignment error"] + #[inline(always)] + pub const fn pgaerr(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Programming alignment error"] + #[inline(always)] + pub fn set_pgaerr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Size error"] + #[inline(always)] + pub const fn sizerr(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Size error"] + #[inline(always)] + pub fn set_sizerr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Programming sequence error"] + #[inline(always)] + pub const fn pgserr(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Programming sequence error"] + #[inline(always)] + pub fn set_pgserr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Fast programming data miss error"] + #[inline(always)] + pub const fn miserr(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Fast programming data miss error"] + #[inline(always)] + pub fn set_miserr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Fast programming error"] + #[inline(always)] + pub const fn fasterr(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Fast programming error"] + #[inline(always)] + pub fn set_fasterr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "PCROP read error"] + #[inline(always)] + pub const fn rderr(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "PCROP read error"] + #[inline(always)] + pub fn set_rderr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Option validity error"] + #[inline(always)] + pub const fn optverr(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Option validity error"] + #[inline(always)] + pub fn set_optverr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "Busy"] + #[inline(always)] + pub const fn bsy(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Busy"] + #[inline(always)] + pub fn set_bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Sr { + #[inline(always)] + fn default() -> Sr { + Sr(0) + } + } + #[doc = "Flash Bank 1 WRP area A address register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Wrp1ar(pub u32); + impl Wrp1ar { + #[doc = "Bank 1 WRP first area start offset"] + #[inline(always)] + pub const fn wrp1a_strt(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x7f; + val as u8 + } + #[doc = "Bank 1 WRP first area start offset"] + #[inline(always)] + pub fn set_wrp1a_strt(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize); + } + #[doc = "Bank 1 WRP first area A end offset"] + #[inline(always)] + pub const fn wrp1a_end(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x7f; + val as u8 + } + #[doc = "Bank 1 WRP first area A end offset"] + #[inline(always)] + pub fn set_wrp1a_end(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize); + } + } + impl Default for Wrp1ar { + #[inline(always)] + fn default() -> Wrp1ar { + Wrp1ar(0) + } + } + #[doc = "Flash Bank 1 WRP area B address register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Wrp1br(pub u32); + impl Wrp1br { + #[doc = "Bank 1 WRP second area B end offset"] + #[inline(always)] + pub const fn wrp1b_strt(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x7f; + val as u8 + } + #[doc = "Bank 1 WRP second area B end offset"] + #[inline(always)] + pub fn set_wrp1b_strt(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize); + } + #[doc = "Bank 1 WRP second area B start offset"] + #[inline(always)] + pub const fn wrp1b_end(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x7f; + val as u8 + } + #[doc = "Bank 1 WRP second area B start offset"] + #[inline(always)] + pub fn set_wrp1b_end(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize); + } + } + impl Default for Wrp1br { + #[inline(always)] + fn default() -> Wrp1br { + Wrp1br(0) + } + } +} +pub mod vals { + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Latency { + #[doc = "Zero wait states"] + WS0 = 0x0, + #[doc = "One wait state"] + WS1 = 0x01, + #[doc = "Two wait states"] + WS2 = 0x02, + #[doc = "Three wait states"] + WS3 = 0x03, + #[doc = "Four wait states"] + WS4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, + _RESERVED_8 = 0x08, + _RESERVED_9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, + } + impl Latency { + #[inline(always)] + pub const fn from_bits(val: u8) -> Latency { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Latency { + #[inline(always)] + fn from(val: u8) -> Latency { + Latency::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Latency) -> u8 { + Latency::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum NrstMode { + _RESERVED_0 = 0x0, + #[doc = "Reset pin is in reset input mode only"] + INPUT_ONLY = 0x01, + #[doc = "Reset pin is in GPIO mode only"] + GPIO = 0x02, + #[doc = "Reset pin is in reset input and output mode"] + INPUT_OUTPUT = 0x03, + } + impl NrstMode { + #[inline(always)] + pub const fn from_bits(val: u8) -> NrstMode { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for NrstMode { + #[inline(always)] + fn from(val: u8) -> NrstMode { + NrstMode::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: NrstMode) -> u8 { + NrstMode::to_bits(val) + } + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rdp(pub u8); + impl Rdp { + #[doc = "Read protection not active"] + pub const LEVEL_0: Self = Self(0xaa); + #[doc = "Memories read protection active"] + pub const LEVEL_1: Self = Self(0xbb); + #[doc = "Chip read protection active"] + pub const LEVEL_2: Self = Self(0xcc); + } + impl Rdp { + pub const fn from_bits(val: u8) -> Rdp { + Self(val & 0xff) + } + pub const fn to_bits(self) -> u8 { + self.0 + } + } + impl From for Rdp { + #[inline(always)] + fn from(val: u8) -> Rdp { + Rdp::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Rdp) -> u8 { + Rdp::to_bits(val) + } + } +} diff --git a/stm32-metapac/src/registers/flash_g4.rs b/stm32-metapac/src/registers/flash_g4c2.rs similarity index 100% rename from stm32-metapac/src/registers/flash_g4.rs rename to stm32-metapac/src/registers/flash_g4c2.rs diff --git a/stm32-metapac/src/registers/flash_g4c3.rs b/stm32-metapac/src/registers/flash_g4c3.rs new file mode 100644 index 0000000000..902ec0cab1 --- /dev/null +++ b/stm32-metapac/src/registers/flash_g4c3.rs @@ -0,0 +1,880 @@ + +use crate::metadata::ir::*; +pub(crate) static REGISTERS: IR = IR { + blocks: &[Block { + name: "Flash", + extends: None, + description: Some("Flash"), + items: &[ + BlockItem { + name: "acr", + description: Some("Access control register"), + array: None, + byte_offset: 0x0, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Acr"), + }), + }, + BlockItem { + name: "pdkeyr", + description: Some("Power down key register"), + array: None, + byte_offset: 0x4, + inner: BlockItemInner::Register(Register { + access: Access::Write, + bit_size: 32, + fieldset: None, + }), + }, + BlockItem { + name: "keyr", + description: Some("Flash key register"), + array: None, + byte_offset: 0x8, + inner: BlockItemInner::Register(Register { + access: Access::Write, + bit_size: 32, + fieldset: None, + }), + }, + BlockItem { + name: "optkeyr", + description: Some("Option byte key register"), + array: None, + byte_offset: 0xc, + inner: BlockItemInner::Register(Register { + access: Access::Write, + bit_size: 32, + fieldset: None, + }), + }, + BlockItem { + name: "sr", + description: Some("Status register"), + array: None, + byte_offset: 0x10, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Sr"), + }), + }, + BlockItem { + name: "cr", + description: Some("Flash control register"), + array: None, + byte_offset: 0x14, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Cr"), + }), + }, + BlockItem { + name: "eccr", + description: Some("Flash ECC register"), + array: None, + byte_offset: 0x18, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Eccr"), + }), + }, + BlockItem { + name: "optr", + description: Some("Flash option register"), + array: None, + byte_offset: 0x20, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Optr"), + }), + }, + BlockItem { + name: "pcrop1sr", + description: Some("Flash Bank 1 PCROP Start address register"), + array: None, + byte_offset: 0x24, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Pcrop1sr"), + }), + }, + BlockItem { + name: "pcrop1er", + description: Some("Flash Bank 1 PCROP End address register"), + array: None, + byte_offset: 0x28, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Pcrop1er"), + }), + }, + BlockItem { + name: "wrp1ar", + description: Some("Flash Bank 1 WRP area A address register"), + array: None, + byte_offset: 0x2c, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Wrp1ar"), + }), + }, + BlockItem { + name: "wrp1br", + description: Some("Flash Bank 1 WRP area B address register"), + array: None, + byte_offset: 0x30, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Wrp1br"), + }), + }, + BlockItem { + name: "sec1r", + description: Some("securable area bank1 register"), + array: None, + byte_offset: 0x70, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Sec1r"), + }), + }, + ], + }], + fieldsets: &[ + FieldSet { + name: "Acr", + extends: None, + description: Some("Access control register"), + bit_size: 32, + fields: &[ + Field { + name: "latency", + description: Some("Latency"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 4, + array: None, + enumm: Some("Latency"), + }, + Field { + name: "prften", + description: Some("Prefetch enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "icen", + description: Some("Instruction cache enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "dcen", + description: Some("Data cache enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "icrst", + description: Some("Instruction cache reset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "dcrst", + description: Some("Data cache reset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "run_pd", + description: Some("Flash Power-down mode during Low-power run mode"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sleep_pd", + description: Some("Flash Power-down mode during Low-power sleep mode"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "dbg_swen", + description: Some("Debug software enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Cr", + extends: None, + description: Some("Flash control register"), + bit_size: 32, + fields: &[ + Field { + name: "pg", + description: Some("Programming"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "per", + description: Some("Page erase"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "mer1", + description: Some("Bank 1 Mass erase"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "pnb", + description: Some("Page number"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }), + bit_size: 7, + array: None, + enumm: None, + }, + Field { + name: "mer2", + description: Some("Bank 2 Mass erase"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "strt", + description: Some("Start"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "optstrt", + description: Some("Options modification start"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "fstpg", + description: Some("Fast programming"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "eopie", + description: Some("End of operation interrupt enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "errie", + description: Some("Error interrupt enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "rderrie", + description: Some("PCROP read error interrupt enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 26 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "obl_launch", + description: Some("Force the option byte loading"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 27 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sec_prot1", + description: Some("Securable memory area protection enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "optlock", + description: Some("Options Lock"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 30 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "lock", + description: Some("FLASH_CR Lock"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Eccr", + extends: None, + description: Some("Flash ECC register"), + bit_size: 32, + fields: &[ + Field { + name: "addr_ecc", + description: Some("ECC fail address"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 19, + array: None, + enumm: None, + }, + Field { + name: "bk_ecc", + description: Some("ECC fail for Corrected ECC Error or Double ECC Error in info block"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 21 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sysf_ecc", + description: Some("ECC fail for Corrected ECC Error or Double ECC Error in info block"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "eccie", + description: Some("ECC correction interrupt enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "eccc2", + description: Some("ECC correction"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "eccd2", + description: Some("ECC2 detection"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 29 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "eccc", + description: Some("ECC correction"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 30 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "eccd", + description: Some("ECC detection"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Optr", + extends: None, + description: Some("Flash option register"), + bit_size: 32, + fields: &[ + Field { + name: "rdp", + description: Some("Read protection level"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 8, + array: None, + enumm: Some("Rdp"), + }, + Field { + name: "bor_lev", + description: Some("BOR reset Level"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }), + bit_size: 3, + array: None, + enumm: None, + }, + Field { + name: "n_rst_stop", + description: Some("nRST_STOP"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "n_rst_stdby", + description: Some("nRST_STDBY"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "n_rst_shdw", + description: Some("nRST_SHDW"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "idwg_sw", + description: Some("Independent watchdog selection"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "iwdg_stop", + description: Some("Independent watchdog counter freeze in Stop mode"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "iwdg_stdby", + description: Some("Independent watchdog counter freeze in Standby mode"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "wwdg_sw", + description: Some("Window watchdog selection"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 19 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "bfb2", + description: Some("Dual bank boot"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "dbank", + description: Some("Dual bank memory mode"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "n_boot1", + description: Some("Boot configuration"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 23 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sram2_pe", + description: Some("SRAM2 parity check enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sram2_rst", + description: Some("SRAM2 Erase when system reset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "n_swboot0", + description: Some("nSWBOOT0"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 26 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "n_boot0", + description: Some("nBOOT0 option bit"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 27 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "nrst_mode", + description: Some("NRST_MODE"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }), + bit_size: 2, + array: None, + enumm: Some("NrstMode"), + }, + Field { + name: "irhen", + description: Some("Internal reset holder enable bit"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 30 }), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Pcrop1er", + extends: None, + description: Some("Flash Bank 1 PCROP End address register"), + bit_size: 32, + fields: &[ + Field { + name: "pcrop1_end", + description: Some("Bank 1 PCROP area end offset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 15, + array: None, + enumm: None, + }, + Field { + name: "pcrop_rdp", + description: Some("PCROP area preserved when RDP level decreased"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Pcrop1sr", + extends: None, + description: Some("Flash Bank 1 PCROP Start address register"), + bit_size: 32, + fields: &[Field { + name: "pcrop1_strt", + description: Some("Bank 1 PCROP area start offset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 15, + array: None, + enumm: None, + }], + }, + FieldSet { + name: "Sec1r", + extends: None, + description: Some("securable area bank1 register"), + bit_size: 32, + fields: &[ + Field { + name: "sec_size1", + description: Some("SEC_SIZE1"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 8, + array: None, + enumm: None, + }, + Field { + name: "boot_lock", + description: Some("used to force boot from user area"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Sr", + extends: None, + description: Some("Status register"), + bit_size: 32, + fields: &[ + Field { + name: "eop", + description: Some("End of operation"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "operr", + description: Some("Operation error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "progerr", + description: Some("Programming error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "wrperr", + description: Some("Write protected error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "pgaerr", + description: Some("Programming alignment error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sizerr", + description: Some("Size error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "pgserr", + description: Some("Programming sequence error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "miserr", + description: Some("Fast programming data miss error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "fasterr", + description: Some("Fast programming error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "rderr", + description: Some("PCROP read error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "optverr", + description: Some("Option validity error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "bsy", + description: Some("Busy"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Wrp1ar", + extends: None, + description: Some("Flash Bank 1 WRP area A address register"), + bit_size: 32, + fields: &[ + Field { + name: "wrp1a_strt", + description: Some("Bank 1 WRP first area start offset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 7, + array: None, + enumm: None, + }, + Field { + name: "wrp1a_end", + description: Some("Bank 1 WRP first area A end offset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }), + bit_size: 7, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Wrp1br", + extends: None, + description: Some("Flash Bank 1 WRP area B address register"), + bit_size: 32, + fields: &[ + Field { + name: "wrp1b_strt", + description: Some("Bank 1 WRP second area B end offset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 7, + array: None, + enumm: None, + }, + Field { + name: "wrp1b_end", + description: Some("Bank 1 WRP second area B start offset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }), + bit_size: 7, + array: None, + enumm: None, + }, + ], + }, + ], + enums: &[ + Enum { + name: "Latency", + description: None, + bit_size: 4, + variants: &[ + EnumVariant { + name: "WS0", + description: Some("Zero wait states"), + value: 0, + }, + EnumVariant { + name: "WS1", + description: Some("One wait state"), + value: 1, + }, + EnumVariant { + name: "WS2", + description: Some("Two wait states"), + value: 2, + }, + EnumVariant { + name: "WS3", + description: Some("Three wait states"), + value: 3, + }, + EnumVariant { + name: "WS4", + description: Some("Four wait states"), + value: 4, + }, + ], + }, + Enum { + name: "NrstMode", + description: None, + bit_size: 2, + variants: &[ + EnumVariant { + name: "INPUT_ONLY", + description: Some("Reset pin is in reset input mode only"), + value: 1, + }, + EnumVariant { + name: "GPIO", + description: Some("Reset pin is in GPIO mode only"), + value: 2, + }, + EnumVariant { + name: "INPUT_OUTPUT", + description: Some("Reset pin is in reset input and output mode"), + value: 3, + }, + ], + }, + Enum { + name: "Rdp", + description: None, + bit_size: 8, + variants: &[ + EnumVariant { + name: "LEVEL_0", + description: Some("Read protection not active"), + value: 170, + }, + EnumVariant { + name: "LEVEL_1", + description: Some("Memories read protection active"), + value: 187, + }, + EnumVariant { + name: "LEVEL_2", + description: Some("Chip read protection active"), + value: 204, + }, + ], + }, + ], +}; diff --git a/stm32-metapac/src/registers/flash_g4c4.rs b/stm32-metapac/src/registers/flash_g4c4.rs new file mode 100644 index 0000000000..34c5f20c74 --- /dev/null +++ b/stm32-metapac/src/registers/flash_g4c4.rs @@ -0,0 +1,864 @@ + +use crate::metadata::ir::*; +pub(crate) static REGISTERS: IR = IR { + blocks: &[Block { + name: "Flash", + extends: None, + description: Some("Flash"), + items: &[ + BlockItem { + name: "acr", + description: Some("Access control register"), + array: None, + byte_offset: 0x0, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Acr"), + }), + }, + BlockItem { + name: "pdkeyr", + description: Some("Power down key register"), + array: None, + byte_offset: 0x4, + inner: BlockItemInner::Register(Register { + access: Access::Write, + bit_size: 32, + fieldset: None, + }), + }, + BlockItem { + name: "keyr", + description: Some("Flash key register"), + array: None, + byte_offset: 0x8, + inner: BlockItemInner::Register(Register { + access: Access::Write, + bit_size: 32, + fieldset: None, + }), + }, + BlockItem { + name: "optkeyr", + description: Some("Option byte key register"), + array: None, + byte_offset: 0xc, + inner: BlockItemInner::Register(Register { + access: Access::Write, + bit_size: 32, + fieldset: None, + }), + }, + BlockItem { + name: "sr", + description: Some("Status register"), + array: None, + byte_offset: 0x10, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Sr"), + }), + }, + BlockItem { + name: "cr", + description: Some("Flash control register"), + array: None, + byte_offset: 0x14, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Cr"), + }), + }, + BlockItem { + name: "eccr", + description: Some("Flash ECC register"), + array: None, + byte_offset: 0x18, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Eccr"), + }), + }, + BlockItem { + name: "optr", + description: Some("Flash option register"), + array: None, + byte_offset: 0x20, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Optr"), + }), + }, + BlockItem { + name: "pcrop1sr", + description: Some("Flash Bank 1 PCROP Start address register"), + array: None, + byte_offset: 0x24, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Pcrop1sr"), + }), + }, + BlockItem { + name: "pcrop1er", + description: Some("Flash Bank 1 PCROP End address register"), + array: None, + byte_offset: 0x28, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Pcrop1er"), + }), + }, + BlockItem { + name: "wrp1ar", + description: Some("Flash Bank 1 WRP area A address register"), + array: None, + byte_offset: 0x2c, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Wrp1ar"), + }), + }, + BlockItem { + name: "wrp1br", + description: Some("Flash Bank 1 WRP area B address register"), + array: None, + byte_offset: 0x30, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Wrp1br"), + }), + }, + BlockItem { + name: "sec1r", + description: Some("securable area bank1 register"), + array: None, + byte_offset: 0x70, + inner: BlockItemInner::Register(Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some("Sec1r"), + }), + }, + ], + }], + fieldsets: &[ + FieldSet { + name: "Acr", + extends: None, + description: Some("Access control register"), + bit_size: 32, + fields: &[ + Field { + name: "latency", + description: Some("Latency"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 4, + array: None, + enumm: Some("Latency"), + }, + Field { + name: "prften", + description: Some("Prefetch enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "icen", + description: Some("Instruction cache enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "dcen", + description: Some("Data cache enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "icrst", + description: Some("Instruction cache reset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "dcrst", + description: Some("Data cache reset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "run_pd", + description: Some("Flash Power-down mode during Low-power run mode"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sleep_pd", + description: Some("Flash Power-down mode during Low-power sleep mode"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "dbg_swen", + description: Some("Debug software enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Cr", + extends: None, + description: Some("Flash control register"), + bit_size: 32, + fields: &[ + Field { + name: "pg", + description: Some("Programming"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "per", + description: Some("Page erase"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "mer1", + description: Some("Bank 1 Mass erase"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "pnb", + description: Some("Page number"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }), + bit_size: 7, + array: None, + enumm: None, + }, + Field { + name: "strt", + description: Some("Start"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "optstrt", + description: Some("Options modification start"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "fstpg", + description: Some("Fast programming"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "eopie", + description: Some("End of operation interrupt enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "errie", + description: Some("Error interrupt enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "rderrie", + description: Some("PCROP read error interrupt enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 26 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "obl_launch", + description: Some("Force the option byte loading"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 27 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sec_prot1", + description: Some("Securable memory area protection enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "optlock", + description: Some("Options Lock"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 30 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "lock", + description: Some("FLASH_CR Lock"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Eccr", + extends: None, + description: Some("Flash ECC register"), + bit_size: 32, + fields: &[ + Field { + name: "addr_ecc", + description: Some("ECC fail address"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 19, + array: None, + enumm: None, + }, + Field { + name: "bk_ecc", + description: Some("ECC fail for Corrected ECC Error or Double ECC Error in info block"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 21 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sysf_ecc", + description: Some("ECC fail for Corrected ECC Error or Double ECC Error in info block"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "eccie", + description: Some("ECC correction interrupt enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "eccc2", + description: Some("ECC correction"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "eccd2", + description: Some("ECC2 detection"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 29 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "eccc", + description: Some("ECC correction"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 30 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "eccd", + description: Some("ECC detection"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Optr", + extends: None, + description: Some("Flash option register"), + bit_size: 32, + fields: &[ + Field { + name: "rdp", + description: Some("Read protection level"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 8, + array: None, + enumm: Some("Rdp"), + }, + Field { + name: "bor_lev", + description: Some("BOR reset Level"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }), + bit_size: 3, + array: None, + enumm: None, + }, + Field { + name: "n_rst_stop", + description: Some("nRST_STOP"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "n_rst_stdby", + description: Some("nRST_STDBY"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "n_rst_shdw", + description: Some("nRST_SHDW"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "idwg_sw", + description: Some("Independent watchdog selection"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "iwdg_stop", + description: Some("Independent watchdog counter freeze in Stop mode"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "iwdg_stdby", + description: Some("Independent watchdog counter freeze in Standby mode"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "wwdg_sw", + description: Some("Window watchdog selection"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 19 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "pb4_pupen", + description: Some("PB4 pull-up enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "n_boot1", + description: Some("Boot configuration"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 23 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sram2_pe", + description: Some("SRAM2 parity check enable"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sram2_rst", + description: Some("SRAM2 Erase when system reset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "n_swboot0", + description: Some("nSWBOOT0"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 26 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "n_boot0", + description: Some("nBOOT0 option bit"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 27 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "nrst_mode", + description: Some("NRST_MODE"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }), + bit_size: 2, + array: None, + enumm: Some("NrstMode"), + }, + Field { + name: "irhen", + description: Some("Internal reset holder enable bit"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 30 }), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Pcrop1er", + extends: None, + description: Some("Flash Bank 1 PCROP End address register"), + bit_size: 32, + fields: &[ + Field { + name: "pcrop1_end", + description: Some("Bank 1 PCROP area end offset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 15, + array: None, + enumm: None, + }, + Field { + name: "pcrop_rdp", + description: Some("PCROP area preserved when RDP level decreased"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Pcrop1sr", + extends: None, + description: Some("Flash Bank 1 PCROP Start address register"), + bit_size: 32, + fields: &[Field { + name: "pcrop1_strt", + description: Some("Bank 1 PCROP area start offset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 15, + array: None, + enumm: None, + }], + }, + FieldSet { + name: "Sec1r", + extends: None, + description: Some("securable area bank1 register"), + bit_size: 32, + fields: &[ + Field { + name: "sec_size1", + description: Some("SEC_SIZE1"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 8, + array: None, + enumm: None, + }, + Field { + name: "boot_lock", + description: Some("used to force boot from user area"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Sr", + extends: None, + description: Some("Status register"), + bit_size: 32, + fields: &[ + Field { + name: "eop", + description: Some("End of operation"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "operr", + description: Some("Operation error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "progerr", + description: Some("Programming error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "wrperr", + description: Some("Write protected error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "pgaerr", + description: Some("Programming alignment error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sizerr", + description: Some("Size error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "pgserr", + description: Some("Programming sequence error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "miserr", + description: Some("Fast programming data miss error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "fasterr", + description: Some("Fast programming error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "rderr", + description: Some("PCROP read error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "optverr", + description: Some("Option validity error"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "bsy", + description: Some("Busy"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Wrp1ar", + extends: None, + description: Some("Flash Bank 1 WRP area A address register"), + bit_size: 32, + fields: &[ + Field { + name: "wrp1a_strt", + description: Some("Bank 1 WRP first area start offset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 7, + array: None, + enumm: None, + }, + Field { + name: "wrp1a_end", + description: Some("Bank 1 WRP first area A end offset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }), + bit_size: 7, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Wrp1br", + extends: None, + description: Some("Flash Bank 1 WRP area B address register"), + bit_size: 32, + fields: &[ + Field { + name: "wrp1b_strt", + description: Some("Bank 1 WRP second area B end offset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), + bit_size: 7, + array: None, + enumm: None, + }, + Field { + name: "wrp1b_end", + description: Some("Bank 1 WRP second area B start offset"), + bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }), + bit_size: 7, + array: None, + enumm: None, + }, + ], + }, + ], + enums: &[ + Enum { + name: "Latency", + description: None, + bit_size: 4, + variants: &[ + EnumVariant { + name: "WS0", + description: Some("Zero wait states"), + value: 0, + }, + EnumVariant { + name: "WS1", + description: Some("One wait state"), + value: 1, + }, + EnumVariant { + name: "WS2", + description: Some("Two wait states"), + value: 2, + }, + EnumVariant { + name: "WS3", + description: Some("Three wait states"), + value: 3, + }, + EnumVariant { + name: "WS4", + description: Some("Four wait states"), + value: 4, + }, + ], + }, + Enum { + name: "NrstMode", + description: None, + bit_size: 2, + variants: &[ + EnumVariant { + name: "INPUT_ONLY", + description: Some("Reset pin is in reset input mode only"), + value: 1, + }, + EnumVariant { + name: "GPIO", + description: Some("Reset pin is in GPIO mode only"), + value: 2, + }, + EnumVariant { + name: "INPUT_OUTPUT", + description: Some("Reset pin is in reset input and output mode"), + value: 3, + }, + ], + }, + Enum { + name: "Rdp", + description: None, + bit_size: 8, + variants: &[ + EnumVariant { + name: "LEVEL_0", + description: Some("Read protection not active"), + value: 170, + }, + EnumVariant { + name: "LEVEL_1", + description: Some("Memories read protection active"), + value: 187, + }, + EnumVariant { + name: "LEVEL_2", + description: Some("Chip read protection active"), + value: 204, + }, + ], + }, + ], +};