From 1a3d47466552169caecbd0c5757d7eae8c28e0cb Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 13 May 2024 16:26:50 +0200
Subject: [PATCH] phy: Simplify Clk/CE generation.

---
 litesdcard/phy.py | 25 +++++++++++++------------
 test/test_phy.py  |  8 ++++----
 2 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/litesdcard/phy.py b/litesdcard/phy.py
index 7198514..e4cabf5 100644
--- a/litesdcard/phy.py
+++ b/litesdcard/phy.py
@@ -46,21 +46,22 @@ def __init__(self):
 
         # # #
 
-        # Generate divided versions of sys_clk that will be used as SDCard clk.
-        clks = Signal(9)
-        self.sync += If(~self.stop, clks.eq(clks + 1))
-
-        # Generate delayed version of the SDCard clk (to do specific actions on change).
+        # SDCard Clk Divider Generation.
         clk   = Signal()
+        count = Signal(10)
+        self.sync += [
+            If(~self.stop,
+                count.eq(count + 1),
+                If(count >= (self.divider.storage[1:] - 1),
+                    clk.eq(~clk),
+                    count.eq(0),
+                )
+            )
+        ]
+
+        # SDCard CE Generation.
         clk_d = Signal()
         self.sync += clk_d.eq(clk)
-
-        # Select SDCard clk based on divider CSR value.
-        cases = {}
-        cases["default"] = clk.eq(clks[0])
-        for i in range(2, 9):
-            cases[2**i] = clk.eq(clks[i-1])
-        self.sync += Case(self.divider.storage, cases)
         self.sync += self.ce.eq(clk & ~clk_d)
 
         # Ensure we don't get short pulses on the SDCard Clk.
diff --git a/test/test_phy.py b/test/test_phy.py
index 1817460..2e09422 100644
--- a/test/test_phy.py
+++ b/test/test_phy.py
@@ -30,8 +30,8 @@ def gen(dut):
     def test_clocker_div4(self):
         def gen(dut):
             yield dut.divider.storage.eq(4)
-            clk   = "______--__--__--__-"
-            ce    = "____-___-___-___-__"
+            clk   = "_____--__--__--__-"
+            ce    = "___-___-___-___-__"
             for i in range(len(clk)):
                 self.assertEqual(c2bool(clk[i]),   (yield dut.clk))
                 self.assertEqual(c2bool(ce[i]),    (yield dut.ce))
@@ -42,8 +42,8 @@ def gen(dut):
     def test_clocker_div8(self):
         def gen(dut):
             yield dut.divider.storage.eq(8)
-            clk   = "__________----____----"
-            ce    = "______-_______-_______"
+            clk   = "_________----____----"
+            ce    = "_____-_______-_______"
             for i in range(len(clk)):
                 self.assertEqual(c2bool(clk[i]),   (yield dut.clk))
                 self.assertEqual(c2bool(ce[i]),    (yield dut.ce))