From a3d174a5f6a8da6887f4a01ea72f56a60ae3dd15 Mon Sep 17 00:00:00 2001 From: Eric Richter Date: Tue, 19 Sep 2023 14:00:29 -0500 Subject: [PATCH] cpu-ppc.c: derive ppc64le assembly entry points from ppccap.c The powerpc64le assembly implementations for certain algorithms are not directly callable, unlike on other architectures. Therefore, they require a small amount of preprocessing handled by some C code. This commit adds a new file derived from OpenSSL's 'ppccap.c', which provides the expected entry point functions. This commit is also derived from the original ppc64 support pull request by q66: https://github.com/briansmith/ring/pull/819 I agree to license my contributions to each file under the terms given at the top of each file I changed. --- crypto/cpu-ppc.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 crypto/cpu-ppc.c diff --git a/crypto/cpu-ppc.c b/crypto/cpu-ppc.c new file mode 100644 index 0000000000..64f87b2b73 --- /dev/null +++ b/crypto/cpu-ppc.c @@ -0,0 +1,37 @@ +/* + * Copyright 2009-2018 The OpenSSL Project Authors. All Rights Reserved. + * + * Licensed under the Apache License 2.0 (the "License"). You may not use + * this file except in compliance with the License. You can obtain a copy + * in the file LICENSE in the source distribution or at + * https://www.openssl.org/source/license.html + */ +/* This file is derived from ppccap.c in OpenSSL */ + + + +int bn_mul_mont_int(unsigned long *rp, const unsigned long *ap, const unsigned long *bp, + const unsigned long *np, const unsigned long *n0, int num); +int bn_mul4x_mont_int(unsigned long *rp, const unsigned long *ap, const unsigned long *bp, + const unsigned long *np, const unsigned long *n0, int num); +int GFp_bn_mul_mont(unsigned long *rp, const unsigned long *ap, const unsigned long *bp, + const unsigned long *np, const unsigned long *n0, int num) +{ + if (num < 4) + return 0; + + if ((num & 3) == 0) + return bn_mul4x_mont_int(rp, ap, bp, np, n0, num); + + /* + * There used to be [optional] call to bn_mul_mont_fpu64 here, + * but above subroutine is faster on contemporary processors. + * Formulation means that there might be old processors where + * FPU code path would be faster, POWER6 perhaps, but there was + * no opportunity to figure it out... + */ + + return bn_mul_mont_int(rp, ap, bp, np, n0, num); +} + +