From e199adad4093fcedd29d61eb3d8e5a2b23d1cee1 Mon Sep 17 00:00:00 2001 From: bjoernQ Date: Tue, 14 Mar 2023 13:14:49 +0100 Subject: [PATCH] Remove r0 dependency --- esp-hal-common/Cargo.toml | 9 +++-- esp32c2-hal/Cargo.toml | 3 +- esp32c2-hal/ld/bl-riscv-link.x | 5 +-- esp32c2-hal/ld/db-riscv-link.x | 5 +-- esp32c2-hal/src/lib.rs | 33 ------------------ esp32c3-hal/Cargo.toml | 5 ++- esp32c3-hal/ld/bl-riscv-link.x | 5 +-- esp32c3-hal/ld/db-riscv-link.x | 5 +-- esp32c3-hal/ld/mb-riscv-link.x | 5 +-- esp32c3-hal/src/lib.rs | 56 ++----------------------------- esp32c6-hal/Cargo.toml | 5 ++- esp32c6-hal/ld/bl-riscv-link.x | 5 +-- esp32c6-hal/ld/db-riscv-link.x | 5 +-- esp32c6-hal/src/lib.rs | 61 ---------------------------------- 14 files changed, 21 insertions(+), 186 deletions(-) diff --git a/esp-hal-common/Cargo.toml b/esp-hal-common/Cargo.toml index 3e48ae875b0..dd0374b30a5 100644 --- a/esp-hal-common/Cargo.toml +++ b/esp-hal-common/Cargo.toml @@ -36,7 +36,7 @@ embassy-time = { version = "0.1.0", features = ["nightly"], optional = tru embassy-futures = { version = "0.1.0", optional = true } # RISC-V -esp-riscv-rt = { version = "0.1.0", optional = true } +esp-riscv-rt = { version = "0.2.0", optional = true } riscv-atomic-emulation-trap = { version = "0.4.0", optional = true } # Xtensa @@ -87,5 +87,10 @@ embassy-time-systick = [] embassy-time-timg0 = [] # Architecture-specific features (intended for internal use) -riscv = ["critical-section/restore-state-u8", "procmacros/riscv", "esp-riscv-rt", "riscv-atomic-emulation-trap"] +riscv = ["critical-section/restore-state-u8", "procmacros/riscv", "esp-riscv-rt", "riscv-atomic-emulation-trap", "esp-riscv-rt/zero-bss"] xtensa = ["critical-section/restore-state-u32", "procmacros/xtensa"] + +# Initialize / clear data sections and RTC memory +rv-init-data = ["esp-riscv-rt/init-data", "esp-riscv-rt/init-rw-text"] +rv-zero-rtc-bss = ["esp-riscv-rt/zero-rtc-fast-bss"] +rv-init-rtc-data = ["esp-riscv-rt/init-rtc-fast-data", "esp-riscv-rt/init-rtc-fast-text"] diff --git a/esp32c2-hal/Cargo.toml b/esp32c2-hal/Cargo.toml index ce3411ba697..4756adb1b4b 100644 --- a/esp32c2-hal/Cargo.toml +++ b/esp32c2-hal/Cargo.toml @@ -31,7 +31,6 @@ embedded-hal-1 = { version = "=1.0.0-alpha.9", optional = true, package = "e embedded-hal-async = { version = "0.2.0-alpha.0", optional = true } embedded-hal-nb = { version = "=1.0.0-alpha.1", optional = true } esp-hal-common = { version = "0.7.0", features = ["esp32c2"], path = "../esp-hal-common" } -r0 = "1.0.0" [dev-dependencies] critical-section = "1.1.1" @@ -45,7 +44,7 @@ static_cell = "1.0.0" [features] default = ["rt", "vectored", "xtal40mhz"] -direct-boot = [] +direct-boot = ["esp-hal-common/rv-init-data"] eh1 = ["esp-hal-common/eh1", "dep:embedded-hal-1", "dep:embedded-hal-nb"] rt = [] ufmt = ["esp-hal-common/ufmt"] diff --git a/esp32c2-hal/ld/bl-riscv-link.x b/esp32c2-hal/ld/bl-riscv-link.x index bef55369e6d..2245624714f 100644 --- a/esp32c2-hal/ld/bl-riscv-link.x +++ b/esp32c2-hal/ld/bl-riscv-link.x @@ -19,10 +19,7 @@ PROVIDE(MachineExternal = DefaultHandler); PROVIDE(DefaultHandler = DefaultInterruptHandler); PROVIDE(ExceptionHandler = DefaultExceptionHandler); -/* # Pre-initialization function */ -/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function, - then the function this points to will be called before the RAM is initialized. */ -PROVIDE(__pre_init = default_pre_init); +PROVIDE(__post_init = default_post_init); /* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */ PROVIDE(_setup_interrupts = default_setup_interrupts); diff --git a/esp32c2-hal/ld/db-riscv-link.x b/esp32c2-hal/ld/db-riscv-link.x index 58517c5013b..54387bfd6d2 100644 --- a/esp32c2-hal/ld/db-riscv-link.x +++ b/esp32c2-hal/ld/db-riscv-link.x @@ -19,10 +19,7 @@ PROVIDE(MachineExternal = DefaultHandler); PROVIDE(DefaultHandler = DefaultInterruptHandler); PROVIDE(ExceptionHandler = DefaultExceptionHandler); -/* # Pre-initialization function */ -/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function, - then the function this points to will be called before the RAM is initialized. */ -PROVIDE(__pre_init = default_pre_init); +PROVIDE(__post_init = default_post_init); /* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */ PROVIDE(_setup_interrupts = default_setup_interrupts); diff --git a/esp32c2-hal/src/lib.rs b/esp32c2-hal/src/lib.rs index 33bf5b086ce..084343220c2 100644 --- a/esp32c2-hal/src/lib.rs +++ b/esp32c2-hal/src/lib.rs @@ -12,36 +12,3 @@ pub use self::gpio::IO; pub mod analog { pub use esp_hal_common::analog::{AvailableAnalog, SarAdcExt}; } - -extern "C" { - // Boundaries of the .iram section - static mut _srwtext: u32; - static mut _erwtext: u32; - static mut _irwtext: u32; - - // Boundaries of the .bss section - static mut _ebss: u32; - static mut _sbss: u32; -} - -#[cfg(feature = "direct-boot")] -#[doc(hidden)] -#[esp_hal_common::esp_riscv_rt::pre_init] -unsafe fn init() { - r0::init_data(&mut _srwtext, &mut _erwtext, &_irwtext); -} - -#[allow(unreachable_code)] -#[export_name = "_mp_hook"] -#[doc(hidden)] -pub fn mp_hook() -> bool { - if cfg!(feature = "direct-boot") { - true - } else { - unsafe { - r0::zero_bss(&mut _sbss, &mut _ebss); - } - - false - } -} diff --git a/esp32c3-hal/Cargo.toml b/esp32c3-hal/Cargo.toml index e21c153bc5a..ec4cd52e7b2 100644 --- a/esp32c3-hal/Cargo.toml +++ b/esp32c3-hal/Cargo.toml @@ -33,7 +33,6 @@ embedded-hal-async = { version = "0.2.0-alpha.0", optional = true } embedded-hal-nb = { version = "=1.0.0-alpha.1", optional = true } embedded-can = { version = "0.4.1", optional = true } esp-hal-common = { version = "0.7.0", features = ["esp32c3"], path = "../esp-hal-common" } -r0 = "1.0.0" [dev-dependencies] aes = "0.8.2" @@ -49,9 +48,9 @@ ssd1306 = "0.7.1" static_cell = "1.0.0" [features] -default = ["rt", "vectored"] +default = ["rt", "vectored", "esp-hal-common/rv-zero-rtc-bss"] mcu-boot = [] -direct-boot = [] +direct-boot = ["esp-hal-common/rv-init-data", "esp-hal-common/rv-init-rtc-data"] eh1 = ["esp-hal-common/eh1", "dep:embedded-hal-1", "dep:embedded-hal-nb", "dep:embedded-can"] rt = [] ufmt = ["esp-hal-common/ufmt"] diff --git a/esp32c3-hal/ld/bl-riscv-link.x b/esp32c3-hal/ld/bl-riscv-link.x index 9f4f10f5c5a..fc698d099fd 100644 --- a/esp32c3-hal/ld/bl-riscv-link.x +++ b/esp32c3-hal/ld/bl-riscv-link.x @@ -19,10 +19,7 @@ PROVIDE(MachineExternal = DefaultHandler); PROVIDE(DefaultHandler = DefaultInterruptHandler); PROVIDE(ExceptionHandler = DefaultExceptionHandler); -/* # Pre-initialization function */ -/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function, - then the function this points to will be called before the RAM is initialized. */ -PROVIDE(__pre_init = default_pre_init); +PROVIDE(__post_init = default_post_init); /* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */ PROVIDE(_setup_interrupts = default_setup_interrupts); diff --git a/esp32c3-hal/ld/db-riscv-link.x b/esp32c3-hal/ld/db-riscv-link.x index 06fce2b8617..cafb517b723 100644 --- a/esp32c3-hal/ld/db-riscv-link.x +++ b/esp32c3-hal/ld/db-riscv-link.x @@ -19,10 +19,7 @@ PROVIDE(MachineExternal = DefaultHandler); PROVIDE(DefaultHandler = DefaultInterruptHandler); PROVIDE(ExceptionHandler = DefaultExceptionHandler); -/* # Pre-initialization function */ -/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function, - then the function this points to will be called before the RAM is initialized. */ -PROVIDE(__pre_init = default_pre_init); +PROVIDE(__post_init = default_post_init); /* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */ PROVIDE(_setup_interrupts = default_setup_interrupts); diff --git a/esp32c3-hal/ld/mb-riscv-link.x b/esp32c3-hal/ld/mb-riscv-link.x index 869f95e14da..a602daf1c15 100644 --- a/esp32c3-hal/ld/mb-riscv-link.x +++ b/esp32c3-hal/ld/mb-riscv-link.x @@ -18,10 +18,7 @@ PROVIDE(MachineExternal = DefaultHandler); PROVIDE(DefaultHandler = DefaultInterruptHandler); PROVIDE(ExceptionHandler = DefaultExceptionHandler); -/* # Pre-initialization function */ -/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function, - then the function this points to will be called before the RAM is initialized. */ -PROVIDE(__pre_init = default_pre_init); +PROVIDE(__post_init = default_post_init); /* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */ PROVIDE(_setup_interrupts = default_setup_interrupts); diff --git a/esp32c3-hal/src/lib.rs b/esp32c3-hal/src/lib.rs index 0a6d94196cb..b0f20af7ff7 100644 --- a/esp32c3-hal/src/lib.rs +++ b/esp32c3-hal/src/lib.rs @@ -62,29 +62,6 @@ extern "C" { static mut _image_drom_size: u32; } } - - // Boundaries of the .iram section - static mut _srwtext: u32; - static mut _erwtext: u32; - static mut _irwtext: u32; - - // Boundaries of the .bss section - static mut _ebss: u32; - static mut _sbss: u32; - - // Boundaries of the rtc .bss section - static mut _rtc_fast_bss_start: u32; - static mut _rtc_fast_bss_end: u32; - - // Boundaries of the .rtc_fast.text section - static mut _srtc_fast_text: u32; - static mut _ertc_fast_text: u32; - static mut _irtc_fast_text: u32; - - // Boundaries of the .rtc_fast.data section - static mut _rtc_fast_data_start: u32; - static mut _rtc_fast_data_end: u32; - static mut _irtc_fast_data: u32; } #[cfg(feature = "mcu-boot")] @@ -94,21 +71,6 @@ extern "C" { // Entry point address for the MCUboot image header static ENTRY_POINT: unsafe extern "C" fn() = _start; -#[cfg(feature = "direct-boot")] -#[doc(hidden)] -#[esp_hal_common::esp_riscv_rt::pre_init] -unsafe fn init() { - r0::init_data(&mut _srwtext, &mut _erwtext, &_irwtext); - - r0::init_data( - &mut _rtc_fast_data_start, - &mut _rtc_fast_data_end, - &_irtc_fast_data, - ); - - r0::init_data(&mut _srtc_fast_text, &mut _ertc_fast_text, &_irtc_fast_text); -} - #[cfg(feature = "mcu-boot")] #[link_section = ".rwtext"] unsafe fn configure_mmu() { @@ -178,26 +140,12 @@ unsafe fn configure_mmu() { } #[allow(unreachable_code)] -#[export_name = "_mp_hook"] +#[export_name = "__post_init"] #[doc(hidden)] #[cfg_attr(feature = "mcu-boot", link_section = ".rwtext")] -pub fn mp_hook() -> bool { +pub fn post_init() { #[cfg(feature = "mcu-boot")] unsafe { configure_mmu(); } - - unsafe { - r0::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end); - } - - #[cfg(feature = "direct-boot")] - return true; - - // no init data when using normal boot - but we need to zero out BSS - unsafe { - r0::zero_bss(&mut _sbss, &mut _ebss); - } - - false } diff --git a/esp32c6-hal/Cargo.toml b/esp32c6-hal/Cargo.toml index a84719097f7..25f6e618eac 100644 --- a/esp32c6-hal/Cargo.toml +++ b/esp32c6-hal/Cargo.toml @@ -34,7 +34,6 @@ embedded-hal-async = { version = "0.2.0-alpha.0", optional = true } embedded-hal-nb = { version = "=1.0.0-alpha.1", optional = true } embedded-can = { version = "0.4.1", optional = true } esp-hal-common = { version = "0.7.0", features = ["esp32c6"], path = "../esp-hal-common" } -r0 = "1.0.0" [dev-dependencies] aes = "0.8.2" @@ -50,8 +49,8 @@ ssd1306 = "0.7.1" static_cell = "1.0.0" [features] -default = ["rt", "vectored"] -direct-boot = [] +default = ["rt", "vectored", "esp-hal-common/rv-zero-rtc-bss"] +direct-boot = ["esp-hal-common/rv-init-data", "esp-hal-common/rv-init-rtc-data"] eh1 = ["esp-hal-common/eh1", "dep:embedded-hal-1", "dep:embedded-hal-nb", "dep:embedded-can"] rt = [] ufmt = ["esp-hal-common/ufmt"] diff --git a/esp32c6-hal/ld/bl-riscv-link.x b/esp32c6-hal/ld/bl-riscv-link.x index bc8231386ea..ea8b575ca89 100644 --- a/esp32c6-hal/ld/bl-riscv-link.x +++ b/esp32c6-hal/ld/bl-riscv-link.x @@ -24,10 +24,7 @@ PROVIDE(ExceptionHandler = DefaultExceptionHandler); ID: */ PROVIDE(interrupt0 = DefaultHandler); -/* # Pre-initialization function */ -/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function, - then the function this points to will be called before the RAM is initialized. */ -PROVIDE(__pre_init = default_pre_init); +PROVIDE(__post_init = default_post_init); /* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */ PROVIDE(_setup_interrupts = default_setup_interrupts); diff --git a/esp32c6-hal/ld/db-riscv-link.x b/esp32c6-hal/ld/db-riscv-link.x index 16c844ab719..509b5efa884 100644 --- a/esp32c6-hal/ld/db-riscv-link.x +++ b/esp32c6-hal/ld/db-riscv-link.x @@ -24,10 +24,7 @@ PROVIDE(ExceptionHandler = DefaultExceptionHandler); ID: */ PROVIDE(interrupt0 = DefaultHandler); -/* # Pre-initialization function */ -/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function, - then the function this points to will be called before the RAM is initialized. */ -PROVIDE(__pre_init = default_pre_init); +PROVIDE(__post_init = default_post_init); /* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */ PROVIDE(_setup_interrupts = default_setup_interrupts); diff --git a/esp32c6-hal/src/lib.rs b/esp32c6-hal/src/lib.rs index 0fed2129f45..3efee7b55cc 100644 --- a/esp32c6-hal/src/lib.rs +++ b/esp32c6-hal/src/lib.rs @@ -11,64 +11,3 @@ pub use self::gpio::IO; pub mod analog { pub use esp_hal_common::analog::{AvailableAnalog, SarAdcExt}; } - -extern "C" { - // Boundaries of the .iram section - static mut _srwtext: u32; - static mut _erwtext: u32; - static mut _irwtext: u32; - - // Boundaries of the .bss section - static mut _ebss: u32; - static mut _sbss: u32; - - // Boundaries of the rtc .bss section - static mut _rtc_fast_bss_start: u32; - static mut _rtc_fast_bss_end: u32; - - // Boundaries of the .rtc_fast.text section - static mut _srtc_fast_text: u32; - static mut _ertc_fast_text: u32; - static mut _irtc_fast_text: u32; - - // Boundaries of the .rtc_fast.data section - static mut _rtc_fast_data_start: u32; - static mut _rtc_fast_data_end: u32; - static mut _irtc_fast_data: u32; -} - -#[cfg(feature = "direct-boot")] -#[doc(hidden)] -#[esp_hal_common::esp_riscv_rt::pre_init] -unsafe fn init() { - r0::init_data(&mut _srwtext, &mut _erwtext, &_irwtext); - - r0::init_data( - &mut _rtc_fast_data_start, - &mut _rtc_fast_data_end, - &_irtc_fast_data, - ); - - r0::init_data(&mut _srtc_fast_text, &mut _ertc_fast_text, &_irtc_fast_text); - - esp_hal_common::disable_apm_filter(); -} - -#[allow(unreachable_code)] -#[export_name = "_mp_hook"] -#[doc(hidden)] -pub fn mp_hook() -> bool { - unsafe { - r0::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end); - } - - #[cfg(feature = "direct-boot")] - return true; - - // no init data when using normal boot - but we need to zero out BSS - unsafe { - r0::zero_bss(&mut _sbss, &mut _ebss); - } - - false -}