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In order to achieve higher data rates and minimize number of dropped packets it is recommended to optimize setting of JTAG clock frequency, so it is at maximum and still provides stable operation of JTAG. To do so use the following tips.
The upper limit of JTAG clock frequency is 20 MHz if CPU runs at 80 MHz, or 26 MHz if CPU runs at 160 MHz or 240 MHz.
Depending on particular JTAG adapter and the length of connecting cables, you may need to reduce JTAG frequency below 20 / 26 MHz.
In particular reduce frequency, if you get DSR/DIR errors (and they do not relate to OpenOCD trying to read from a memory range without physical memory being present there).
ESP-WROVER-KIT operates stable at 20 / 26 MHz.
Can the discrepancy between the documentation, configuration, and any bugs/issues in this repo be re-aligned to an appropriate consensus?
The text was updated successfully, but these errors were encountered:
While documenting platformio/platform-espressif32#917 I noted a detail:
Checking out 7fbfdc8 and 0d16bff confirmed it.
As per "Optimize JTAG speed" in the API guide.
Can the discrepancy between the documentation, configuration, and any bugs/issues in this repo be re-aligned to an appropriate consensus?
The text was updated successfully, but these errors were encountered: