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fabianschuiki opened this issue
Jan 9, 2021
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A-codegenArea: Code generation.A-typeckArea: Type checking, inference, and computation.C-bugCategory: This is a bug.L-vlogLanguage: Verilog and SystemVerilog.
Wait statements with an integer argument instead of a exact duration with units generate LLHD wait instructions with an i32 duration. For example:
modulefoo;
initial#1;
endmodule
Generates the following LLHD:
proc %foo.initial.3.0 () -> () {
0:
%1 = const i321; wrong, should be a time constant
wait %2 for %12:
halt
}
entity @foo () -> () {
inst %foo.initial.3.0 () -> ()
}
This should generate a time constant, at least picking some arbitrary unit as a starting point, and later actually honoring the timescale and timeunit statements and preprocessor macros in the SV source code.
The text was updated successfully, but these errors were encountered:
A-codegenArea: Code generation.A-typeckArea: Type checking, inference, and computation.C-bugCategory: This is a bug.L-vlogLanguage: Verilog and SystemVerilog.
Wait statements with an integer argument instead of a exact duration with units generate LLHD
wait
instructions with ani32
duration. For example:Generates the following LLHD:
This should generate a
time
constant, at least picking some arbitrary unit as a starting point, and later actually honoring thetimescale
andtimeunit
statements and preprocessor macros in the SV source code.The text was updated successfully, but these errors were encountered: