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Wait with unit-less duration generates incorrect code #220

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fabianschuiki opened this issue Jan 9, 2021 · 0 comments
Open

Wait with unit-less duration generates incorrect code #220

fabianschuiki opened this issue Jan 9, 2021 · 0 comments
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A-codegen Area: Code generation. A-typeck Area: Type checking, inference, and computation. C-bug Category: This is a bug. L-vlog Language: Verilog and SystemVerilog.

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@fabianschuiki
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fabianschuiki commented Jan 9, 2021

Wait statements with an integer argument instead of a exact duration with units generate LLHD wait instructions with an i32 duration. For example:

module foo;
    initial #1;
endmodule

Generates the following LLHD:

proc %foo.initial.3.0 () -> () {
0:
    %1 = const i32 1  ; wrong, should be a time constant
    wait %2 for %1
2:
    halt
}

entity @foo () -> () {
    inst %foo.initial.3.0 () -> ()
}

This should generate a time constant, at least picking some arbitrary unit as a starting point, and later actually honoring the timescale and timeunit statements and preprocessor macros in the SV source code.

@fabianschuiki fabianschuiki added C-bug Category: This is a bug. L-vlog Language: Verilog and SystemVerilog. A-codegen Area: Code generation. A-typeck Area: Type checking, inference, and computation. labels Jan 9, 2021
@fabianschuiki fabianschuiki modified the milestone: v0.12 Jan 9, 2021
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Labels
A-codegen Area: Code generation. A-typeck Area: Type checking, inference, and computation. C-bug Category: This is a bug. L-vlog Language: Verilog and SystemVerilog.
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