From 50de8a34c19c12de5066cd7ada50ebb5f5b2ea26 Mon Sep 17 00:00:00 2001
From: Albert Chen <40366337+albertchen-sifive@users.noreply.github.com>
Date: Sat, 22 Jun 2019 02:02:06 -0700
Subject: [PATCH] add support for wake and wit (#2010)

---
 build.wake           | 138 +++++++++++++++++++++++++++++++++++++++++++
 ivydependencies.json |  23 ++++++++
 wit-manifest.json    |  22 +++++++
 3 files changed, 183 insertions(+)
 create mode 100644 build.wake
 create mode 100644 ivydependencies.json
 create mode 100644 wit-manifest.json

diff --git a/build.wake b/build.wake
new file mode 100644
index 00000000000..de02ae057a3
--- /dev/null
+++ b/build.wake
@@ -0,0 +1,138 @@
+
+global def hardfloatScalaModule =
+  makeScalaModuleFromJSON here "hardfloat"
+  | setScalaModuleRootDir "berkeley-hardfloat"
+  | setScalaModuleDeps (chisel3ScalaModule, Nil)
+  | setScalaModuleScalacOptions ("-Xsource:2.11", Nil)
+
+global def rocketchipMacros =
+  makeScalaModuleFromJSON here "rocketchipMacros"
+  | setScalaModuleRootDir "rocket-chip/macros"
+  | addMacrosParadiseCompilerPlugin
+
+global def rocketchipScalaModule =
+  makeScalaModuleFromJSON here "rocketchip"
+  | setScalaModuleRootDir "rocket-chip"
+  | setScalaModuleDeps (rocketchipMacros, hardfloatScalaModule, Nil)
+  | setScalaModuleScalacOptions ("-Xsource:2.11", Nil)
+  | addMacrosParadiseCompilerPlugin
+
+def vlsi_mem_gen = source "rocket-chip/scripts/vlsi_mem_gen"
+def vlsi_rom_gen = source "rocket-chip/scripts/vlsi_rom_gen"
+
+tuple VLSIRomGenOptions =
+  global ConfFile:   Path
+  global HexFile:    String
+  global OutputFile: String
+
+global def makeVLSIRomGenOptions confFile hexFile outputFile = VLSIRomGenOptions confFile hexFile outputFile
+
+global def rocket_vlsi_rom_gen options =
+  def cmdline =
+    def confFile = options.getVLSIRomGenOptionsConfFile.getPathName
+    def hexFile  = options.getVLSIRomGenOptionsHexFile
+    vlsi_rom_gen.getPathName, confFile, hexFile, Nil
+
+  def inputs =
+    def confFile = options.getVLSIRomGenOptionsConfFile
+    def outputFile = options.getVLSIRomGenOptionsOutputFile
+    def outputDir = simplify "{outputFile}/.." | mkdir
+    vlsi_rom_gen, confFile, outputDir, Nil
+
+  def outputFile = options.getVLSIRomGenOptionsOutputFile
+  match (job cmdline inputs | getJobStdout)
+    Pass content = write outputFile content
+    Fail error   = makeBadPath error
+
+tuple VLSIMemGenOptions =
+  global BlackBox: Boolean
+  global ConfFile: Path
+  global OutputFile: String
+
+global def makeVLSIMemGenOptions confFile outputFile = VLSIMemGenOptions False confFile outputFile
+
+global def rocket_vlsi_mem_gen options =
+  def cmdline =
+    def blackBox = if options.getVLSIMemGenOptionsBlackBox then "-b", Nil else Nil
+    def outputFile = "-o", options.getVLSIMemGenOptionsOutputFile, Nil
+    def confFile = options.getVLSIMemGenOptionsConfFile.getPathName, Nil
+    vlsi_mem_gen.getPathName, (blackBox ++ outputFile ++ confFile)
+
+  def inputs =
+    def confFile = options.getVLSIMemGenOptionsConfFile
+    def outputFile = options.getVLSIMemGenOptionsOutputFile
+    def outputDir = simplify "{outputFile}/.." | mkdir
+    vlsi_mem_gen, confFile, outputDir, Nil
+
+  job cmdline inputs | getJobOutput
+
+tuple RocketChipGeneratorOptions =
+  global Jars:          List Path
+  global TargetDir:     Path
+  global TopModuleName: String
+  global ConfigNames:   List String
+  global ExtraSources:  List Path
+
+global def makeRocketChipGeneratorOptions jars targetDir topModule configs =
+  RocketChipGeneratorOptions jars targetDir topModule configs Nil
+
+tuple RocketChipGeneratorOutputs =
+  DTS_:            Path
+  FirrtlFile_:     Path
+  FirrtlAnnoFile_: Path
+  RomConf_:        Path
+  AllOutputs_:     List Path
+  InputOptions_:   RocketChipGeneratorOptions
+  OMFile_:         Option Path
+
+global def getRocketChipGeneratorOutputsDTS             = getRocketChipGeneratorOutputsDTS_
+global def getRocketChipGeneratorOutputsFirrtlFile      = getRocketChipGeneratorOutputsFirrtlFile_
+global def getRocketChipGeneratorOutputsFirrtlAnnoFile  = getRocketChipGeneratorOutputsFirrtlAnnoFile_
+global def getRocketChipGeneratorOutputsRomConf         = getRocketChipGeneratorOutputsRomConf_
+global def getRocketChipGeneratorOutputsAllOutputs      = getRocketChipGeneratorOutputsAllOutputs_
+global def getRocketChipGeneratorOutputsInputOptions    = getRocketChipGeneratorOutputsInputOptions_
+global def getRocketChipGeneratorOutputsObjectModelFile = getRocketChipGeneratorOutputsOMFile_
+
+global def runRocketChipGenerator options =
+  def jars = options.getRocketChipGeneratorOptionsJars
+  def runDir = "rocket-chip"
+  def targetDir = options.getRocketChipGeneratorOptionsTargetDir
+
+  def cmdline =
+    def rootPackage = "_root_"
+    def main = "freechips.rocketchip.system.Generator"
+    def configs = catWith "_" options.getRocketChipGeneratorOptionsConfigNames
+    def topModule = options.getRocketChipGeneratorOptionsTopModuleName
+    def relJars = jars | map getPathName | map (relative runDir)
+    def classpath = catWith ":" relJars
+    def relTargetDir = relative runDir targetDir.getPathName
+    which "java", "-cp", classpath, main,
+    relTargetDir,
+    rootPackage, topModule,
+    rootPackage, configs,
+    Nil
+
+  def inputs =
+    def bootrom = source 'rocket-chip/bootrom/bootrom.img'
+    def extras = options.getRocketChipGeneratorOptionsExtraSources
+    (bootrom, targetDir, extras) ++ jars
+
+  def generatorJob =
+    makePlan cmdline inputs
+    | setPlanDirectory runDir
+    | runJob
+
+  def filterFiles regex = filter (matches regex _.getPathName) allOutputs
+  def getFile regex = filterFiles regex | head | getOrElse (makeBadPath (makeError "File not found"))
+  def getFileOpt regex = match (filterFiles regex)
+    Nil        = None
+    head, tail = Some head
+
+  def allOutputs = generatorJob.getJobOutputs
+  def annoFile    = getFile `.*\.anno\.json`
+  def firrtlFile  = getFile `.*\.fir`
+  def romConfFile = getFile `.*\.rom\.conf`
+  def dtsFile     = getFile `.*\.dts`
+  def omFile      = getFileOpt `.*\.objectModel\.json`
+
+  RocketChipGeneratorOutputs dtsFile firrtlFile annoFile romConfFile allOutputs options omFile
diff --git a/ivydependencies.json b/ivydependencies.json
new file mode 100644
index 00000000000..407a79efd97
--- /dev/null
+++ b/ivydependencies.json
@@ -0,0 +1,23 @@
+{
+  "hardfloat": {
+    "scalaVersion": "2.12.8"
+  },
+  "rocketchipMacros": {
+    "scalaVersion": "2.12.8",
+    "dependencies": [
+      "org.scala-lang:scala-reflect:2.12.8"
+    ]
+  },
+  "rocketchip": {
+    "scalaVersion": "2.12.8",
+    "dependencies": [
+      "org.json4s::json4s-jackson:3.5.3"
+    ]
+  },
+  "macrosParadise": {
+    "scalaVersion": "2.12.8",
+    "dependencies": [
+      "org.scalamacros:::paradise:2.1.0"
+    ]
+  }
+}
diff --git a/wit-manifest.json b/wit-manifest.json
new file mode 100644
index 00000000000..a013ca6a0a5
--- /dev/null
+++ b/wit-manifest.json
@@ -0,0 +1,22 @@
+[
+    {
+        "commit": "70c1e1dd0954bb8e9d62563b8c9730bbc39d2bf0",
+        "name": "berkeley-hardfloat",
+        "source": "git@github.com:ucb-bar/berkeley-hardfloat.git"
+    },
+    {
+        "commit": "258e0bd41ddc8811725d51192a8fffb133b6f1c8",
+        "name": "api-chisel3-sifive",
+        "source": "git@github.com:sifive/api-chisel3-sifive.git"
+    },
+    {
+        "commit": "e1aa5f3f5c0cdeb204047c3ca50801d9f7ea25f1",
+        "name": "chisel3",
+        "source": "git@github.com:freechipsproject/chisel3.git"
+    },
+    {
+        "commit": "228c9a4b7432ac52178d63b8f27fe064aec71e9c",
+        "name": "firrtl",
+        "source": "git@github.com:freechipsproject/firrtl.git"
+    }
+]