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mspm0l110x.mmap
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mspm0l110x.mmap
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0x40004000 A PERIPHERAL ADC0
0x40004400 B REGISTER FSUB_0 (rw): Subscriber Configuration Register.
0x40004400 C FIELD 00w02 FSUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40004444 B REGISTER FPUB_1 (rw): Publisher Configuration Register.
0x40004444 C FIELD 00w02 FPUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40004800 B REGISTER PWREN (rw): Power enable
0x40004800 C FIELD 00w01 PWREN_ENABLE (rw): Enable the power
0x40004800 C FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40004804 B REGISTER RSTCTL (wo): Reset Control
0x40004804 C FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x40004804 C FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x40004804 C FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40004808 B REGISTER CLKCFG (rw): ADC clock configuration Register
0x40004808 C FIELD 00w02 CLKCFG_SAMPCLK: ADC sample clock source selection.
0x40004808 C FIELD 04w01 CLKCFG_CCONRUN: CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source.
0x40004808 C FIELD 05w01 CLKCFG_CCONSTOP: CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source.
0x40004808 C FIELD 24w08 CLKCFG_KEY (wo): Unlock key
0x40004814 B REGISTER STAT (ro): Status Register
0x40004814 C FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40005020 B REGISTER INT_EVENT0_IIDX (ro): Interrupt index
0x40005020 C FIELD 00w10 INT_EVENT0_IIDX_STAT (ro): Interrupt index status
0x40005028 B REGISTER INT_EVENT0_IMASK (rw): Interrupt mask
0x40005028 C FIELD 00w01 INT_EVENT0_IMASK_OVIFG: Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005028 C FIELD 01w01 INT_EVENT0_IMASK_TOVIFG: Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005028 C FIELD 02w01 INT_EVENT0_IMASK_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005028 C FIELD 03w01 INT_EVENT0_IMASK_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005028 C FIELD 04w01 INT_EVENT0_IMASK_INIFG: Mask INIFG in MIS_EX register.
0x40005028 C FIELD 05w01 INT_EVENT0_IMASK_DMADONE: Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005028 C FIELD 06w01 INT_EVENT0_IMASK_UVIFG: Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1.
0x40005028 C FIELD 08w01 INT_EVENT0_IMASK_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005028 C FIELD 09w01 INT_EVENT0_IMASK_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005028 C FIELD 10w01 INT_EVENT0_IMASK_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005028 C FIELD 11w01 INT_EVENT0_IMASK_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005030 B REGISTER INT_EVENT0_RIS (ro): Raw interrupt status
0x40005030 C FIELD 00w01 INT_EVENT0_RIS_OVIFG: Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005030 C FIELD 01w01 INT_EVENT0_RIS_TOVIFG: Raw interrupt flag for sequence conversion trigger overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005030 C FIELD 02w01 INT_EVENT0_RIS_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005030 C FIELD 03w01 INT_EVENT0_RIS_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005030 C FIELD 04w01 INT_EVENT0_RIS_INIFG: Mask INIFG in MIS_EX register.
0x40005030 C FIELD 05w01 INT_EVENT0_RIS_DMADONE: Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005030 C FIELD 06w01 INT_EVENT0_RIS_UVIFG: Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1.
0x40005030 C FIELD 08w01 INT_EVENT0_RIS_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005030 C FIELD 09w01 INT_EVENT0_RIS_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005030 C FIELD 10w01 INT_EVENT0_RIS_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005030 C FIELD 11w01 INT_EVENT0_RIS_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005038 B REGISTER INT_EVENT0_MIS (ro): Masked interrupt status
0x40005038 C FIELD 00w01 INT_EVENT0_MIS_OVIFG: Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005038 C FIELD 01w01 INT_EVENT0_MIS_TOVIFG: Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005038 C FIELD 02w01 INT_EVENT0_MIS_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005038 C FIELD 03w01 INT_EVENT0_MIS_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005038 C FIELD 04w01 INT_EVENT0_MIS_INIFG: Mask INIFG in MIS_EX register.
0x40005038 C FIELD 05w01 INT_EVENT0_MIS_DMADONE: Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005038 C FIELD 06w01 INT_EVENT0_MIS_UVIFG: Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1.
0x40005038 C FIELD 08w01 INT_EVENT0_MIS_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005038 C FIELD 09w01 INT_EVENT0_MIS_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005038 C FIELD 10w01 INT_EVENT0_MIS_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005038 C FIELD 11w01 INT_EVENT0_MIS_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005040 B REGISTER INT_EVENT0_ISET (wo): Interrupt set
0x40005040 C FIELD 00w01 INT_EVENT0_ISET_OVIFG: Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005040 C FIELD 01w01 INT_EVENT0_ISET_TOVIFG: Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005040 C FIELD 02w01 INT_EVENT0_ISET_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005040 C FIELD 03w01 INT_EVENT0_ISET_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005040 C FIELD 04w01 INT_EVENT0_ISET_INIFG: Mask INIFG in MIS_EX register.
0x40005040 C FIELD 05w01 INT_EVENT0_ISET_DMADONE: Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005040 C FIELD 06w01 INT_EVENT0_ISET_UVIFG: Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005040 C FIELD 08w01 INT_EVENT0_ISET_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005040 C FIELD 09w01 INT_EVENT0_ISET_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005040 C FIELD 10w01 INT_EVENT0_ISET_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005040 C FIELD 11w01 INT_EVENT0_ISET_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005048 B REGISTER INT_EVENT0_ICLR (wo): Interrupt clear
0x40005048 C FIELD 00w01 INT_EVENT0_ICLR_OVIFG: Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005048 C FIELD 01w01 INT_EVENT0_ICLR_TOVIFG: Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005048 C FIELD 02w01 INT_EVENT0_ICLR_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005048 C FIELD 03w01 INT_EVENT0_ICLR_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005048 C FIELD 04w01 INT_EVENT0_ICLR_INIFG: Mask INIFG in MIS_EX register.
0x40005048 C FIELD 05w01 INT_EVENT0_ICLR_DMADONE: Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005048 C FIELD 06w01 INT_EVENT0_ICLR_UVIFG: Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005048 C FIELD 08w01 INT_EVENT0_ICLR_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005048 C FIELD 09w01 INT_EVENT0_ICLR_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005048 C FIELD 10w01 INT_EVENT0_ICLR_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005048 C FIELD 11w01 INT_EVENT0_ICLR_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005050 B REGISTER INT_EVENT1_IIDX (ro): Interrupt index
0x40005050 C FIELD 00w10 INT_EVENT1_IIDX_STAT (ro): Interrupt index status
0x40005058 B REGISTER INT_EVENT1_IMASK (rw): Interrupt mask
0x40005058 C FIELD 02w01 INT_EVENT1_IMASK_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005058 C FIELD 03w01 INT_EVENT1_IMASK_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005058 C FIELD 04w01 INT_EVENT1_IMASK_INIFG: Mask INIFG in MIS_EX register.
0x40005058 C FIELD 08w01 INT_EVENT1_IMASK_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005060 B REGISTER INT_EVENT1_RIS (ro): Raw interrupt status
0x40005060 C FIELD 02w01 INT_EVENT1_RIS_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005060 C FIELD 03w01 INT_EVENT1_RIS_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005060 C FIELD 04w01 INT_EVENT1_RIS_INIFG: Mask INIFG in MIS_EX register.
0x40005060 C FIELD 08w01 INT_EVENT1_RIS_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005068 B REGISTER INT_EVENT1_MIS (ro): Masked interrupt status
0x40005068 C FIELD 02w01 INT_EVENT1_MIS_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005068 C FIELD 03w01 INT_EVENT1_MIS_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005068 C FIELD 04w01 INT_EVENT1_MIS_INIFG: Mask INIFG in MIS_EX register.
0x40005068 C FIELD 08w01 INT_EVENT1_MIS_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005070 B REGISTER INT_EVENT1_ISET (wo): Interrupt set
0x40005070 C FIELD 02w01 INT_EVENT1_ISET_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005070 C FIELD 03w01 INT_EVENT1_ISET_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005070 C FIELD 04w01 INT_EVENT1_ISET_INIFG: Mask INIFG in MIS_EX register.
0x40005070 C FIELD 08w01 INT_EVENT1_ISET_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005078 B REGISTER INT_EVENT1_ICLR (wo): Interrupt clear
0x40005078 C FIELD 02w01 INT_EVENT1_ICLR_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005078 C FIELD 03w01 INT_EVENT1_ICLR_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005078 C FIELD 04w01 INT_EVENT1_ICLR_INIFG: Mask INIFG in MIS_EX register.
0x40005078 C FIELD 08w01 INT_EVENT1_ICLR_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005080 B REGISTER INT_EVENT2_IIDX (ro): Interrupt index
0x40005080 C FIELD 00w10 INT_EVENT2_IIDX_STAT (ro): Interrupt index status
0x40005088 B REGISTER INT_EVENT2_IMASK (rw): Interrupt mask extension
0x40005088 C FIELD 08w01 INT_EVENT2_IMASK_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005088 C FIELD 09w01 INT_EVENT2_IMASK_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005088 C FIELD 10w01 INT_EVENT2_IMASK_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005088 C FIELD 11w01 INT_EVENT2_IMASK_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005090 B REGISTER INT_EVENT2_RIS (ro): Raw interrupt status extension
0x40005090 C FIELD 08w01 INT_EVENT2_RIS_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005090 C FIELD 09w01 INT_EVENT2_RIS_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005090 C FIELD 10w01 INT_EVENT2_RIS_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005090 C FIELD 11w01 INT_EVENT2_RIS_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005098 B REGISTER INT_EVENT2_MIS (ro): Masked interrupt status extension
0x40005098 C FIELD 08w01 INT_EVENT2_MIS_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005098 C FIELD 09w01 INT_EVENT2_MIS_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005098 C FIELD 10w01 INT_EVENT2_MIS_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005098 C FIELD 11w01 INT_EVENT2_MIS_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050A0 B REGISTER INT_EVENT2_ISET (wo): Interrupt set extension
0x400050A0 C FIELD 08w01 INT_EVENT2_ISET_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050A0 C FIELD 09w01 INT_EVENT2_ISET_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050A0 C FIELD 10w01 INT_EVENT2_ISET_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050A0 C FIELD 11w01 INT_EVENT2_ISET_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050A8 B REGISTER INT_EVENT2_ICLR (wo): Interrupt clear extension
0x400050A8 C FIELD 08w01 INT_EVENT2_ICLR_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050A8 C FIELD 09w01 INT_EVENT2_ICLR_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050A8 C FIELD 10w01 INT_EVENT2_ICLR_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050A8 C FIELD 11w01 INT_EVENT2_ICLR_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050E0 B REGISTER EVT_MODE (ro): Event Mode
0x400050E0 C FIELD 00w02 EVT_MODE_INT0_CFG (ro): Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0
0x400050E0 C FIELD 02w02 EVT_MODE_EVT1_CFG (ro): Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1
0x400050FC B REGISTER DESC (ro): Module Description
0x400050FC C FIELD 00w04 DESC_MINREV (ro): Minor rev of the IP
0x400050FC C FIELD 04w04 DESC_MAJREV (ro): Major rev of the IP
0x400050FC C FIELD 08w04 DESC_INSTNUM (ro): Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x400050FC C FIELD 12w04 DESC_FEATUREVER (ro): Feature Set for the module *instance*
0x400050FC C FIELD 16w16 DESC_MODULEID (ro): Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x40005100 B REGISTER CTL0 (rw): Control Register 0
0x40005100 C FIELD 00w01 CTL0_ENC (rw): Enable conversion
0x40005100 C FIELD 16w01 CTL0_PWRDN (rw): Power down policy
0x40005100 C FIELD 24w03 CTL0_SCLKDIV: Sample clock divider
0x40005104 B REGISTER CTL1 (rw): Control Register 1
0x40005104 C FIELD 00w01 CTL1_TRIGSRC (rw): Sample trigger source
0x40005104 C FIELD 08w01 CTL1_SC (rw): Start of conversion
0x40005104 C FIELD 16w02 CTL1_CONSEQ (rw): Conversion sequence mode
0x40005104 C FIELD 20w01 CTL1_SAMPMODE (rw): Sample mode. This bit selects the source of the sampling signal. MANUAL option is not valid when TRIGSRC is selected as hardware event trigger.
0x40005104 C FIELD 24w03 CTL1_AVGN (rw): Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx.
0x40005104 C FIELD 28w03 CTL1_AVGD (rw): Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated.
0x40005108 B REGISTER CTL2 (rw): Control Register 2
0x40005108 C FIELD 00w01 CTL2_DF (rw): Data read-back format. Data is always stored in binary unsigned format.
0x40005108 C FIELD 01w02 CTL2_RES (rw): Resolution. These bits define the resolutoin of ADC conversion result. Note : A value of 3 defaults to 12-bits resolution.
0x40005108 C FIELD 08w01 CTL2_DMAEN (rw): Enable DMA trigger for data transfer. Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers.
0x40005108 C FIELD 10w01 CTL2_FIFOEN: Enable FIFO based operation
0x40005108 C FIELD 11w05 CTL2_SAMPCNT (rw): Number of ADC converted samples to be transferred on a DMA trigger
0x40005108 C FIELD 16w05 CTL2_STARTADD (rw): Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode. The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23.
0x40005108 C FIELD 24w05 CTL2_ENDADD (rw): Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode. The value of ENDADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23.
0x40005110 B REGISTER CLKFREQ (rw): Sample Clock Frequency Range Register
0x40005110 C FIELD 00w03 CLKFREQ_FRANGE: Frequency Range.
0x40005114 B REGISTER SCOMP0 (rw): Sample Time Compare 0 Register
0x40005114 C FIELD 00w10 SCOMP0_VAL (rw): Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL > 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.
0x40005118 B REGISTER SCOMP1 (rw): Sample Time Compare 1 Register
0x40005118 C FIELD 00w10 SCOMP1_VAL (rw): Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL > 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.
0x40005148 B REGISTER WCLOW (rw): Window Comparator Low Threshold Register
0x40005148 C FIELD 00w16 WCLOW_DATA (rw): If DF = 0, unsigned binary format has to be used. The value based on the resolution has to be right aligned with the MSB on the left. For 10-bits and 8-bits resolution, unused bits have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bits have to be 0s.
0x40005150 B REGISTER WCHIGH (rw): Window Comparator High Threshold Register
0x40005150 C FIELD 00w16 WCHIGH_DATA (rw): If DF = 0, unsigned binary format has to be used. The threshold value has to be right aligned, with the MSB on the left. For 10-bits and 8-bits resolution, unused bit have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bit have to be 0s.
0x40005180 B REGISTER MEMCTL[0] (rw): Conversion Memory Control Register
0x40005180 C FIELD 00w05 MEMCTL_CHANSEL (rw): Input channel select.
0x40005180 C FIELD 08w02 MEMCTL_VRSEL (rw): Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.
0x40005180 C FIELD 12w01 MEMCTL_STIME: Selects the source of sample timer period between SCOMP0 and SCOMP1.
0x40005180 C FIELD 16w01 MEMCTL_AVGEN (rw): Enable hardware averaging.
0x40005180 C FIELD 20w01 MEMCTL_BCSEN (rw): Enable burn out current source.
0x40005180 C FIELD 24w01 MEMCTL_TRIG (rw): Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
0x40005180 C FIELD 28w01 MEMCTL_WINCOMP (rw): Enable window comparator.
0x40005184 B REGISTER MEMCTL[1] (rw): Conversion Memory Control Register
0x40005184 C FIELD 00w05 MEMCTL_CHANSEL (rw): Input channel select.
0x40005184 C FIELD 08w02 MEMCTL_VRSEL (rw): Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.
0x40005184 C FIELD 12w01 MEMCTL_STIME: Selects the source of sample timer period between SCOMP0 and SCOMP1.
0x40005184 C FIELD 16w01 MEMCTL_AVGEN (rw): Enable hardware averaging.
0x40005184 C FIELD 20w01 MEMCTL_BCSEN (rw): Enable burn out current source.
0x40005184 C FIELD 24w01 MEMCTL_TRIG (rw): Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
0x40005184 C FIELD 28w01 MEMCTL_WINCOMP (rw): Enable window comparator.
0x40005188 B REGISTER MEMCTL[2] (rw): Conversion Memory Control Register
0x40005188 C FIELD 00w05 MEMCTL_CHANSEL (rw): Input channel select.
0x40005188 C FIELD 08w02 MEMCTL_VRSEL (rw): Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.
0x40005188 C FIELD 12w01 MEMCTL_STIME: Selects the source of sample timer period between SCOMP0 and SCOMP1.
0x40005188 C FIELD 16w01 MEMCTL_AVGEN (rw): Enable hardware averaging.
0x40005188 C FIELD 20w01 MEMCTL_BCSEN (rw): Enable burn out current source.
0x40005188 C FIELD 24w01 MEMCTL_TRIG (rw): Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
0x40005188 C FIELD 28w01 MEMCTL_WINCOMP (rw): Enable window comparator.
0x4000518C B REGISTER MEMCTL[3] (rw): Conversion Memory Control Register
0x4000518C C FIELD 00w05 MEMCTL_CHANSEL (rw): Input channel select.
0x4000518C C FIELD 08w02 MEMCTL_VRSEL (rw): Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.
0x4000518C C FIELD 12w01 MEMCTL_STIME: Selects the source of sample timer period between SCOMP0 and SCOMP1.
0x4000518C C FIELD 16w01 MEMCTL_AVGEN (rw): Enable hardware averaging.
0x4000518C C FIELD 20w01 MEMCTL_BCSEN (rw): Enable burn out current source.
0x4000518C C FIELD 24w01 MEMCTL_TRIG (rw): Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
0x4000518C C FIELD 28w01 MEMCTL_WINCOMP (rw): Enable window comparator.
0x40005340 B REGISTER STATUS (ro): Status Register
0x40005340 C FIELD 00w01 STATUS_BUSY (ro): Busy. This bit indicates that an active ADC sample or conversion operation is in progress.
0x40005340 C FIELD 01w01 STATUS_REFBUFRDY: Indicates reference buffer is powered up and ready.
0x40030000 A PERIPHERAL VREF
0x40030800 B REGISTER PWREN (rw): Power enable
0x40030800 C FIELD 00w01 PWREN_ENABLE: Enable the power
0x40030800 C FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40030804 B REGISTER RSTCTL (wo): Reset Control
0x40030804 C FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x40030804 C FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x40030804 C FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40030814 B REGISTER STAT (ro): Status Register
0x40030814 C FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40031000 B REGISTER CLKDIV (rw): Clock Divider
0x40031000 C FIELD 00w03 CLKDIV_RATIO (rw): Selects divide ratio of module clock
0x40031008 B REGISTER CLKSEL (rw): Clock Selection
0x40031008 C FIELD 01w01 CLKSEL_LFCLK_SEL (rw): Selects LFCLK as clock source if enabled
0x40031008 C FIELD 02w01 CLKSEL_MFCLK_SEL (rw): Selects MFCLK as clock source if enabled
0x40031008 C FIELD 03w01 CLKSEL_BUSCLK_SEL (rw): Selects BUSCLK as clock source if enabled
0x400310FC B REGISTER DESC (ro): Module Description
0x400310FC C FIELD 00w04 DESC_MINREV (ro): Minor rev of the IP
0x400310FC C FIELD 04w04 DESC_MAJREV (ro): Major rev of the IP
0x400310FC C FIELD 12w04 DESC_FEATUREVER (ro): Feature Set for the module *instance*
0x400310FC C FIELD 16w16 DESC_MODULEID (ro): Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x40031100 B REGISTER CTL0 (rw): Control 0
0x40031100 C FIELD 00w01 CTL0_ENABLE (rw): This bit enables the VREF module.
0x40031100 C FIELD 01w01 CTL0_ENABLEBIAS (rw): This bit enables the VREF Bias.
0x40031100 C FIELD 02w02 CTL0_IBPROG (rw): There bits configure current bias.
0x40031100 C FIELD 07w01 CTL0_BUFCONFIG (rw): These bits configure output buffer.
0x40031100 C FIELD 08w01 CTL0_SHMODE (rw): This bit enable sample and hold mode
0x40031100 C FIELD 09w04 CTL0_SPARE (rw): These bits are reserved
0x40031104 B REGISTER CTL1 (rw): Control 1
0x40031104 C FIELD 00w01 CTL1_READY (ro): These bits defines status of VREF
0x40031104 C FIELD 01w01 CTL1_VREFLOSEL (rw): This bit select VREFLO pin
0x40031108 B REGISTER CTL2 (rw): Control 2
0x40031108 C FIELD 00w16 CTL2_SHCYCLE (rw): Sample and hold cycle count
0x40031108 C FIELD 16w16 CTL2_HCYCLE (rw): Hold cycle count
0x40080000 A PERIPHERAL WWDT0
0x40080800 B REGISTER PWREN (rw): Power enable
0x40080800 C FIELD 00w01 PWREN_ENABLE: Enable the power Note: For safety devices the power cannot be disabled once enabled.
0x40080800 C FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40080804 B REGISTER RSTCTL (wo): Reset Control
0x40080804 C FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral Note: For safety devices a watchdog reset by software is not possible.
0x40080804 C FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear [GPRCM.STAT.RESETSTKY]
0x40080804 C FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40080814 B REGISTER STAT (ro): Status Register
0x40080814 C FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40081018 B REGISTER PDBGCTL (rw): Peripheral Debug Control
0x40081018 C FIELD 00w01 PDBGCTL_FREE (rw): Free run control
0x40081020 B REGISTER IIDX (ro): Interrupt index
0x40081020 C FIELD 00w05 IIDX_STAT (ro): Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC.
0x40081028 B REGISTER IMASK (rw): Interrupt mask
0x40081028 C FIELD 00w01 IMASK_INTTIM: Interval Timer Interrupt.
0x40081030 B REGISTER RIS (ro): Raw interrupt status
0x40081030 C FIELD 00w01 RIS_INTTIM: Interval Timer Interrupt.
0x40081038 B REGISTER MIS (ro): Masked interrupt status
0x40081038 C FIELD 00w01 MIS_INTTIM: Interval Timer Interrupt.
0x40081040 B REGISTER ISET (wo): Interrupt set
0x40081040 C FIELD 00w01 ISET_INTTIM: Interval Timer Interrupt.
0x40081048 B REGISTER ICLR (wo): Interrupt clear
0x40081048 C FIELD 00w01 ICLR_INTTIM: Interval Timer Interrupt.
0x400810E0 B REGISTER EVT_MODE (rw): Event Mode
0x400810E0 C FIELD 00w02 EVT_MODE_INT0_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]
0x400810FC B REGISTER DESC (ro): Module Description
0x400810FC C FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x400810FC C FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x400810FC C FIELD 08w04 DESC_INSTNUM: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x400810FC C FIELD 12w04 DESC_FEATUREVER: Feature Set for the module *instance*
0x400810FC C FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x40081100 B REGISTER WWDTCTL0 (read-writeOnce): Window Watchdog Timer Control Register 0
0x40081100 C FIELD 00w03 WWDTCTL0_CLKDIV (read-writeOnce): Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0.
0x40081100 C FIELD 04w03 WWDTCTL0_PER (read-writeOnce): Timer Period of the WWDT. These bits select the total watchdog timer count.
0x40081100 C FIELD 08w03 WWDTCTL0_WINDOW0 (read-writeOnce): Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).
0x40081100 C FIELD 12w03 WWDTCTL0_WINDOW1 (read-writeOnce): Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).
0x40081100 C FIELD 16w01 WWDTCTL0_MODE (read-writeOnce): Window Watchdog Timer Mode
0x40081100 C FIELD 17w01 WWDTCTL0_STISM (read-writeOnce): Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported.
0x40081100 C FIELD 24w08 WWDTCTL0_KEY (read-writeOnce): KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0.
0x40081104 B REGISTER WWDTCTL1 (rw): Window Watchdog Timer Control Register 0
0x40081104 C FIELD 00w01 WWDTCTL1_WINSEL (rw): Close Window Select
0x40081104 C FIELD 24w08 WWDTCTL1_KEY (wo): KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0.
0x40081108 B REGISTER WWDTCNTRST (rw): Window Watchdog Timer Counter Reset Register
0x40081108 C FIELD 00w32 WWDTCNTRST_RESTART (rw): Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter. Writing any other value causes an error generation to the ESM. Read as 0.
0x4008110C B REGISTER WWDTSTAT (ro): Window Watchdog Timer Status Register
0x4008110C C FIELD 00w01 WWDTSTAT_RUN (ro): Watchdog running status flag.
0x40084000 A PERIPHERAL TIMG0
0x40084400 B REGISTER FSUB_0 (rw): Subsciber Port 0
0x40084400 C FIELD 00w02 FSUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40084404 B REGISTER FSUB_1 (rw): Subscriber Port 1
0x40084404 C FIELD 00w02 FSUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40084444 B REGISTER FPUB_0 (rw): Publisher Port 0
0x40084444 C FIELD 00w02 FPUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40084448 B REGISTER FPUB_1 (rw): Publisher Port 1
0x40084448 C FIELD 00w02 FPUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40084800 B REGISTER PWREN (rw): Power enable
0x40084800 C FIELD 00w01 PWREN_ENABLE: Enable the power
0x40084800 C FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40084804 B REGISTER RSTCTL (wo): Reset Control
0x40084804 C FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x40084804 C FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x40084804 C FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40084814 B REGISTER STAT (ro): Status Register
0x40084814 C FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40085000 B REGISTER CLKDIV (rw): Clock Divider
0x40085000 C FIELD 00w03 CLKDIV_RATIO: Selects divide ratio of module clock
0x40085008 B REGISTER CLKSEL (rw): Clock Select for Ultra Low Power peripherals
0x40085008 C FIELD 01w01 CLKSEL_LFCLK_SEL (rw): Selects LFCLK as clock source if enabled
0x40085008 C FIELD 02w01 CLKSEL_MFCLK_SEL (rw): Selects MFCLK as clock source if enabled
0x40085008 C FIELD 03w01 CLKSEL_BUSCLK_SEL (rw): Selects BUSCLK as clock source if enabled
0x40085018 B REGISTER PDBGCTL (rw): Peripheral Debug Control
0x40085018 C FIELD 00w01 PDBGCTL_FREE (rw): Free run control
0x40085018 C FIELD 01w01 PDBGCTL_SOFT (rw): Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP'
0x40085020 B REGISTER IIDX (ro): Interrupt index
0x40085020 C FIELD 00w08 IIDX_STAT (ro): Interrupt index status
0x40085028 B REGISTER IMASK (rw): Interrupt mask
0x40085028 C FIELD 00w01 IMASK_Z: Zero Event mask
0x40085028 C FIELD 01w01 IMASK_L: Load Event mask
0x40085028 C FIELD 04w01 IMASK_CCD0: Capture or Compare DN event mask CCP0
0x40085028 C FIELD 05w01 IMASK_CCD1: Capture or Compare DN event mask CCP1
0x40085028 C FIELD 08w01 IMASK_CCU0: Capture or Compare UP event mask CCP0
0x40085028 C FIELD 09w01 IMASK_CCU1: Capture or Compare UP event mask CCP1
0x40085028 C FIELD 25w01 IMASK_TOV: Trigger Overflow Event mask
0x40085030 B REGISTER RIS (ro): Raw interrupt status
0x40085030 C FIELD 00w01 RIS_Z: Zero event generated an interrupt.
0x40085030 C FIELD 01w01 RIS_L: Load event generated an interrupt.
0x40085030 C FIELD 04w01 RIS_CCD0: Capture or compare down event generated an interrupt CCP0
0x40085030 C FIELD 05w01 RIS_CCD1: Capture or compare down event generated an interrupt CCP1
0x40085030 C FIELD 08w01 RIS_CCU0: Capture or compare up event generated an interrupt CCP0
0x40085030 C FIELD 09w01 RIS_CCU1: Capture or compare up event generated an interrupt CCP1
0x40085030 C FIELD 25w01 RIS_TOV: Trigger overflow
0x40085038 B REGISTER MIS (ro): Masked interrupt status
0x40085038 C FIELD 00w01 MIS_Z: Zero event generated an interrupt.
0x40085038 C FIELD 01w01 MIS_L: Load event generated an interrupt.
0x40085038 C FIELD 04w01 MIS_CCD0: Capture or compare down event generated an interrupt CCP0
0x40085038 C FIELD 05w01 MIS_CCD1: Capture or compare down event generated an interrupt CCP1
0x40085038 C FIELD 08w01 MIS_CCU0: Capture or compare up event generated an interrupt CCP0
0x40085038 C FIELD 09w01 MIS_CCU1: Capture or compare up event generated an interrupt CCP1
0x40085038 C FIELD 25w01 MIS_TOV: Trigger overflow
0x40085040 B REGISTER ISET (wo): Interrupt set
0x40085040 C FIELD 00w01 ISET_Z: Zero event SET
0x40085040 C FIELD 01w01 ISET_L: Load event SET
0x40085040 C FIELD 04w01 ISET_CCD0: Capture or compare down event SET
0x40085040 C FIELD 05w01 ISET_CCD1: Capture or compare down event SET
0x40085040 C FIELD 08w01 ISET_CCU0: Capture or compare up event SET
0x40085040 C FIELD 09w01 ISET_CCU1: Capture or compare up event SET
0x40085040 C FIELD 25w01 ISET_TOV: Trigger Overflow event SET
0x40085048 B REGISTER ICLR (wo): Interrupt clear
0x40085048 C FIELD 00w01 ICLR_Z: Zero event CLEAR
0x40085048 C FIELD 01w01 ICLR_L: Load event CLEAR
0x40085048 C FIELD 04w01 ICLR_CCD0: Capture or compare down event CLEAR
0x40085048 C FIELD 05w01 ICLR_CCD1: Capture or compare down event CLEAR
0x40085048 C FIELD 08w01 ICLR_CCU0: Capture or compare up event CLEAR
0x40085048 C FIELD 09w01 ICLR_CCU1: Capture or compare up event CLEAR
0x40085048 C FIELD 25w01 ICLR_TOV: Trigger Overflow event CLEAR
0x400850E0 B REGISTER EVT_MODE (rw): Event Mode
0x400850E0 C FIELD 00w02 EVT_MODE_EVT0_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]
0x400850E0 C FIELD 02w02 EVT_MODE_EVT1_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]
0x400850E0 C FIELD 04w02 EVT_MODE_EVT2_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]
0x400850FC B REGISTER DESC (ro): Module Description
0x400850FC C FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x400850FC C FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x400850FC C FIELD 08w04 DESC_INSTNUM: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x400850FC C FIELD 12w04 DESC_FEATUREVER: Feature Set for the module *instance*
0x400850FC C FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x40085100 B REGISTER CCPD (rw): CCP Direction
0x40085100 C FIELD 00w01 CCPD_C0CCP0: Counter CCP0
0x40085100 C FIELD 01w01 CCPD_C0CCP1: Counter CCP1
0x40085104 B REGISTER ODIS (rw): Output Disable
0x40085104 C FIELD 00w01 ODIS_C0CCP0 (rw): Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not
0x40085104 C FIELD 01w01 ODIS_C0CCP1 (rw): Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not
0x40085108 B REGISTER CCLKCTL (rw): Counter Clock Control Register
0x40085108 C FIELD 00w01 CCLKCTL_CLKEN (rw): Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock.
0x4008510C B REGISTER CPS (rw): Clock Prescale Register
0x4008510C C FIELD 00w08 CPS_PCNT (rw): Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock
0x40085110 B REGISTER CPSV (ro): Clock prescale count status register
0x40085110 C FIELD 00w08 CPSV_CPSVAL (ro): Current Prescale Count Value
0x40085114 B REGISTER CTTRIGCTL (rw): Timer Cross Trigger Control Register
0x40085114 C FIELD 00w01 CTTRIGCTL_CTEN (rw): Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register.
0x40085114 C FIELD 01w01 CTTRIGCTL_EVTCTEN (rw): Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path
0x40085114 C FIELD 16w04 CTTRIGCTL_EVTCTTRIGSEL (rw): Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path
0x4008511C B REGISTER CTTRIG (wo): Timer Cross Trigger Register
0x4008511C C FIELD 00w01 CTTRIG_TRIG (wo): Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance.
0x40085800 B REGISTER CTR (rw): Counter Register
0x40085800 C FIELD 00w16 CTR_CCTR (rw): Current Counter value
0x40085804 B REGISTER CTRCTL (rw): Counter Control Register
0x40085804 C FIELD 00w01 CTRCTL_EN (rw): Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively.
0x40085804 C FIELD 01w03 CTRCTL_REPEAT (rw): Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended.
0x40085804 C FIELD 04w02 CTRCTL_CM (rw): Count Mode
0x40085804 C FIELD 07w03 CTRCTL_CLC (rw): Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40085804 C FIELD 10w03 CTRCTL_CAC (rw): Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40085804 C FIELD 13w03 CTRCTL_CZC (rw): Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40085804 C FIELD 17w01 CTRCTL_DRB (rw): Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode.
0x40085804 C FIELD 28w02 CTRCTL_CVAE (rw): Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active.
0x40085808 B REGISTER LOAD (rw): Load Register
0x40085808 C FIELD 00w16 LOAD_LD (rw): Load Value
0x40085810 B REGISTER CC_01[0] (rw): Capture or Compare Register 0 to Capture or Compare Register 1
0x40085810 C FIELD 00w16 CC_01_CCVAL (rw): Capture or compare value
0x40085814 B REGISTER CC_01[1] (rw): Capture or Compare Register 0 to Capture or Compare Register 1
0x40085814 C FIELD 00w16 CC_01_CCVAL (rw): Capture or compare value
0x40085830 B REGISTER CCCTL_01[0] (rw): Capture or Compare Control Registers
0x40085830 C FIELD 00w03 CCCTL_01_CCOND (rw): Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved
0x40085830 C FIELD 04w03 CCCTL_01_ACOND (rw): Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved
0x40085830 C FIELD 08w03 CCCTL_01_LCOND (rw): Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved
0x40085830 C FIELD 12w03 CCCTL_01_ZCOND (rw): Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved
0x40085830 C FIELD 17w01 CCCTL_01_COC (rw): Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0x40085830 C FIELD 22w03 CCCTL_01_CC2SELU: Selects the source second CCU event.
0x40085830 C FIELD 26w03 CCCTL_01_CCACTUPD (rw): CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed
0x40085830 C FIELD 29w03 CCCTL_01_CC2SELD: Selects the source second CCD event.
0x40085834 B REGISTER CCCTL_01[1] (rw): Capture or Compare Control Registers
0x40085834 C FIELD 00w03 CCCTL_01_CCOND (rw): Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved
0x40085834 C FIELD 04w03 CCCTL_01_ACOND (rw): Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved
0x40085834 C FIELD 08w03 CCCTL_01_LCOND (rw): Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved
0x40085834 C FIELD 12w03 CCCTL_01_ZCOND (rw): Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved
0x40085834 C FIELD 17w01 CCCTL_01_COC (rw): Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0x40085834 C FIELD 22w03 CCCTL_01_CC2SELU: Selects the source second CCU event.
0x40085834 C FIELD 26w03 CCCTL_01_CCACTUPD (rw): CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed
0x40085834 C FIELD 29w03 CCCTL_01_CC2SELD: Selects the source second CCD event.
0x40085850 B REGISTER OCTL_01[0] (rw): CCP Output Control Registers
0x40085850 C FIELD 00w04 OCTL_01_CCPO (rw): CCP Output Source
0x40085850 C FIELD 04w01 OCTL_01_CCPOINV (rw): CCP Output Invert The output as selected by CCPO is conditionally inverted.
0x40085850 C FIELD 05w01 OCTL_01_CCPIV (rw): CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0x40085854 B REGISTER OCTL_01[1] (rw): CCP Output Control Registers
0x40085854 C FIELD 00w04 OCTL_01_CCPO (rw): CCP Output Source
0x40085854 C FIELD 04w01 OCTL_01_CCPOINV (rw): CCP Output Invert The output as selected by CCPO is conditionally inverted.
0x40085854 C FIELD 05w01 OCTL_01_CCPIV (rw): CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0x40085870 B REGISTER CCACT_01[0] (rw): Capture or Compare Action Registers
0x40085870 C FIELD 00w02 CCACT_01_ZACT (rw): CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0x40085870 C FIELD 03w02 CCACT_01_LACT (rw): CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0x40085870 C FIELD 06w02 CCACT_01_CDACT (rw): CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0x40085870 C FIELD 09w02 CCACT_01_CUACT (rw): CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0x40085870 C FIELD 12w02 CCACT_01_CC2DACT (rw): CCP Output Action on CC2D event.
0x40085870 C FIELD 15w02 CCACT_01_CC2UACT (rw): CCP Output Action on CC2U event.
0x40085870 C FIELD 28w02 CCACT_01_SWFRCACT (rw): CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.
0x40085874 B REGISTER CCACT_01[1] (rw): Capture or Compare Action Registers
0x40085874 C FIELD 00w02 CCACT_01_ZACT (rw): CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0x40085874 C FIELD 03w02 CCACT_01_LACT (rw): CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0x40085874 C FIELD 06w02 CCACT_01_CDACT (rw): CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0x40085874 C FIELD 09w02 CCACT_01_CUACT (rw): CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0x40085874 C FIELD 12w02 CCACT_01_CC2DACT (rw): CCP Output Action on CC2D event.
0x40085874 C FIELD 15w02 CCACT_01_CC2UACT (rw): CCP Output Action on CC2U event.
0x40085874 C FIELD 28w02 CCACT_01_SWFRCACT (rw): CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.
0x40085880 B REGISTER IFCTL_01[0] (rw): Input Filter Control Register
0x40085880 C FIELD 00w04 IFCTL_01_ISEL (rw): Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0x40085880 C FIELD 07w01 IFCTL_01_INV (rw): Input Inversion This bit controls whether the selected input is inverted.
0x40085880 C FIELD 08w02 IFCTL_01_FP (rw): Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.
0x40085880 C FIELD 11w01 IFCTL_01_CPV (rw): Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.
0x40085880 C FIELD 12w01 IFCTL_01_FE (rw): Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.
0x40085884 B REGISTER IFCTL_01[1] (rw): Input Filter Control Register
0x40085884 C FIELD 00w04 IFCTL_01_ISEL (rw): Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0x40085884 C FIELD 07w01 IFCTL_01_INV (rw): Input Inversion This bit controls whether the selected input is inverted.
0x40085884 C FIELD 08w02 IFCTL_01_FP (rw): Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.
0x40085884 C FIELD 11w01 IFCTL_01_CPV (rw): Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.
0x40085884 C FIELD 12w01 IFCTL_01_FE (rw): Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.
0x400858B0 B REGISTER TSEL (rw): Trigger Select
0x400858B0 C FIELD 00w05 TSEL_ETSEL (rw): External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use.
0x400858B0 C FIELD 09w01 TSEL_TE (rw): Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field
0x40086000 A PERIPHERAL TIMG1
0x40086400 B REGISTER FSUB_0 (rw): Subsciber Port 0
0x40086400 C FIELD 00w02 FSUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40086404 B REGISTER FSUB_1 (rw): Subscriber Port 1
0x40086404 C FIELD 00w02 FSUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40086444 B REGISTER FPUB_0 (rw): Publisher Port 0
0x40086444 C FIELD 00w02 FPUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40086448 B REGISTER FPUB_1 (rw): Publisher Port 1
0x40086448 C FIELD 00w02 FPUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40086800 B REGISTER PWREN (rw): Power enable
0x40086800 C FIELD 00w01 PWREN_ENABLE: Enable the power
0x40086800 C FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40086804 B REGISTER RSTCTL (wo): Reset Control
0x40086804 C FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x40086804 C FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x40086804 C FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40086814 B REGISTER STAT (ro): Status Register
0x40086814 C FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40087000 B REGISTER CLKDIV (rw): Clock Divider
0x40087000 C FIELD 00w03 CLKDIV_RATIO: Selects divide ratio of module clock
0x40087008 B REGISTER CLKSEL (rw): Clock Select for Ultra Low Power peripherals
0x40087008 C FIELD 01w01 CLKSEL_LFCLK_SEL (rw): Selects LFCLK as clock source if enabled
0x40087008 C FIELD 02w01 CLKSEL_MFCLK_SEL (rw): Selects MFCLK as clock source if enabled
0x40087008 C FIELD 03w01 CLKSEL_BUSCLK_SEL (rw): Selects BUSCLK as clock source if enabled
0x40087018 B REGISTER PDBGCTL (rw): Peripheral Debug Control
0x40087018 C FIELD 00w01 PDBGCTL_FREE (rw): Free run control
0x40087018 C FIELD 01w01 PDBGCTL_SOFT (rw): Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP'
0x40087020 B REGISTER IIDX (ro): Interrupt index
0x40087020 C FIELD 00w08 IIDX_STAT (ro): Interrupt index status
0x40087028 B REGISTER IMASK (rw): Interrupt mask
0x40087028 C FIELD 00w01 IMASK_Z: Zero Event mask
0x40087028 C FIELD 01w01 IMASK_L: Load Event mask
0x40087028 C FIELD 04w01 IMASK_CCD0: Capture or Compare DN event mask CCP0
0x40087028 C FIELD 05w01 IMASK_CCD1: Capture or Compare DN event mask CCP1
0x40087028 C FIELD 08w01 IMASK_CCU0: Capture or Compare UP event mask CCP0
0x40087028 C FIELD 09w01 IMASK_CCU1: Capture or Compare UP event mask CCP1
0x40087028 C FIELD 25w01 IMASK_TOV: Trigger Overflow Event mask
0x40087030 B REGISTER RIS (ro): Raw interrupt status
0x40087030 C FIELD 00w01 RIS_Z: Zero event generated an interrupt.
0x40087030 C FIELD 01w01 RIS_L: Load event generated an interrupt.
0x40087030 C FIELD 04w01 RIS_CCD0: Capture or compare down event generated an interrupt CCP0
0x40087030 C FIELD 05w01 RIS_CCD1: Capture or compare down event generated an interrupt CCP1
0x40087030 C FIELD 08w01 RIS_CCU0: Capture or compare up event generated an interrupt CCP0
0x40087030 C FIELD 09w01 RIS_CCU1: Capture or compare up event generated an interrupt CCP1
0x40087030 C FIELD 25w01 RIS_TOV: Trigger overflow
0x40087038 B REGISTER MIS (ro): Masked interrupt status
0x40087038 C FIELD 00w01 MIS_Z: Zero event generated an interrupt.
0x40087038 C FIELD 01w01 MIS_L: Load event generated an interrupt.
0x40087038 C FIELD 04w01 MIS_CCD0: Capture or compare down event generated an interrupt CCP0
0x40087038 C FIELD 05w01 MIS_CCD1: Capture or compare down event generated an interrupt CCP1
0x40087038 C FIELD 08w01 MIS_CCU0: Capture or compare up event generated an interrupt CCP0
0x40087038 C FIELD 09w01 MIS_CCU1: Capture or compare up event generated an interrupt CCP1
0x40087038 C FIELD 25w01 MIS_TOV: Trigger overflow
0x40087040 B REGISTER ISET (wo): Interrupt set
0x40087040 C FIELD 00w01 ISET_Z: Zero event SET
0x40087040 C FIELD 01w01 ISET_L: Load event SET
0x40087040 C FIELD 04w01 ISET_CCD0: Capture or compare down event SET
0x40087040 C FIELD 05w01 ISET_CCD1: Capture or compare down event SET
0x40087040 C FIELD 08w01 ISET_CCU0: Capture or compare up event SET
0x40087040 C FIELD 09w01 ISET_CCU1: Capture or compare up event SET
0x40087040 C FIELD 25w01 ISET_TOV: Trigger Overflow event SET
0x40087048 B REGISTER ICLR (wo): Interrupt clear
0x40087048 C FIELD 00w01 ICLR_Z: Zero event CLEAR
0x40087048 C FIELD 01w01 ICLR_L: Load event CLEAR
0x40087048 C FIELD 04w01 ICLR_CCD0: Capture or compare down event CLEAR
0x40087048 C FIELD 05w01 ICLR_CCD1: Capture or compare down event CLEAR
0x40087048 C FIELD 08w01 ICLR_CCU0: Capture or compare up event CLEAR
0x40087048 C FIELD 09w01 ICLR_CCU1: Capture or compare up event CLEAR
0x40087048 C FIELD 25w01 ICLR_TOV: Trigger Overflow event CLEAR
0x400870E0 B REGISTER EVT_MODE (rw): Event Mode
0x400870E0 C FIELD 00w02 EVT_MODE_EVT0_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]
0x400870E0 C FIELD 02w02 EVT_MODE_EVT1_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]
0x400870E0 C FIELD 04w02 EVT_MODE_EVT2_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]
0x400870FC B REGISTER DESC (ro): Module Description
0x400870FC C FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x400870FC C FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x400870FC C FIELD 08w04 DESC_INSTNUM: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x400870FC C FIELD 12w04 DESC_FEATUREVER: Feature Set for the module *instance*
0x400870FC C FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x40087100 B REGISTER CCPD (rw): CCP Direction
0x40087100 C FIELD 00w01 CCPD_C0CCP0: Counter CCP0
0x40087100 C FIELD 01w01 CCPD_C0CCP1: Counter CCP1
0x40087104 B REGISTER ODIS (rw): Output Disable
0x40087104 C FIELD 00w01 ODIS_C0CCP0 (rw): Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not
0x40087104 C FIELD 01w01 ODIS_C0CCP1 (rw): Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not
0x40087108 B REGISTER CCLKCTL (rw): Counter Clock Control Register
0x40087108 C FIELD 00w01 CCLKCTL_CLKEN (rw): Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock.
0x4008710C B REGISTER CPS (rw): Clock Prescale Register
0x4008710C C FIELD 00w08 CPS_PCNT (rw): Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock
0x40087110 B REGISTER CPSV (ro): Clock prescale count status register
0x40087110 C FIELD 00w08 CPSV_CPSVAL (ro): Current Prescale Count Value
0x40087114 B REGISTER CTTRIGCTL (rw): Timer Cross Trigger Control Register
0x40087114 C FIELD 00w01 CTTRIGCTL_CTEN (rw): Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register.
0x40087114 C FIELD 01w01 CTTRIGCTL_EVTCTEN (rw): Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path
0x40087114 C FIELD 16w04 CTTRIGCTL_EVTCTTRIGSEL (rw): Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path
0x4008711C B REGISTER CTTRIG (wo): Timer Cross Trigger Register
0x4008711C C FIELD 00w01 CTTRIG_TRIG (wo): Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance.
0x40087800 B REGISTER CTR (rw): Counter Register
0x40087800 C FIELD 00w16 CTR_CCTR (rw): Current Counter value
0x40087804 B REGISTER CTRCTL (rw): Counter Control Register
0x40087804 C FIELD 00w01 CTRCTL_EN (rw): Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively.
0x40087804 C FIELD 01w03 CTRCTL_REPEAT (rw): Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended.
0x40087804 C FIELD 04w02 CTRCTL_CM (rw): Count Mode
0x40087804 C FIELD 07w03 CTRCTL_CLC (rw): Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40087804 C FIELD 10w03 CTRCTL_CAC (rw): Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40087804 C FIELD 13w03 CTRCTL_CZC (rw): Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40087804 C FIELD 17w01 CTRCTL_DRB (rw): Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode.
0x40087804 C FIELD 28w02 CTRCTL_CVAE (rw): Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active.
0x40087808 B REGISTER LOAD (rw): Load Register
0x40087808 C FIELD 00w16 LOAD_LD (rw): Load Value
0x40087810 B REGISTER CC_01[0] (rw): Capture or Compare Register 0 to Capture or Compare Register 1
0x40087810 C FIELD 00w16 CC_01_CCVAL (rw): Capture or compare value
0x40087814 B REGISTER CC_01[1] (rw): Capture or Compare Register 0 to Capture or Compare Register 1
0x40087814 C FIELD 00w16 CC_01_CCVAL (rw): Capture or compare value
0x40087830 B REGISTER CCCTL_01[0] (rw): Capture or Compare Control Registers
0x40087830 C FIELD 00w03 CCCTL_01_CCOND (rw): Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved
0x40087830 C FIELD 04w03 CCCTL_01_ACOND (rw): Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved
0x40087830 C FIELD 08w03 CCCTL_01_LCOND (rw): Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved
0x40087830 C FIELD 12w03 CCCTL_01_ZCOND (rw): Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved
0x40087830 C FIELD 17w01 CCCTL_01_COC (rw): Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0x40087830 C FIELD 22w03 CCCTL_01_CC2SELU: Selects the source second CCU event.
0x40087830 C FIELD 26w03 CCCTL_01_CCACTUPD (rw): CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed
0x40087830 C FIELD 29w03 CCCTL_01_CC2SELD: Selects the source second CCD event.
0x40087834 B REGISTER CCCTL_01[1] (rw): Capture or Compare Control Registers
0x40087834 C FIELD 00w03 CCCTL_01_CCOND (rw): Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved
0x40087834 C FIELD 04w03 CCCTL_01_ACOND (rw): Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved
0x40087834 C FIELD 08w03 CCCTL_01_LCOND (rw): Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved
0x40087834 C FIELD 12w03 CCCTL_01_ZCOND (rw): Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved
0x40087834 C FIELD 17w01 CCCTL_01_COC (rw): Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0x40087834 C FIELD 22w03 CCCTL_01_CC2SELU: Selects the source second CCU event.
0x40087834 C FIELD 26w03 CCCTL_01_CCACTUPD (rw): CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed
0x40087834 C FIELD 29w03 CCCTL_01_CC2SELD: Selects the source second CCD event.
0x40087850 B REGISTER OCTL_01[0] (rw): CCP Output Control Registers
0x40087850 C FIELD 00w04 OCTL_01_CCPO (rw): CCP Output Source
0x40087850 C FIELD 04w01 OCTL_01_CCPOINV (rw): CCP Output Invert The output as selected by CCPO is conditionally inverted.
0x40087850 C FIELD 05w01 OCTL_01_CCPIV (rw): CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0x40087854 B REGISTER OCTL_01[1] (rw): CCP Output Control Registers
0x40087854 C FIELD 00w04 OCTL_01_CCPO (rw): CCP Output Source
0x40087854 C FIELD 04w01 OCTL_01_CCPOINV (rw): CCP Output Invert The output as selected by CCPO is conditionally inverted.
0x40087854 C FIELD 05w01 OCTL_01_CCPIV (rw): CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0x40087870 B REGISTER CCACT_01[0] (rw): Capture or Compare Action Registers
0x40087870 C FIELD 00w02 CCACT_01_ZACT (rw): CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0x40087870 C FIELD 03w02 CCACT_01_LACT (rw): CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0x40087870 C FIELD 06w02 CCACT_01_CDACT (rw): CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0x40087870 C FIELD 09w02 CCACT_01_CUACT (rw): CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0x40087870 C FIELD 12w02 CCACT_01_CC2DACT (rw): CCP Output Action on CC2D event.
0x40087870 C FIELD 15w02 CCACT_01_CC2UACT (rw): CCP Output Action on CC2U event.
0x40087870 C FIELD 28w02 CCACT_01_SWFRCACT (rw): CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.
0x40087874 B REGISTER CCACT_01[1] (rw): Capture or Compare Action Registers
0x40087874 C FIELD 00w02 CCACT_01_ZACT (rw): CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0x40087874 C FIELD 03w02 CCACT_01_LACT (rw): CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0x40087874 C FIELD 06w02 CCACT_01_CDACT (rw): CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0x40087874 C FIELD 09w02 CCACT_01_CUACT (rw): CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0x40087874 C FIELD 12w02 CCACT_01_CC2DACT (rw): CCP Output Action on CC2D event.
0x40087874 C FIELD 15w02 CCACT_01_CC2UACT (rw): CCP Output Action on CC2U event.
0x40087874 C FIELD 28w02 CCACT_01_SWFRCACT (rw): CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.
0x40087880 B REGISTER IFCTL_01[0] (rw): Input Filter Control Register
0x40087880 C FIELD 00w04 IFCTL_01_ISEL (rw): Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0x40087880 C FIELD 07w01 IFCTL_01_INV (rw): Input Inversion This bit controls whether the selected input is inverted.
0x40087880 C FIELD 08w02 IFCTL_01_FP (rw): Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.
0x40087880 C FIELD 11w01 IFCTL_01_CPV (rw): Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.
0x40087880 C FIELD 12w01 IFCTL_01_FE (rw): Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.
0x40087884 B REGISTER IFCTL_01[1] (rw): Input Filter Control Register
0x40087884 C FIELD 00w04 IFCTL_01_ISEL (rw): Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0x40087884 C FIELD 07w01 IFCTL_01_INV (rw): Input Inversion This bit controls whether the selected input is inverted.
0x40087884 C FIELD 08w02 IFCTL_01_FP (rw): Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.
0x40087884 C FIELD 11w01 IFCTL_01_CPV (rw): Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.
0x40087884 C FIELD 12w01 IFCTL_01_FE (rw): Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.
0x400878B0 B REGISTER TSEL (rw): Trigger Select
0x400878B0 C FIELD 00w05 TSEL_ETSEL (rw): External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use.
0x400878B0 C FIELD 09w01 TSEL_TE (rw): Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field
0x40088000 A PERIPHERAL TIMG2
0x40088400 B REGISTER FSUB_0 (rw): Subsciber Port 0
0x40088400 C FIELD 00w02 FSUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40088404 B REGISTER FSUB_1 (rw): Subscriber Port 1
0x40088404 C FIELD 00w02 FSUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40088444 B REGISTER FPUB_0 (rw): Publisher Port 0
0x40088444 C FIELD 00w02 FPUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40088448 B REGISTER FPUB_1 (rw): Publisher Port 1
0x40088448 C FIELD 00w02 FPUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40088800 B REGISTER PWREN (rw): Power enable
0x40088800 C FIELD 00w01 PWREN_ENABLE: Enable the power
0x40088800 C FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40088804 B REGISTER RSTCTL (wo): Reset Control
0x40088804 C FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x40088804 C FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x40088804 C FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40088814 B REGISTER STAT (ro): Status Register
0x40088814 C FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40089000 B REGISTER CLKDIV (rw): Clock Divider
0x40089000 C FIELD 00w03 CLKDIV_RATIO: Selects divide ratio of module clock
0x40089008 B REGISTER CLKSEL (rw): Clock Select for Ultra Low Power peripherals
0x40089008 C FIELD 01w01 CLKSEL_LFCLK_SEL (rw): Selects LFCLK as clock source if enabled
0x40089008 C FIELD 02w01 CLKSEL_MFCLK_SEL (rw): Selects MFCLK as clock source if enabled
0x40089008 C FIELD 03w01 CLKSEL_BUSCLK_SEL (rw): Selects BUSCLK as clock source if enabled
0x40089018 B REGISTER PDBGCTL (rw): Peripheral Debug Control
0x40089018 C FIELD 00w01 PDBGCTL_FREE (rw): Free run control
0x40089018 C FIELD 01w01 PDBGCTL_SOFT (rw): Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP'
0x40089020 B REGISTER IIDX (ro): Interrupt index
0x40089020 C FIELD 00w08 IIDX_STAT (ro): Interrupt index status
0x40089028 B REGISTER IMASK (rw): Interrupt mask
0x40089028 C FIELD 00w01 IMASK_Z: Zero Event mask
0x40089028 C FIELD 01w01 IMASK_L: Load Event mask
0x40089028 C FIELD 04w01 IMASK_CCD0: Capture or Compare DN event mask CCP0
0x40089028 C FIELD 05w01 IMASK_CCD1: Capture or Compare DN event mask CCP1
0x40089028 C FIELD 08w01 IMASK_CCU0: Capture or Compare UP event mask CCP0
0x40089028 C FIELD 09w01 IMASK_CCU1: Capture or Compare UP event mask CCP1
0x40089028 C FIELD 25w01 IMASK_TOV: Trigger Overflow Event mask
0x40089030 B REGISTER RIS (ro): Raw interrupt status
0x40089030 C FIELD 00w01 RIS_Z: Zero event generated an interrupt.
0x40089030 C FIELD 01w01 RIS_L: Load event generated an interrupt.
0x40089030 C FIELD 04w01 RIS_CCD0: Capture or compare down event generated an interrupt CCP0
0x40089030 C FIELD 05w01 RIS_CCD1: Capture or compare down event generated an interrupt CCP1
0x40089030 C FIELD 08w01 RIS_CCU0: Capture or compare up event generated an interrupt CCP0
0x40089030 C FIELD 09w01 RIS_CCU1: Capture or compare up event generated an interrupt CCP1
0x40089030 C FIELD 25w01 RIS_TOV: Trigger overflow
0x40089038 B REGISTER MIS (ro): Masked interrupt status
0x40089038 C FIELD 00w01 MIS_Z: Zero event generated an interrupt.
0x40089038 C FIELD 01w01 MIS_L: Load event generated an interrupt.
0x40089038 C FIELD 04w01 MIS_CCD0: Capture or compare down event generated an interrupt CCP0
0x40089038 C FIELD 05w01 MIS_CCD1: Capture or compare down event generated an interrupt CCP1
0x40089038 C FIELD 08w01 MIS_CCU0: Capture or compare up event generated an interrupt CCP0
0x40089038 C FIELD 09w01 MIS_CCU1: Capture or compare up event generated an interrupt CCP1
0x40089038 C FIELD 25w01 MIS_TOV: Trigger overflow
0x40089040 B REGISTER ISET (wo): Interrupt set
0x40089040 C FIELD 00w01 ISET_Z: Zero event SET
0x40089040 C FIELD 01w01 ISET_L: Load event SET
0x40089040 C FIELD 04w01 ISET_CCD0: Capture or compare down event SET
0x40089040 C FIELD 05w01 ISET_CCD1: Capture or compare down event SET
0x40089040 C FIELD 08w01 ISET_CCU0: Capture or compare up event SET
0x40089040 C FIELD 09w01 ISET_CCU1: Capture or compare up event SET
0x40089040 C FIELD 25w01 ISET_TOV: Trigger Overflow event SET
0x40089048 B REGISTER ICLR (wo): Interrupt clear
0x40089048 C FIELD 00w01 ICLR_Z: Zero event CLEAR
0x40089048 C FIELD 01w01 ICLR_L: Load event CLEAR
0x40089048 C FIELD 04w01 ICLR_CCD0: Capture or compare down event CLEAR
0x40089048 C FIELD 05w01 ICLR_CCD1: Capture or compare down event CLEAR
0x40089048 C FIELD 08w01 ICLR_CCU0: Capture or compare up event CLEAR
0x40089048 C FIELD 09w01 ICLR_CCU1: Capture or compare up event CLEAR
0x40089048 C FIELD 25w01 ICLR_TOV: Trigger Overflow event CLEAR
0x400890E0 B REGISTER EVT_MODE (rw): Event Mode
0x400890E0 C FIELD 00w02 EVT_MODE_EVT0_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]
0x400890E0 C FIELD 02w02 EVT_MODE_EVT1_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]
0x400890E0 C FIELD 04w02 EVT_MODE_EVT2_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]
0x400890FC B REGISTER DESC (ro): Module Description
0x400890FC C FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x400890FC C FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x400890FC C FIELD 08w04 DESC_INSTNUM: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x400890FC C FIELD 12w04 DESC_FEATUREVER: Feature Set for the module *instance*
0x400890FC C FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x40089100 B REGISTER CCPD (rw): CCP Direction
0x40089100 C FIELD 00w01 CCPD_C0CCP0: Counter CCP0
0x40089100 C FIELD 01w01 CCPD_C0CCP1: Counter CCP1
0x40089104 B REGISTER ODIS (rw): Output Disable
0x40089104 C FIELD 00w01 ODIS_C0CCP0 (rw): Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not
0x40089104 C FIELD 01w01 ODIS_C0CCP1 (rw): Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not
0x40089108 B REGISTER CCLKCTL (rw): Counter Clock Control Register
0x40089108 C FIELD 00w01 CCLKCTL_CLKEN (rw): Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock.
0x4008910C B REGISTER CPS (rw): Clock Prescale Register
0x4008910C C FIELD 00w08 CPS_PCNT (rw): Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock
0x40089110 B REGISTER CPSV (ro): Clock prescale count status register
0x40089110 C FIELD 00w08 CPSV_CPSVAL (ro): Current Prescale Count Value
0x40089114 B REGISTER CTTRIGCTL (rw): Timer Cross Trigger Control Register
0x40089114 C FIELD 00w01 CTTRIGCTL_CTEN (rw): Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register.
0x40089114 C FIELD 01w01 CTTRIGCTL_EVTCTEN (rw): Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path
0x40089114 C FIELD 16w04 CTTRIGCTL_EVTCTTRIGSEL (rw): Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path
0x4008911C B REGISTER CTTRIG (wo): Timer Cross Trigger Register
0x4008911C C FIELD 00w01 CTTRIG_TRIG (wo): Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance.
0x40089800 B REGISTER CTR (rw): Counter Register
0x40089800 C FIELD 00w16 CTR_CCTR (rw): Current Counter value
0x40089804 B REGISTER CTRCTL (rw): Counter Control Register
0x40089804 C FIELD 00w01 CTRCTL_EN (rw): Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively.
0x40089804 C FIELD 01w03 CTRCTL_REPEAT (rw): Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended.
0x40089804 C FIELD 04w02 CTRCTL_CM (rw): Count Mode
0x40089804 C FIELD 07w03 CTRCTL_CLC (rw): Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40089804 C FIELD 10w03 CTRCTL_CAC (rw): Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40089804 C FIELD 13w03 CTRCTL_CZC (rw): Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40089804 C FIELD 17w01 CTRCTL_DRB (rw): Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode.
0x40089804 C FIELD 28w02 CTRCTL_CVAE (rw): Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active.
0x40089808 B REGISTER LOAD (rw): Load Register
0x40089808 C FIELD 00w16 LOAD_LD (rw): Load Value
0x40089810 B REGISTER CC_01[0] (rw): Capture or Compare Register 0 to Capture or Compare Register 1
0x40089810 C FIELD 00w16 CC_01_CCVAL (rw): Capture or compare value
0x40089814 B REGISTER CC_01[1] (rw): Capture or Compare Register 0 to Capture or Compare Register 1
0x40089814 C FIELD 00w16 CC_01_CCVAL (rw): Capture or compare value
0x40089830 B REGISTER CCCTL_01[0] (rw): Capture or Compare Control Registers
0x40089830 C FIELD 00w03 CCCTL_01_CCOND (rw): Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved
0x40089830 C FIELD 04w03 CCCTL_01_ACOND (rw): Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved
0x40089830 C FIELD 08w03 CCCTL_01_LCOND (rw): Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved
0x40089830 C FIELD 12w03 CCCTL_01_ZCOND (rw): Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved
0x40089830 C FIELD 17w01 CCCTL_01_COC (rw): Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0x40089830 C FIELD 22w03 CCCTL_01_CC2SELU: Selects the source second CCU event.
0x40089830 C FIELD 26w03 CCCTL_01_CCACTUPD (rw): CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed
0x40089830 C FIELD 29w03 CCCTL_01_CC2SELD: Selects the source second CCD event.
0x40089834 B REGISTER CCCTL_01[1] (rw): Capture or Compare Control Registers
0x40089834 C FIELD 00w03 CCCTL_01_CCOND (rw): Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved
0x40089834 C FIELD 04w03 CCCTL_01_ACOND (rw): Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved
0x40089834 C FIELD 08w03 CCCTL_01_LCOND (rw): Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved
0x40089834 C FIELD 12w03 CCCTL_01_ZCOND (rw): Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved
0x40089834 C FIELD 17w01 CCCTL_01_COC (rw): Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0x40089834 C FIELD 22w03 CCCTL_01_CC2SELU: Selects the source second CCU event.
0x40089834 C FIELD 26w03 CCCTL_01_CCACTUPD (rw): CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed
0x40089834 C FIELD 29w03 CCCTL_01_CC2SELD: Selects the source second CCD event.
0x40089850 B REGISTER OCTL_01[0] (rw): CCP Output Control Registers
0x40089850 C FIELD 00w04 OCTL_01_CCPO (rw): CCP Output Source
0x40089850 C FIELD 04w01 OCTL_01_CCPOINV (rw): CCP Output Invert The output as selected by CCPO is conditionally inverted.
0x40089850 C FIELD 05w01 OCTL_01_CCPIV (rw): CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0x40089854 B REGISTER OCTL_01[1] (rw): CCP Output Control Registers
0x40089854 C FIELD 00w04 OCTL_01_CCPO (rw): CCP Output Source
0x40089854 C FIELD 04w01 OCTL_01_CCPOINV (rw): CCP Output Invert The output as selected by CCPO is conditionally inverted.
0x40089854 C FIELD 05w01 OCTL_01_CCPIV (rw): CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0x40089870 B REGISTER CCACT_01[0] (rw): Capture or Compare Action Registers
0x40089870 C FIELD 00w02 CCACT_01_ZACT (rw): CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0x40089870 C FIELD 03w02 CCACT_01_LACT (rw): CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0x40089870 C FIELD 06w02 CCACT_01_CDACT (rw): CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0x40089870 C FIELD 09w02 CCACT_01_CUACT (rw): CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0x40089870 C FIELD 12w02 CCACT_01_CC2DACT (rw): CCP Output Action on CC2D event.
0x40089870 C FIELD 15w02 CCACT_01_CC2UACT (rw): CCP Output Action on CC2U event.
0x40089870 C FIELD 28w02 CCACT_01_SWFRCACT (rw): CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.
0x40089874 B REGISTER CCACT_01[1] (rw): Capture or Compare Action Registers
0x40089874 C FIELD 00w02 CCACT_01_ZACT (rw): CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0x40089874 C FIELD 03w02 CCACT_01_LACT (rw): CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0x40089874 C FIELD 06w02 CCACT_01_CDACT (rw): CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0x40089874 C FIELD 09w02 CCACT_01_CUACT (rw): CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0x40089874 C FIELD 12w02 CCACT_01_CC2DACT (rw): CCP Output Action on CC2D event.
0x40089874 C FIELD 15w02 CCACT_01_CC2UACT (rw): CCP Output Action on CC2U event.
0x40089874 C FIELD 28w02 CCACT_01_SWFRCACT (rw): CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.
0x40089880 B REGISTER IFCTL_01[0] (rw): Input Filter Control Register
0x40089880 C FIELD 00w04 IFCTL_01_ISEL (rw): Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0x40089880 C FIELD 07w01 IFCTL_01_INV (rw): Input Inversion This bit controls whether the selected input is inverted.
0x40089880 C FIELD 08w02 IFCTL_01_FP (rw): Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.
0x40089880 C FIELD 11w01 IFCTL_01_CPV (rw): Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.
0x40089880 C FIELD 12w01 IFCTL_01_FE (rw): Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.
0x40089884 B REGISTER IFCTL_01[1] (rw): Input Filter Control Register
0x40089884 C FIELD 00w04 IFCTL_01_ISEL (rw): Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0x40089884 C FIELD 07w01 IFCTL_01_INV (rw): Input Inversion This bit controls whether the selected input is inverted.
0x40089884 C FIELD 08w02 IFCTL_01_FP (rw): Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.
0x40089884 C FIELD 11w01 IFCTL_01_CPV (rw): Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.
0x40089884 C FIELD 12w01 IFCTL_01_FE (rw): Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.
0x400898B0 B REGISTER TSEL (rw): Trigger Select
0x400898B0 C FIELD 00w05 TSEL_ETSEL (rw): External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use.
0x400898B0 C FIELD 09w01 TSEL_TE (rw): Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field
0x4008C000 A PERIPHERAL TIMG4
0x4008C400 B REGISTER FSUB_0 (rw): Subsciber Port 0
0x4008C400 C FIELD 00w02 FSUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x4008C404 B REGISTER FSUB_1 (rw): Subscriber Port 1
0x4008C404 C FIELD 00w02 FSUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x4008C444 B REGISTER FPUB_0 (rw): Publisher Port 0
0x4008C444 C FIELD 00w02 FPUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x4008C448 B REGISTER FPUB_1 (rw): Publisher Port 1
0x4008C448 C FIELD 00w02 FPUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x4008C800 B REGISTER PWREN (rw): Power enable
0x4008C800 C FIELD 00w01 PWREN_ENABLE: Enable the power
0x4008C800 C FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x4008C804 B REGISTER RSTCTL (wo): Reset Control
0x4008C804 C FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x4008C804 C FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x4008C804 C FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x4008C814 B REGISTER STAT (ro): Status Register
0x4008C814 C FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x4008D000 B REGISTER CLKDIV (rw): Clock Divider
0x4008D000 C FIELD 00w03 CLKDIV_RATIO: Selects divide ratio of module clock
0x4008D008 B REGISTER CLKSEL (rw): Clock Select for Ultra Low Power peripherals
0x4008D008 C FIELD 01w01 CLKSEL_LFCLK_SEL (rw): Selects LFCLK as clock source if enabled
0x4008D008 C FIELD 02w01 CLKSEL_MFCLK_SEL (rw): Selects MFCLK as clock source if enabled
0x4008D008 C FIELD 03w01 CLKSEL_BUSCLK_SEL (rw): Selects BUSCLK as clock source if enabled
0x4008D018 B REGISTER PDBGCTL (rw): Peripheral Debug Control
0x4008D018 C FIELD 00w01 PDBGCTL_FREE (rw): Free run control
0x4008D018 C FIELD 01w01 PDBGCTL_SOFT (rw): Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP'
0x4008D020 B REGISTER IIDX (ro): Interrupt index
0x4008D020 C FIELD 00w08 IIDX_STAT (ro): Interrupt index status
0x4008D028 B REGISTER IMASK (rw): Interrupt mask
0x4008D028 C FIELD 00w01 IMASK_Z: Zero Event mask
0x4008D028 C FIELD 01w01 IMASK_L: Load Event mask
0x4008D028 C FIELD 04w01 IMASK_CCD0: Capture or Compare DN event mask CCP0
0x4008D028 C FIELD 05w01 IMASK_CCD1: Capture or Compare DN event mask CCP1
0x4008D028 C FIELD 08w01 IMASK_CCU0: Capture or Compare UP event mask CCP0
0x4008D028 C FIELD 09w01 IMASK_CCU1: Capture or Compare UP event mask CCP1
0x4008D028 C FIELD 25w01 IMASK_TOV: Trigger Overflow Event mask
0x4008D030 B REGISTER RIS (ro): Raw interrupt status
0x4008D030 C FIELD 00w01 RIS_Z: Zero event generated an interrupt.
0x4008D030 C FIELD 01w01 RIS_L: Load event generated an interrupt.
0x4008D030 C FIELD 04w01 RIS_CCD0: Capture or compare down event generated an interrupt CCP0
0x4008D030 C FIELD 05w01 RIS_CCD1: Capture or compare down event generated an interrupt CCP1
0x4008D030 C FIELD 08w01 RIS_CCU0: Capture or compare up event generated an interrupt CCP0
0x4008D030 C FIELD 09w01 RIS_CCU1: Capture or compare up event generated an interrupt CCP1
0x4008D030 C FIELD 25w01 RIS_TOV: Trigger overflow
0x4008D038 B REGISTER MIS (ro): Masked interrupt status
0x4008D038 C FIELD 00w01 MIS_Z: Zero event generated an interrupt.
0x4008D038 C FIELD 01w01 MIS_L: Load event generated an interrupt.
0x4008D038 C FIELD 04w01 MIS_CCD0: Capture or compare down event generated an interrupt CCP0
0x4008D038 C FIELD 05w01 MIS_CCD1: Capture or compare down event generated an interrupt CCP1
0x4008D038 C FIELD 08w01 MIS_CCU0: Capture or compare up event generated an interrupt CCP0
0x4008D038 C FIELD 09w01 MIS_CCU1: Capture or compare up event generated an interrupt CCP1
0x4008D038 C FIELD 12w01 MIS_CCD4: Compare down event generated an interrupt CCP4
0x4008D038 C FIELD 13w01 MIS_CCD5: Compare down event generated an interrupt CCP5
0x4008D038 C FIELD 14w01 MIS_CCU4: Compare up event generated an interrupt CCP4
0x4008D038 C FIELD 15w01 MIS_CCU5: Compare up event generated an interrupt CCP5
0x4008D038 C FIELD 25w01 MIS_TOV: Trigger overflow
0x4008D040 B REGISTER ISET (wo): Interrupt set
0x4008D040 C FIELD 00w01 ISET_Z: Zero event SET
0x4008D040 C FIELD 01w01 ISET_L: Load event SET
0x4008D040 C FIELD 04w01 ISET_CCD0: Capture or compare down event SET
0x4008D040 C FIELD 05w01 ISET_CCD1: Capture or compare down event SET
0x4008D040 C FIELD 08w01 ISET_CCU0: Capture or compare up event SET
0x4008D040 C FIELD 09w01 ISET_CCU1: Capture or compare up event SET
0x4008D040 C FIELD 25w01 ISET_TOV: Trigger Overflow event SET
0x4008D048 B REGISTER ICLR (wo): Interrupt clear
0x4008D048 C FIELD 00w01 ICLR_Z: Zero event CLEAR
0x4008D048 C FIELD 01w01 ICLR_L: Load event CLEAR
0x4008D048 C FIELD 04w01 ICLR_CCD0: Capture or compare down event CLEAR
0x4008D048 C FIELD 05w01 ICLR_CCD1: Capture or compare down event CLEAR
0x4008D048 C FIELD 08w01 ICLR_CCU0: Capture or compare up event CLEAR
0x4008D048 C FIELD 09w01 ICLR_CCU1: Capture or compare up event CLEAR
0x4008D048 C FIELD 25w01 ICLR_TOV: Trigger Overflow event CLEAR
0x4008D0E0 B REGISTER EVT_MODE (rw): Event Mode
0x4008D0E0 C FIELD 00w02 EVT_MODE_EVT0_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]
0x4008D0E0 C FIELD 02w02 EVT_MODE_EVT1_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]
0x4008D0E0 C FIELD 04w02 EVT_MODE_EVT2_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]
0x4008D0FC B REGISTER DESC (ro): Module Description
0x4008D0FC C FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x4008D0FC C FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x4008D0FC C FIELD 08w04 DESC_INSTNUM: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x4008D0FC C FIELD 12w04 DESC_FEATUREVER: Feature Set for the module *instance*
0x4008D0FC C FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x4008D100 B REGISTER CCPD (rw): CCP Direction
0x4008D100 C FIELD 00w01 CCPD_C0CCP0: Counter CCP0
0x4008D100 C FIELD 01w01 CCPD_C0CCP1: Counter CCP1
0x4008D104 B REGISTER ODIS (rw): Output Disable
0x4008D104 C FIELD 00w01 ODIS_C0CCP0 (rw): Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not
0x4008D104 C FIELD 01w01 ODIS_C0CCP1 (rw): Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not
0x4008D108 B REGISTER CCLKCTL (rw): Counter Clock Control Register
0x4008D108 C FIELD 00w01 CCLKCTL_CLKEN (rw): Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock.
0x4008D10C B REGISTER CPS (rw): Clock Prescale Register
0x4008D10C C FIELD 00w08 CPS_PCNT (rw): Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock
0x4008D110 B REGISTER CPSV (ro): Clock prescale count status register
0x4008D110 C FIELD 00w08 CPSV_CPSVAL (ro): Current Prescale Count Value
0x4008D114 B REGISTER CTTRIGCTL (rw): Timer Cross Trigger Control Register
0x4008D114 C FIELD 00w01 CTTRIGCTL_CTEN (rw): Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register.
0x4008D114 C FIELD 01w01 CTTRIGCTL_EVTCTEN (rw): Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path
0x4008D114 C FIELD 16w04 CTTRIGCTL_EVTCTTRIGSEL (rw): Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path
0x4008D11C B REGISTER CTTRIG (wo): Timer Cross Trigger Register
0x4008D11C C FIELD 00w01 CTTRIG_TRIG (wo): Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance.
0x4008D124 B REGISTER GCTL (rw): Shadow to active load mask
0x4008D124 C FIELD 00w01 GCTL_SHDWLDEN (rw): Enables shadow to active load of bufferred registers and register fields.
0x4008D800 B REGISTER CTR (rw): Counter Register
0x4008D800 C FIELD 00w16 CTR_CCTR (rw): Current Counter value
0x4008D804 B REGISTER CTRCTL (rw): Counter Control Register
0x4008D804 C FIELD 00w01 CTRCTL_EN (rw): Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively.
0x4008D804 C FIELD 01w03 CTRCTL_REPEAT (rw): Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended.
0x4008D804 C FIELD 04w02 CTRCTL_CM (rw): Count Mode
0x4008D804 C FIELD 07w03 CTRCTL_CLC (rw): Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x4008D804 C FIELD 10w03 CTRCTL_CAC (rw): Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x4008D804 C FIELD 13w03 CTRCTL_CZC (rw): Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x4008D804 C FIELD 17w01 CTRCTL_DRB (rw): Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode.
0x4008D804 C FIELD 28w02 CTRCTL_CVAE (rw): Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active.
0x4008D808 B REGISTER LOAD (rw): Load Register
0x4008D808 C FIELD 00w16 LOAD_LD (rw): Load Value
0x4008D810 B REGISTER CC_01[0] (rw): Capture or Compare Register 0 to Capture or Compare Register 1
0x4008D810 C FIELD 00w16 CC_01_CCVAL (rw): Capture or compare value
0x4008D814 B REGISTER CC_01[1] (rw): Capture or Compare Register 0 to Capture or Compare Register 1
0x4008D814 C FIELD 00w16 CC_01_CCVAL (rw): Capture or compare value
0x4008D830 B REGISTER CCCTL_01[0] (rw): Capture or Compare Control Registers
0x4008D830 C FIELD 00w03 CCCTL_01_CCOND (rw): Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved
0x4008D830 C FIELD 04w03 CCCTL_01_ACOND (rw): Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved
0x4008D830 C FIELD 08w03 CCCTL_01_LCOND (rw): Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved
0x4008D830 C FIELD 12w03 CCCTL_01_ZCOND (rw): Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved
0x4008D830 C FIELD 17w01 CCCTL_01_COC (rw): Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0x4008D830 C FIELD 18w03 CCCTL_01_CCUPD (rw): Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0).
0x4008D830 C FIELD 22w03 CCCTL_01_CC2SELU: Selects the source second CCU event.
0x4008D830 C FIELD 26w03 CCCTL_01_CCACTUPD (rw): CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed
0x4008D830 C FIELD 29w03 CCCTL_01_CC2SELD: Selects the source second CCD event.
0x4008D834 B REGISTER CCCTL_01[1] (rw): Capture or Compare Control Registers
0x4008D834 C FIELD 00w03 CCCTL_01_CCOND (rw): Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved
0x4008D834 C FIELD 04w03 CCCTL_01_ACOND (rw): Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved
0x4008D834 C FIELD 08w03 CCCTL_01_LCOND (rw): Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved
0x4008D834 C FIELD 12w03 CCCTL_01_ZCOND (rw): Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved
0x4008D834 C FIELD 17w01 CCCTL_01_COC (rw): Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0x4008D834 C FIELD 18w03 CCCTL_01_CCUPD (rw): Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0).
0x4008D834 C FIELD 22w03 CCCTL_01_CC2SELU: Selects the source second CCU event.
0x4008D834 C FIELD 26w03 CCCTL_01_CCACTUPD (rw): CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed
0x4008D834 C FIELD 29w03 CCCTL_01_CC2SELD: Selects the source second CCD event.
0x4008D850 B REGISTER OCTL_01[0] (rw): CCP Output Control Registers
0x4008D850 C FIELD 00w04 OCTL_01_CCPO (rw): CCP Output Source
0x4008D850 C FIELD 04w01 OCTL_01_CCPOINV (rw): CCP Output Invert The output as selected by CCPO is conditionally inverted.
0x4008D850 C FIELD 05w01 OCTL_01_CCPIV (rw): CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0x4008D854 B REGISTER OCTL_01[1] (rw): CCP Output Control Registers
0x4008D854 C FIELD 00w04 OCTL_01_CCPO (rw): CCP Output Source
0x4008D854 C FIELD 04w01 OCTL_01_CCPOINV (rw): CCP Output Invert The output as selected by CCPO is conditionally inverted.
0x4008D854 C FIELD 05w01 OCTL_01_CCPIV (rw): CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0x4008D870 B REGISTER CCACT_01[0] (rw): Capture or Compare Action Registers
0x4008D870 C FIELD 00w02 CCACT_01_ZACT (rw): CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0x4008D870 C FIELD 03w02 CCACT_01_LACT (rw): CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0x4008D870 C FIELD 06w02 CCACT_01_CDACT (rw): CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0x4008D870 C FIELD 09w02 CCACT_01_CUACT (rw): CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0x4008D870 C FIELD 12w02 CCACT_01_CC2DACT (rw): CCP Output Action on CC2D event.
0x4008D870 C FIELD 15w02 CCACT_01_CC2UACT (rw): CCP Output Action on CC2U event.
0x4008D870 C FIELD 28w02 CCACT_01_SWFRCACT (rw): CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.
0x4008D874 B REGISTER CCACT_01[1] (rw): Capture or Compare Action Registers
0x4008D874 C FIELD 00w02 CCACT_01_ZACT (rw): CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0x4008D874 C FIELD 03w02 CCACT_01_LACT (rw): CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0x4008D874 C FIELD 06w02 CCACT_01_CDACT (rw): CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0x4008D874 C FIELD 09w02 CCACT_01_CUACT (rw): CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0x4008D874 C FIELD 12w02 CCACT_01_CC2DACT (rw): CCP Output Action on CC2D event.
0x4008D874 C FIELD 15w02 CCACT_01_CC2UACT (rw): CCP Output Action on CC2U event.
0x4008D874 C FIELD 28w02 CCACT_01_SWFRCACT (rw): CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.
0x4008D880 B REGISTER IFCTL_01[0] (rw): Input Filter Control Register
0x4008D880 C FIELD 00w04 IFCTL_01_ISEL (rw): Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0x4008D880 C FIELD 07w01 IFCTL_01_INV (rw): Input Inversion This bit controls whether the selected input is inverted.
0x4008D880 C FIELD 08w02 IFCTL_01_FP (rw): Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.
0x4008D880 C FIELD 11w01 IFCTL_01_CPV (rw): Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.
0x4008D880 C FIELD 12w01 IFCTL_01_FE (rw): Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.
0x4008D884 B REGISTER IFCTL_01[1] (rw): Input Filter Control Register
0x4008D884 C FIELD 00w04 IFCTL_01_ISEL (rw): Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0x4008D884 C FIELD 07w01 IFCTL_01_INV (rw): Input Inversion This bit controls whether the selected input is inverted.
0x4008D884 C FIELD 08w02 IFCTL_01_FP (rw): Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.
0x4008D884 C FIELD 11w01 IFCTL_01_CPV (rw): Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.
0x4008D884 C FIELD 12w01 IFCTL_01_FE (rw): Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.
0x4008D8B0 B REGISTER TSEL (rw): Trigger Select
0x4008D8B0 C FIELD 00w05 TSEL_ETSEL (rw): External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use.
0x4008D8B0 C FIELD 09w01 TSEL_TE (rw): Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field
0x400A0000 A PERIPHERAL GPIOA
0x400A0400 B REGISTER FSUB_0 (rw): Subsciber Port 0
0x400A0400 C FIELD 00w02 FSUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x400A0404 B REGISTER FSUB_1 (rw): Subscriber Port 1
0x400A0404 C FIELD 00w02 FSUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x400A0444 B REGISTER FPUB_0 (rw): Publisher Port 0
0x400A0444 C FIELD 00w02 FPUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x400A0448 B REGISTER FPUB_1 (rw): Publisher Port 1
0x400A0448 C FIELD 00w02 FPUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x400A0800 B REGISTER PWREN (rw): Power enable
0x400A0800 C FIELD 00w01 PWREN_ENABLE: Enable the power
0x400A0800 C FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x400A0804 B REGISTER RSTCTL (wo): Reset Control
0x400A0804 C FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x400A0804 C FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x400A0804 C FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x400A0814 B REGISTER STAT (ro): Status Register
0x400A0814 C FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x400A1010 B REGISTER CLKOVR (rw): Clock Override